base.cc revision 8786
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Definition of BaseCache functions. 342810SN/A */ 352810SN/A 363348SN/A#include "cpu/base.hh" 373348SN/A#include "cpu/smt.hh" 388232Snate@binkert.org#include "debug/Cache.hh" 395338Sstever@gmail.com#include "mem/cache/base.hh" 405338Sstever@gmail.com#include "mem/cache/mshr.hh" 418786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 422810SN/A 432810SN/Ausing namespace std; 442810SN/A 454965SN/ABaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 466122SSteve.Reinhardt@amd.com const std::string &_label) 475314SN/A : SimpleTimingPort(_name, _cache), cache(_cache), 485314SN/A label(_label), otherPort(NULL), 496122SSteve.Reinhardt@amd.com blocked(false), mustSendRetry(false) 502810SN/A{ 514475SN/A} 524475SN/A 534475SN/A 545034SN/ABaseCache::BaseCache(const Params *p) 555034SN/A : MemObject(p), 565314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 575314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 584628SN/A MSHRQueue_WriteBuffer), 595034SN/A blkSize(p->block_size), 605034SN/A hitLatency(p->latency), 615034SN/A numTarget(p->tgts_per_mshr), 626122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 638134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 644626SN/A blocked(0), 654626SN/A noTargetMSHR(NULL), 665034SN/A missCount(p->max_miss_count), 676122SSteve.Reinhardt@amd.com drainEvent(NULL), 686978SLisa.Hsu@amd.com addrRange(p->addr_range), 696978SLisa.Hsu@amd.com _numCpus(p->num_cpus) 704458SN/A{ 712810SN/A} 722810SN/A 732811SN/Avoid 742810SN/ABaseCache::CachePort::recvStatusChange(Port::Status status) 752810SN/A{ 764458SN/A if (status == Port::RangeChange) { 774458SN/A otherPort->sendStatusChange(Port::RangeChange); 784458SN/A } 792810SN/A} 802810SN/A 815314SN/A 825314SN/Abool 835314SN/ABaseCache::CachePort::checkFunctional(PacketPtr pkt) 845314SN/A{ 855314SN/A pkt->pushLabel(label); 865314SN/A bool done = SimpleTimingPort::checkFunctional(pkt); 875314SN/A pkt->popLabel(); 885314SN/A return done; 895314SN/A} 905314SN/A 915314SN/A 926227Snate@binkert.orgunsigned 936227Snate@binkert.orgBaseCache::CachePort::deviceBlockSize() const 942810SN/A{ 952810SN/A return cache->getBlockSize(); 962810SN/A} 972810SN/A 983606SN/A 994458SN/Abool 1004458SN/ABaseCache::CachePort::recvRetryCommon() 1013013SN/A{ 1023236SN/A assert(waitingOnRetry); 1034458SN/A waitingOnRetry = false; 1044458SN/A return false; 1054458SN/A} 1063246SN/A 1073309SN/A 1083013SN/Avoid 1092810SN/ABaseCache::CachePort::setBlocked() 1102810SN/A{ 1113013SN/A assert(!blocked); 1123013SN/A DPRINTF(Cache, "Cache Blocking\n"); 1132810SN/A blocked = true; 1143013SN/A //Clear the retry flag 1153013SN/A mustSendRetry = false; 1162810SN/A} 1172810SN/A 1182810SN/Avoid 1192810SN/ABaseCache::CachePort::clearBlocked() 1202810SN/A{ 1213013SN/A assert(blocked); 1223013SN/A DPRINTF(Cache, "Cache Unblocking\n"); 1233013SN/A blocked = false; 1242897SN/A if (mustSendRetry) 1252897SN/A { 1263013SN/A DPRINTF(Cache, "Cache Sending Retry\n"); 1272897SN/A mustSendRetry = false; 1284666SN/A SendRetryEvent *ev = new SendRetryEvent(this, true); 1294666SN/A // @TODO: need to find a better time (next bus cycle?) 1307823Ssteve.reinhardt@amd.com schedule(ev, curTick() + 1); 1312897SN/A } 1322810SN/A} 1332810SN/A 1342844SN/A 1352810SN/Avoid 1362858SN/ABaseCache::init() 1372858SN/A{ 1382858SN/A if (!cpuSidePort || !memSidePort) 1392858SN/A panic("Cache not hooked up on both sides\n"); 1402858SN/A cpuSidePort->sendStatusChange(Port::RangeChange); 1412858SN/A} 1422858SN/A 1434628SN/A 1442858SN/Avoid 1452810SN/ABaseCache::regStats() 1462810SN/A{ 1472810SN/A using namespace Stats; 1482810SN/A 1492810SN/A // Hit statistics 1504022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1514022SN/A MemCmd cmd(access_idx); 1524022SN/A const string &cstr = cmd.toString(); 1532810SN/A 1542810SN/A hits[access_idx] 1558786Sgblack@eecs.umich.edu .init(FullSystem ? (_numCpus + 1) : _numCpus) 1562810SN/A .name(name() + "." + cstr + "_hits") 1572810SN/A .desc("number of " + cstr + " hits") 1582810SN/A .flags(total | nozero | nonan) 1592810SN/A ; 1602810SN/A } 1612810SN/A 1624871SN/A// These macros make it easier to sum the right subset of commands and 1634871SN/A// to change the subset of commands that are considered "demand" vs 1644871SN/A// "non-demand" 1654871SN/A#define SUM_DEMAND(s) \ 1664871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1674871SN/A 1684871SN/A// should writebacks be included here? prior code was inconsistent... 1694871SN/A#define SUM_NON_DEMAND(s) \ 1704871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1714871SN/A 1722810SN/A demandHits 1732810SN/A .name(name() + ".demand_hits") 1742810SN/A .desc("number of demand (read+write) hits") 1752810SN/A .flags(total) 1762810SN/A ; 1774871SN/A demandHits = SUM_DEMAND(hits); 1782810SN/A 1792810SN/A overallHits 1802810SN/A .name(name() + ".overall_hits") 1812810SN/A .desc("number of overall hits") 1822810SN/A .flags(total) 1832810SN/A ; 1844871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1852810SN/A 1862810SN/A // Miss statistics 1874022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1884022SN/A MemCmd cmd(access_idx); 1894022SN/A const string &cstr = cmd.toString(); 1902810SN/A 1912810SN/A misses[access_idx] 1928786Sgblack@eecs.umich.edu .init(FullSystem ? (_numCpus + 1) : _numCpus) 1932810SN/A .name(name() + "." + cstr + "_misses") 1942810SN/A .desc("number of " + cstr + " misses") 1952810SN/A .flags(total | nozero | nonan) 1962810SN/A ; 1972810SN/A } 1982810SN/A 1992810SN/A demandMisses 2002810SN/A .name(name() + ".demand_misses") 2012810SN/A .desc("number of demand (read+write) misses") 2022810SN/A .flags(total) 2032810SN/A ; 2044871SN/A demandMisses = SUM_DEMAND(misses); 2052810SN/A 2062810SN/A overallMisses 2072810SN/A .name(name() + ".overall_misses") 2082810SN/A .desc("number of overall misses") 2092810SN/A .flags(total) 2102810SN/A ; 2114871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2122810SN/A 2132810SN/A // Miss latency statistics 2144022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2154022SN/A MemCmd cmd(access_idx); 2164022SN/A const string &cstr = cmd.toString(); 2172810SN/A 2182810SN/A missLatency[access_idx] 2192810SN/A .init(maxThreadsPerCPU) 2202810SN/A .name(name() + "." + cstr + "_miss_latency") 2212810SN/A .desc("number of " + cstr + " miss cycles") 2222810SN/A .flags(total | nozero | nonan) 2232810SN/A ; 2242810SN/A } 2252810SN/A 2262810SN/A demandMissLatency 2272810SN/A .name(name() + ".demand_miss_latency") 2282810SN/A .desc("number of demand (read+write) miss cycles") 2292810SN/A .flags(total) 2302810SN/A ; 2314871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2322810SN/A 2332810SN/A overallMissLatency 2342810SN/A .name(name() + ".overall_miss_latency") 2352810SN/A .desc("number of overall miss cycles") 2362810SN/A .flags(total) 2372810SN/A ; 2384871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2392810SN/A 2402810SN/A // access formulas 2414022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2424022SN/A MemCmd cmd(access_idx); 2434022SN/A const string &cstr = cmd.toString(); 2442810SN/A 2452810SN/A accesses[access_idx] 2462810SN/A .name(name() + "." + cstr + "_accesses") 2472810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2482810SN/A .flags(total | nozero | nonan) 2492810SN/A ; 2502810SN/A 2512810SN/A accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2522810SN/A } 2532810SN/A 2542810SN/A demandAccesses 2552810SN/A .name(name() + ".demand_accesses") 2562810SN/A .desc("number of demand (read+write) accesses") 2572810SN/A .flags(total) 2582810SN/A ; 2592810SN/A demandAccesses = demandHits + demandMisses; 2602810SN/A 2612810SN/A overallAccesses 2622810SN/A .name(name() + ".overall_accesses") 2632810SN/A .desc("number of overall (read+write) accesses") 2642810SN/A .flags(total) 2652810SN/A ; 2662810SN/A overallAccesses = overallHits + overallMisses; 2672810SN/A 2682810SN/A // miss rate formulas 2694022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2704022SN/A MemCmd cmd(access_idx); 2714022SN/A const string &cstr = cmd.toString(); 2722810SN/A 2732810SN/A missRate[access_idx] 2742810SN/A .name(name() + "." + cstr + "_miss_rate") 2752810SN/A .desc("miss rate for " + cstr + " accesses") 2762810SN/A .flags(total | nozero | nonan) 2772810SN/A ; 2782810SN/A 2792810SN/A missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 2802810SN/A } 2812810SN/A 2822810SN/A demandMissRate 2832810SN/A .name(name() + ".demand_miss_rate") 2842810SN/A .desc("miss rate for demand accesses") 2852810SN/A .flags(total) 2862810SN/A ; 2872810SN/A demandMissRate = demandMisses / demandAccesses; 2882810SN/A 2892810SN/A overallMissRate 2902810SN/A .name(name() + ".overall_miss_rate") 2912810SN/A .desc("miss rate for overall accesses") 2922810SN/A .flags(total) 2932810SN/A ; 2942810SN/A overallMissRate = overallMisses / overallAccesses; 2952810SN/A 2962810SN/A // miss latency formulas 2974022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2984022SN/A MemCmd cmd(access_idx); 2994022SN/A const string &cstr = cmd.toString(); 3002810SN/A 3012810SN/A avgMissLatency[access_idx] 3022810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3032810SN/A .desc("average " + cstr + " miss latency") 3042810SN/A .flags(total | nozero | nonan) 3052810SN/A ; 3062810SN/A 3072810SN/A avgMissLatency[access_idx] = 3082810SN/A missLatency[access_idx] / misses[access_idx]; 3092810SN/A } 3102810SN/A 3112810SN/A demandAvgMissLatency 3122810SN/A .name(name() + ".demand_avg_miss_latency") 3132810SN/A .desc("average overall miss latency") 3142810SN/A .flags(total) 3152810SN/A ; 3162810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3172810SN/A 3182810SN/A overallAvgMissLatency 3192810SN/A .name(name() + ".overall_avg_miss_latency") 3202810SN/A .desc("average overall miss latency") 3212810SN/A .flags(total) 3222810SN/A ; 3232810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3242810SN/A 3252810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3262810SN/A blocked_cycles 3272810SN/A .name(name() + ".blocked_cycles") 3282810SN/A .desc("number of cycles access was blocked") 3292810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3302810SN/A .subname(Blocked_NoTargets, "no_targets") 3312810SN/A ; 3322810SN/A 3332810SN/A 3342810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3352810SN/A blocked_causes 3362810SN/A .name(name() + ".blocked") 3372810SN/A .desc("number of cycles access was blocked") 3382810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3392810SN/A .subname(Blocked_NoTargets, "no_targets") 3402810SN/A ; 3412810SN/A 3422810SN/A avg_blocked 3432810SN/A .name(name() + ".avg_blocked_cycles") 3442810SN/A .desc("average number of cycles each access was blocked") 3452810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3462810SN/A .subname(Blocked_NoTargets, "no_targets") 3472810SN/A ; 3482810SN/A 3492810SN/A avg_blocked = blocked_cycles / blocked_causes; 3502810SN/A 3512810SN/A fastWrites 3522810SN/A .name(name() + ".fast_writes") 3532810SN/A .desc("number of fast writes performed") 3542810SN/A ; 3552810SN/A 3562810SN/A cacheCopies 3572810SN/A .name(name() + ".cache_copies") 3582810SN/A .desc("number of cache copies performed") 3592810SN/A ; 3602826SN/A 3614626SN/A writebacks 3624626SN/A .init(maxThreadsPerCPU) 3634626SN/A .name(name() + ".writebacks") 3644626SN/A .desc("number of writebacks") 3654626SN/A .flags(total) 3664626SN/A ; 3674626SN/A 3684626SN/A // MSHR statistics 3694626SN/A // MSHR hit statistics 3704626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3714626SN/A MemCmd cmd(access_idx); 3724626SN/A const string &cstr = cmd.toString(); 3734626SN/A 3744626SN/A mshr_hits[access_idx] 3754626SN/A .init(maxThreadsPerCPU) 3764626SN/A .name(name() + "." + cstr + "_mshr_hits") 3774626SN/A .desc("number of " + cstr + " MSHR hits") 3784626SN/A .flags(total | nozero | nonan) 3794626SN/A ; 3804626SN/A } 3814626SN/A 3824626SN/A demandMshrHits 3834626SN/A .name(name() + ".demand_mshr_hits") 3844626SN/A .desc("number of demand (read+write) MSHR hits") 3854626SN/A .flags(total) 3864626SN/A ; 3874871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 3884626SN/A 3894626SN/A overallMshrHits 3904626SN/A .name(name() + ".overall_mshr_hits") 3914626SN/A .desc("number of overall MSHR hits") 3924626SN/A .flags(total) 3934626SN/A ; 3944871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 3954626SN/A 3964626SN/A // MSHR miss statistics 3974626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3984626SN/A MemCmd cmd(access_idx); 3994626SN/A const string &cstr = cmd.toString(); 4004626SN/A 4014626SN/A mshr_misses[access_idx] 4024626SN/A .init(maxThreadsPerCPU) 4034626SN/A .name(name() + "." + cstr + "_mshr_misses") 4044626SN/A .desc("number of " + cstr + " MSHR misses") 4054626SN/A .flags(total | nozero | nonan) 4064626SN/A ; 4074626SN/A } 4084626SN/A 4094626SN/A demandMshrMisses 4104626SN/A .name(name() + ".demand_mshr_misses") 4114626SN/A .desc("number of demand (read+write) MSHR misses") 4124626SN/A .flags(total) 4134626SN/A ; 4144871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4154626SN/A 4164626SN/A overallMshrMisses 4174626SN/A .name(name() + ".overall_mshr_misses") 4184626SN/A .desc("number of overall MSHR misses") 4194626SN/A .flags(total) 4204626SN/A ; 4214871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4224626SN/A 4234626SN/A // MSHR miss latency statistics 4244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4254626SN/A MemCmd cmd(access_idx); 4264626SN/A const string &cstr = cmd.toString(); 4274626SN/A 4284626SN/A mshr_miss_latency[access_idx] 4294626SN/A .init(maxThreadsPerCPU) 4304626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 4314626SN/A .desc("number of " + cstr + " MSHR miss cycles") 4324626SN/A .flags(total | nozero | nonan) 4334626SN/A ; 4344626SN/A } 4354626SN/A 4364626SN/A demandMshrMissLatency 4374626SN/A .name(name() + ".demand_mshr_miss_latency") 4384626SN/A .desc("number of demand (read+write) MSHR miss cycles") 4394626SN/A .flags(total) 4404626SN/A ; 4414871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 4424626SN/A 4434626SN/A overallMshrMissLatency 4444626SN/A .name(name() + ".overall_mshr_miss_latency") 4454626SN/A .desc("number of overall MSHR miss cycles") 4464626SN/A .flags(total) 4474626SN/A ; 4484871SN/A overallMshrMissLatency = 4494871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 4504626SN/A 4514626SN/A // MSHR uncacheable statistics 4524626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4534626SN/A MemCmd cmd(access_idx); 4544626SN/A const string &cstr = cmd.toString(); 4554626SN/A 4564626SN/A mshr_uncacheable[access_idx] 4574626SN/A .init(maxThreadsPerCPU) 4584626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 4594626SN/A .desc("number of " + cstr + " MSHR uncacheable") 4604626SN/A .flags(total | nozero | nonan) 4614626SN/A ; 4624626SN/A } 4634626SN/A 4644626SN/A overallMshrUncacheable 4654626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 4664626SN/A .desc("number of overall MSHR uncacheable misses") 4674626SN/A .flags(total) 4684626SN/A ; 4694871SN/A overallMshrUncacheable = 4704871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 4714626SN/A 4724626SN/A // MSHR miss latency statistics 4734626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4744626SN/A MemCmd cmd(access_idx); 4754626SN/A const string &cstr = cmd.toString(); 4764626SN/A 4774626SN/A mshr_uncacheable_lat[access_idx] 4784626SN/A .init(maxThreadsPerCPU) 4794626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 4804626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 4814626SN/A .flags(total | nozero | nonan) 4824626SN/A ; 4834626SN/A } 4844626SN/A 4854626SN/A overallMshrUncacheableLatency 4864626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 4874626SN/A .desc("number of overall MSHR uncacheable cycles") 4884626SN/A .flags(total) 4894626SN/A ; 4904871SN/A overallMshrUncacheableLatency = 4914871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 4924871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 4934626SN/A 4944626SN/A#if 0 4954626SN/A // MSHR access formulas 4964626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4974626SN/A MemCmd cmd(access_idx); 4984626SN/A const string &cstr = cmd.toString(); 4994626SN/A 5004626SN/A mshrAccesses[access_idx] 5014626SN/A .name(name() + "." + cstr + "_mshr_accesses") 5024626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 5034626SN/A .flags(total | nozero | nonan) 5044626SN/A ; 5054626SN/A mshrAccesses[access_idx] = 5064626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 5074626SN/A + mshr_uncacheable[access_idx]; 5084626SN/A } 5094626SN/A 5104626SN/A demandMshrAccesses 5114626SN/A .name(name() + ".demand_mshr_accesses") 5124626SN/A .desc("number of demand (read+write) mshr accesses") 5134626SN/A .flags(total | nozero | nonan) 5144626SN/A ; 5154626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 5164626SN/A 5174626SN/A overallMshrAccesses 5184626SN/A .name(name() + ".overall_mshr_accesses") 5194626SN/A .desc("number of overall (read+write) mshr accesses") 5204626SN/A .flags(total | nozero | nonan) 5214626SN/A ; 5224626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 5234626SN/A + overallMshrUncacheable; 5244626SN/A#endif 5254626SN/A 5264626SN/A // MSHR miss rate formulas 5274626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5284626SN/A MemCmd cmd(access_idx); 5294626SN/A const string &cstr = cmd.toString(); 5304626SN/A 5314626SN/A mshrMissRate[access_idx] 5324626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 5334626SN/A .desc("mshr miss rate for " + cstr + " accesses") 5344626SN/A .flags(total | nozero | nonan) 5354626SN/A ; 5364626SN/A 5374626SN/A mshrMissRate[access_idx] = 5384626SN/A mshr_misses[access_idx] / accesses[access_idx]; 5394626SN/A } 5404626SN/A 5414626SN/A demandMshrMissRate 5424626SN/A .name(name() + ".demand_mshr_miss_rate") 5434626SN/A .desc("mshr miss rate for demand accesses") 5444626SN/A .flags(total) 5454626SN/A ; 5464626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 5474626SN/A 5484626SN/A overallMshrMissRate 5494626SN/A .name(name() + ".overall_mshr_miss_rate") 5504626SN/A .desc("mshr miss rate for overall accesses") 5514626SN/A .flags(total) 5524626SN/A ; 5534626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 5544626SN/A 5554626SN/A // mshrMiss latency formulas 5564626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5574626SN/A MemCmd cmd(access_idx); 5584626SN/A const string &cstr = cmd.toString(); 5594626SN/A 5604626SN/A avgMshrMissLatency[access_idx] 5614626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 5624626SN/A .desc("average " + cstr + " mshr miss latency") 5634626SN/A .flags(total | nozero | nonan) 5644626SN/A ; 5654626SN/A 5664626SN/A avgMshrMissLatency[access_idx] = 5674626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 5684626SN/A } 5694626SN/A 5704626SN/A demandAvgMshrMissLatency 5714626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 5724626SN/A .desc("average overall mshr miss latency") 5734626SN/A .flags(total) 5744626SN/A ; 5754626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 5764626SN/A 5774626SN/A overallAvgMshrMissLatency 5784626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 5794626SN/A .desc("average overall mshr miss latency") 5804626SN/A .flags(total) 5814626SN/A ; 5824626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 5834626SN/A 5844626SN/A // mshrUncacheable latency formulas 5854626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5864626SN/A MemCmd cmd(access_idx); 5874626SN/A const string &cstr = cmd.toString(); 5884626SN/A 5894626SN/A avgMshrUncacheableLatency[access_idx] 5904626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 5914626SN/A .desc("average " + cstr + " mshr uncacheable latency") 5924626SN/A .flags(total | nozero | nonan) 5934626SN/A ; 5944626SN/A 5954626SN/A avgMshrUncacheableLatency[access_idx] = 5964626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 5974626SN/A } 5984626SN/A 5994626SN/A overallAvgMshrUncacheableLatency 6004626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 6014626SN/A .desc("average overall mshr uncacheable latency") 6024626SN/A .flags(total) 6034626SN/A ; 6044626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 6054626SN/A 6064626SN/A mshr_cap_events 6074626SN/A .init(maxThreadsPerCPU) 6084626SN/A .name(name() + ".mshr_cap_events") 6094626SN/A .desc("number of times MSHR cap was activated") 6104626SN/A .flags(total) 6114626SN/A ; 6124626SN/A 6134626SN/A //software prefetching stats 6144626SN/A soft_prefetch_mshr_full 6154626SN/A .init(maxThreadsPerCPU) 6164626SN/A .name(name() + ".soft_prefetch_mshr_full") 6174626SN/A .desc("number of mshr full events for SW prefetching instrutions") 6184626SN/A .flags(total) 6194626SN/A ; 6204626SN/A 6214626SN/A mshr_no_allocate_misses 6224626SN/A .name(name() +".no_allocate_misses") 6234626SN/A .desc("Number of misses that were no-allocate") 6244626SN/A ; 6254626SN/A 6262810SN/A} 6273503SN/A 6283503SN/Aunsigned int 6293503SN/ABaseCache::drain(Event *de) 6303503SN/A{ 6314626SN/A int count = memSidePort->drain(de) + cpuSidePort->drain(de); 6324626SN/A 6333503SN/A // Set status 6344626SN/A if (count != 0) { 6353503SN/A drainEvent = de; 6363503SN/A 6373503SN/A changeState(SimObject::Draining); 6384626SN/A return count; 6393503SN/A } 6403503SN/A 6413503SN/A changeState(SimObject::Drained); 6423503SN/A return 0; 6433503SN/A} 644