base.cc revision 7823
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Definition of BaseCache functions. 342810SN/A */ 352810SN/A 363348SN/A#include "cpu/base.hh" 373348SN/A#include "cpu/smt.hh" 385338Sstever@gmail.com#include "mem/cache/base.hh" 395338Sstever@gmail.com#include "mem/cache/mshr.hh" 402810SN/A 412810SN/Ausing namespace std; 422810SN/A 434965SN/ABaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 446122SSteve.Reinhardt@amd.com const std::string &_label) 455314SN/A : SimpleTimingPort(_name, _cache), cache(_cache), 465314SN/A label(_label), otherPort(NULL), 476122SSteve.Reinhardt@amd.com blocked(false), mustSendRetry(false) 482810SN/A{ 494475SN/A} 504475SN/A 514475SN/A 525034SN/ABaseCache::BaseCache(const Params *p) 535034SN/A : MemObject(p), 545314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 555314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 564628SN/A MSHRQueue_WriteBuffer), 575034SN/A blkSize(p->block_size), 585034SN/A hitLatency(p->latency), 595034SN/A numTarget(p->tgts_per_mshr), 606122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 614626SN/A blocked(0), 624626SN/A noTargetMSHR(NULL), 635034SN/A missCount(p->max_miss_count), 646122SSteve.Reinhardt@amd.com drainEvent(NULL), 656978SLisa.Hsu@amd.com addrRange(p->addr_range), 666978SLisa.Hsu@amd.com _numCpus(p->num_cpus) 674458SN/A{ 682810SN/A} 692810SN/A 702811SN/Avoid 712810SN/ABaseCache::CachePort::recvStatusChange(Port::Status status) 722810SN/A{ 734458SN/A if (status == Port::RangeChange) { 744458SN/A otherPort->sendStatusChange(Port::RangeChange); 754458SN/A } 762810SN/A} 772810SN/A 785314SN/A 795314SN/Abool 805314SN/ABaseCache::CachePort::checkFunctional(PacketPtr pkt) 815314SN/A{ 825314SN/A pkt->pushLabel(label); 835314SN/A bool done = SimpleTimingPort::checkFunctional(pkt); 845314SN/A pkt->popLabel(); 855314SN/A return done; 865314SN/A} 875314SN/A 885314SN/A 896227Snate@binkert.orgunsigned 906227Snate@binkert.orgBaseCache::CachePort::deviceBlockSize() const 912810SN/A{ 922810SN/A return cache->getBlockSize(); 932810SN/A} 942810SN/A 953606SN/A 964458SN/Abool 974458SN/ABaseCache::CachePort::recvRetryCommon() 983013SN/A{ 993236SN/A assert(waitingOnRetry); 1004458SN/A waitingOnRetry = false; 1014458SN/A return false; 1024458SN/A} 1033246SN/A 1043309SN/A 1053013SN/Avoid 1062810SN/ABaseCache::CachePort::setBlocked() 1072810SN/A{ 1083013SN/A assert(!blocked); 1093013SN/A DPRINTF(Cache, "Cache Blocking\n"); 1102810SN/A blocked = true; 1113013SN/A //Clear the retry flag 1123013SN/A mustSendRetry = false; 1132810SN/A} 1142810SN/A 1152810SN/Avoid 1162810SN/ABaseCache::CachePort::clearBlocked() 1172810SN/A{ 1183013SN/A assert(blocked); 1193013SN/A DPRINTF(Cache, "Cache Unblocking\n"); 1203013SN/A blocked = false; 1212897SN/A if (mustSendRetry) 1222897SN/A { 1233013SN/A DPRINTF(Cache, "Cache Sending Retry\n"); 1242897SN/A mustSendRetry = false; 1254666SN/A SendRetryEvent *ev = new SendRetryEvent(this, true); 1264666SN/A // @TODO: need to find a better time (next bus cycle?) 1277823Ssteve.reinhardt@amd.com schedule(ev, curTick() + 1); 1282897SN/A } 1292810SN/A} 1302810SN/A 1312844SN/A 1322810SN/Avoid 1332858SN/ABaseCache::init() 1342858SN/A{ 1352858SN/A if (!cpuSidePort || !memSidePort) 1362858SN/A panic("Cache not hooked up on both sides\n"); 1372858SN/A cpuSidePort->sendStatusChange(Port::RangeChange); 1382858SN/A} 1392858SN/A 1404628SN/A 1412858SN/Avoid 1422810SN/ABaseCache::regStats() 1432810SN/A{ 1442810SN/A using namespace Stats; 1452810SN/A 1462810SN/A // Hit statistics 1474022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1484022SN/A MemCmd cmd(access_idx); 1494022SN/A const string &cstr = cmd.toString(); 1502810SN/A 1512810SN/A hits[access_idx] 1526978SLisa.Hsu@amd.com#if FULL_SYSTEM 1536978SLisa.Hsu@amd.com .init(_numCpus + 1) 1546978SLisa.Hsu@amd.com#else 1556978SLisa.Hsu@amd.com .init(_numCpus) 1566978SLisa.Hsu@amd.com#endif 1572810SN/A .name(name() + "." + cstr + "_hits") 1582810SN/A .desc("number of " + cstr + " hits") 1592810SN/A .flags(total | nozero | nonan) 1602810SN/A ; 1612810SN/A } 1622810SN/A 1634871SN/A// These macros make it easier to sum the right subset of commands and 1644871SN/A// to change the subset of commands that are considered "demand" vs 1654871SN/A// "non-demand" 1664871SN/A#define SUM_DEMAND(s) \ 1674871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1684871SN/A 1694871SN/A// should writebacks be included here? prior code was inconsistent... 1704871SN/A#define SUM_NON_DEMAND(s) \ 1714871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1724871SN/A 1732810SN/A demandHits 1742810SN/A .name(name() + ".demand_hits") 1752810SN/A .desc("number of demand (read+write) hits") 1762810SN/A .flags(total) 1772810SN/A ; 1784871SN/A demandHits = SUM_DEMAND(hits); 1792810SN/A 1802810SN/A overallHits 1812810SN/A .name(name() + ".overall_hits") 1822810SN/A .desc("number of overall hits") 1832810SN/A .flags(total) 1842810SN/A ; 1854871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1862810SN/A 1872810SN/A // Miss statistics 1884022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1894022SN/A MemCmd cmd(access_idx); 1904022SN/A const string &cstr = cmd.toString(); 1912810SN/A 1922810SN/A misses[access_idx] 1936978SLisa.Hsu@amd.com#if FULL_SYSTEM 1946978SLisa.Hsu@amd.com .init(_numCpus + 1) 1956978SLisa.Hsu@amd.com#else 1966978SLisa.Hsu@amd.com .init(_numCpus) 1976978SLisa.Hsu@amd.com#endif 1982810SN/A .name(name() + "." + cstr + "_misses") 1992810SN/A .desc("number of " + cstr + " misses") 2002810SN/A .flags(total | nozero | nonan) 2012810SN/A ; 2022810SN/A } 2032810SN/A 2042810SN/A demandMisses 2052810SN/A .name(name() + ".demand_misses") 2062810SN/A .desc("number of demand (read+write) misses") 2072810SN/A .flags(total) 2082810SN/A ; 2094871SN/A demandMisses = SUM_DEMAND(misses); 2102810SN/A 2112810SN/A overallMisses 2122810SN/A .name(name() + ".overall_misses") 2132810SN/A .desc("number of overall misses") 2142810SN/A .flags(total) 2152810SN/A ; 2164871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2172810SN/A 2182810SN/A // Miss latency statistics 2194022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2204022SN/A MemCmd cmd(access_idx); 2214022SN/A const string &cstr = cmd.toString(); 2222810SN/A 2232810SN/A missLatency[access_idx] 2242810SN/A .init(maxThreadsPerCPU) 2252810SN/A .name(name() + "." + cstr + "_miss_latency") 2262810SN/A .desc("number of " + cstr + " miss cycles") 2272810SN/A .flags(total | nozero | nonan) 2282810SN/A ; 2292810SN/A } 2302810SN/A 2312810SN/A demandMissLatency 2322810SN/A .name(name() + ".demand_miss_latency") 2332810SN/A .desc("number of demand (read+write) miss cycles") 2342810SN/A .flags(total) 2352810SN/A ; 2364871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2372810SN/A 2382810SN/A overallMissLatency 2392810SN/A .name(name() + ".overall_miss_latency") 2402810SN/A .desc("number of overall miss cycles") 2412810SN/A .flags(total) 2422810SN/A ; 2434871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2442810SN/A 2452810SN/A // access formulas 2464022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2474022SN/A MemCmd cmd(access_idx); 2484022SN/A const string &cstr = cmd.toString(); 2492810SN/A 2502810SN/A accesses[access_idx] 2512810SN/A .name(name() + "." + cstr + "_accesses") 2522810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2532810SN/A .flags(total | nozero | nonan) 2542810SN/A ; 2552810SN/A 2562810SN/A accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2572810SN/A } 2582810SN/A 2592810SN/A demandAccesses 2602810SN/A .name(name() + ".demand_accesses") 2612810SN/A .desc("number of demand (read+write) accesses") 2622810SN/A .flags(total) 2632810SN/A ; 2642810SN/A demandAccesses = demandHits + demandMisses; 2652810SN/A 2662810SN/A overallAccesses 2672810SN/A .name(name() + ".overall_accesses") 2682810SN/A .desc("number of overall (read+write) accesses") 2692810SN/A .flags(total) 2702810SN/A ; 2712810SN/A overallAccesses = overallHits + overallMisses; 2722810SN/A 2732810SN/A // miss rate formulas 2744022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2754022SN/A MemCmd cmd(access_idx); 2764022SN/A const string &cstr = cmd.toString(); 2772810SN/A 2782810SN/A missRate[access_idx] 2792810SN/A .name(name() + "." + cstr + "_miss_rate") 2802810SN/A .desc("miss rate for " + cstr + " accesses") 2812810SN/A .flags(total | nozero | nonan) 2822810SN/A ; 2832810SN/A 2842810SN/A missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 2852810SN/A } 2862810SN/A 2872810SN/A demandMissRate 2882810SN/A .name(name() + ".demand_miss_rate") 2892810SN/A .desc("miss rate for demand accesses") 2902810SN/A .flags(total) 2912810SN/A ; 2922810SN/A demandMissRate = demandMisses / demandAccesses; 2932810SN/A 2942810SN/A overallMissRate 2952810SN/A .name(name() + ".overall_miss_rate") 2962810SN/A .desc("miss rate for overall accesses") 2972810SN/A .flags(total) 2982810SN/A ; 2992810SN/A overallMissRate = overallMisses / overallAccesses; 3002810SN/A 3012810SN/A // miss latency formulas 3024022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3034022SN/A MemCmd cmd(access_idx); 3044022SN/A const string &cstr = cmd.toString(); 3052810SN/A 3062810SN/A avgMissLatency[access_idx] 3072810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3082810SN/A .desc("average " + cstr + " miss latency") 3092810SN/A .flags(total | nozero | nonan) 3102810SN/A ; 3112810SN/A 3122810SN/A avgMissLatency[access_idx] = 3132810SN/A missLatency[access_idx] / misses[access_idx]; 3142810SN/A } 3152810SN/A 3162810SN/A demandAvgMissLatency 3172810SN/A .name(name() + ".demand_avg_miss_latency") 3182810SN/A .desc("average overall miss latency") 3192810SN/A .flags(total) 3202810SN/A ; 3212810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3222810SN/A 3232810SN/A overallAvgMissLatency 3242810SN/A .name(name() + ".overall_avg_miss_latency") 3252810SN/A .desc("average overall miss latency") 3262810SN/A .flags(total) 3272810SN/A ; 3282810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3292810SN/A 3302810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3312810SN/A blocked_cycles 3322810SN/A .name(name() + ".blocked_cycles") 3332810SN/A .desc("number of cycles access was blocked") 3342810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3352810SN/A .subname(Blocked_NoTargets, "no_targets") 3362810SN/A ; 3372810SN/A 3382810SN/A 3392810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3402810SN/A blocked_causes 3412810SN/A .name(name() + ".blocked") 3422810SN/A .desc("number of cycles access was blocked") 3432810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3442810SN/A .subname(Blocked_NoTargets, "no_targets") 3452810SN/A ; 3462810SN/A 3472810SN/A avg_blocked 3482810SN/A .name(name() + ".avg_blocked_cycles") 3492810SN/A .desc("average number of cycles each access was blocked") 3502810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3512810SN/A .subname(Blocked_NoTargets, "no_targets") 3522810SN/A ; 3532810SN/A 3542810SN/A avg_blocked = blocked_cycles / blocked_causes; 3552810SN/A 3562810SN/A fastWrites 3572810SN/A .name(name() + ".fast_writes") 3582810SN/A .desc("number of fast writes performed") 3592810SN/A ; 3602810SN/A 3612810SN/A cacheCopies 3622810SN/A .name(name() + ".cache_copies") 3632810SN/A .desc("number of cache copies performed") 3642810SN/A ; 3652826SN/A 3664626SN/A writebacks 3674626SN/A .init(maxThreadsPerCPU) 3684626SN/A .name(name() + ".writebacks") 3694626SN/A .desc("number of writebacks") 3704626SN/A .flags(total) 3714626SN/A ; 3724626SN/A 3734626SN/A // MSHR statistics 3744626SN/A // MSHR hit statistics 3754626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3764626SN/A MemCmd cmd(access_idx); 3774626SN/A const string &cstr = cmd.toString(); 3784626SN/A 3794626SN/A mshr_hits[access_idx] 3804626SN/A .init(maxThreadsPerCPU) 3814626SN/A .name(name() + "." + cstr + "_mshr_hits") 3824626SN/A .desc("number of " + cstr + " MSHR hits") 3834626SN/A .flags(total | nozero | nonan) 3844626SN/A ; 3854626SN/A } 3864626SN/A 3874626SN/A demandMshrHits 3884626SN/A .name(name() + ".demand_mshr_hits") 3894626SN/A .desc("number of demand (read+write) MSHR hits") 3904626SN/A .flags(total) 3914626SN/A ; 3924871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 3934626SN/A 3944626SN/A overallMshrHits 3954626SN/A .name(name() + ".overall_mshr_hits") 3964626SN/A .desc("number of overall MSHR hits") 3974626SN/A .flags(total) 3984626SN/A ; 3994871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4004626SN/A 4014626SN/A // MSHR miss statistics 4024626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4034626SN/A MemCmd cmd(access_idx); 4044626SN/A const string &cstr = cmd.toString(); 4054626SN/A 4064626SN/A mshr_misses[access_idx] 4074626SN/A .init(maxThreadsPerCPU) 4084626SN/A .name(name() + "." + cstr + "_mshr_misses") 4094626SN/A .desc("number of " + cstr + " MSHR misses") 4104626SN/A .flags(total | nozero | nonan) 4114626SN/A ; 4124626SN/A } 4134626SN/A 4144626SN/A demandMshrMisses 4154626SN/A .name(name() + ".demand_mshr_misses") 4164626SN/A .desc("number of demand (read+write) MSHR misses") 4174626SN/A .flags(total) 4184626SN/A ; 4194871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4204626SN/A 4214626SN/A overallMshrMisses 4224626SN/A .name(name() + ".overall_mshr_misses") 4234626SN/A .desc("number of overall MSHR misses") 4244626SN/A .flags(total) 4254626SN/A ; 4264871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4274626SN/A 4284626SN/A // MSHR miss latency statistics 4294626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4304626SN/A MemCmd cmd(access_idx); 4314626SN/A const string &cstr = cmd.toString(); 4324626SN/A 4334626SN/A mshr_miss_latency[access_idx] 4344626SN/A .init(maxThreadsPerCPU) 4354626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 4364626SN/A .desc("number of " + cstr + " MSHR miss cycles") 4374626SN/A .flags(total | nozero | nonan) 4384626SN/A ; 4394626SN/A } 4404626SN/A 4414626SN/A demandMshrMissLatency 4424626SN/A .name(name() + ".demand_mshr_miss_latency") 4434626SN/A .desc("number of demand (read+write) MSHR miss cycles") 4444626SN/A .flags(total) 4454626SN/A ; 4464871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 4474626SN/A 4484626SN/A overallMshrMissLatency 4494626SN/A .name(name() + ".overall_mshr_miss_latency") 4504626SN/A .desc("number of overall MSHR miss cycles") 4514626SN/A .flags(total) 4524626SN/A ; 4534871SN/A overallMshrMissLatency = 4544871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 4554626SN/A 4564626SN/A // MSHR uncacheable statistics 4574626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4584626SN/A MemCmd cmd(access_idx); 4594626SN/A const string &cstr = cmd.toString(); 4604626SN/A 4614626SN/A mshr_uncacheable[access_idx] 4624626SN/A .init(maxThreadsPerCPU) 4634626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 4644626SN/A .desc("number of " + cstr + " MSHR uncacheable") 4654626SN/A .flags(total | nozero | nonan) 4664626SN/A ; 4674626SN/A } 4684626SN/A 4694626SN/A overallMshrUncacheable 4704626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 4714626SN/A .desc("number of overall MSHR uncacheable misses") 4724626SN/A .flags(total) 4734626SN/A ; 4744871SN/A overallMshrUncacheable = 4754871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 4764626SN/A 4774626SN/A // MSHR miss latency statistics 4784626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4794626SN/A MemCmd cmd(access_idx); 4804626SN/A const string &cstr = cmd.toString(); 4814626SN/A 4824626SN/A mshr_uncacheable_lat[access_idx] 4834626SN/A .init(maxThreadsPerCPU) 4844626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 4854626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 4864626SN/A .flags(total | nozero | nonan) 4874626SN/A ; 4884626SN/A } 4894626SN/A 4904626SN/A overallMshrUncacheableLatency 4914626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 4924626SN/A .desc("number of overall MSHR uncacheable cycles") 4934626SN/A .flags(total) 4944626SN/A ; 4954871SN/A overallMshrUncacheableLatency = 4964871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 4974871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 4984626SN/A 4994626SN/A#if 0 5004626SN/A // MSHR access formulas 5014626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5024626SN/A MemCmd cmd(access_idx); 5034626SN/A const string &cstr = cmd.toString(); 5044626SN/A 5054626SN/A mshrAccesses[access_idx] 5064626SN/A .name(name() + "." + cstr + "_mshr_accesses") 5074626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 5084626SN/A .flags(total | nozero | nonan) 5094626SN/A ; 5104626SN/A mshrAccesses[access_idx] = 5114626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 5124626SN/A + mshr_uncacheable[access_idx]; 5134626SN/A } 5144626SN/A 5154626SN/A demandMshrAccesses 5164626SN/A .name(name() + ".demand_mshr_accesses") 5174626SN/A .desc("number of demand (read+write) mshr accesses") 5184626SN/A .flags(total | nozero | nonan) 5194626SN/A ; 5204626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 5214626SN/A 5224626SN/A overallMshrAccesses 5234626SN/A .name(name() + ".overall_mshr_accesses") 5244626SN/A .desc("number of overall (read+write) mshr accesses") 5254626SN/A .flags(total | nozero | nonan) 5264626SN/A ; 5274626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 5284626SN/A + overallMshrUncacheable; 5294626SN/A#endif 5304626SN/A 5314626SN/A // MSHR miss rate formulas 5324626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5334626SN/A MemCmd cmd(access_idx); 5344626SN/A const string &cstr = cmd.toString(); 5354626SN/A 5364626SN/A mshrMissRate[access_idx] 5374626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 5384626SN/A .desc("mshr miss rate for " + cstr + " accesses") 5394626SN/A .flags(total | nozero | nonan) 5404626SN/A ; 5414626SN/A 5424626SN/A mshrMissRate[access_idx] = 5434626SN/A mshr_misses[access_idx] / accesses[access_idx]; 5444626SN/A } 5454626SN/A 5464626SN/A demandMshrMissRate 5474626SN/A .name(name() + ".demand_mshr_miss_rate") 5484626SN/A .desc("mshr miss rate for demand accesses") 5494626SN/A .flags(total) 5504626SN/A ; 5514626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 5524626SN/A 5534626SN/A overallMshrMissRate 5544626SN/A .name(name() + ".overall_mshr_miss_rate") 5554626SN/A .desc("mshr miss rate for overall accesses") 5564626SN/A .flags(total) 5574626SN/A ; 5584626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 5594626SN/A 5604626SN/A // mshrMiss latency formulas 5614626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5624626SN/A MemCmd cmd(access_idx); 5634626SN/A const string &cstr = cmd.toString(); 5644626SN/A 5654626SN/A avgMshrMissLatency[access_idx] 5664626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 5674626SN/A .desc("average " + cstr + " mshr miss latency") 5684626SN/A .flags(total | nozero | nonan) 5694626SN/A ; 5704626SN/A 5714626SN/A avgMshrMissLatency[access_idx] = 5724626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 5734626SN/A } 5744626SN/A 5754626SN/A demandAvgMshrMissLatency 5764626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 5774626SN/A .desc("average overall mshr miss latency") 5784626SN/A .flags(total) 5794626SN/A ; 5804626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 5814626SN/A 5824626SN/A overallAvgMshrMissLatency 5834626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 5844626SN/A .desc("average overall mshr miss latency") 5854626SN/A .flags(total) 5864626SN/A ; 5874626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 5884626SN/A 5894626SN/A // mshrUncacheable latency formulas 5904626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5914626SN/A MemCmd cmd(access_idx); 5924626SN/A const string &cstr = cmd.toString(); 5934626SN/A 5944626SN/A avgMshrUncacheableLatency[access_idx] 5954626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 5964626SN/A .desc("average " + cstr + " mshr uncacheable latency") 5974626SN/A .flags(total | nozero | nonan) 5984626SN/A ; 5994626SN/A 6004626SN/A avgMshrUncacheableLatency[access_idx] = 6014626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 6024626SN/A } 6034626SN/A 6044626SN/A overallAvgMshrUncacheableLatency 6054626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 6064626SN/A .desc("average overall mshr uncacheable latency") 6074626SN/A .flags(total) 6084626SN/A ; 6094626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 6104626SN/A 6114626SN/A mshr_cap_events 6124626SN/A .init(maxThreadsPerCPU) 6134626SN/A .name(name() + ".mshr_cap_events") 6144626SN/A .desc("number of times MSHR cap was activated") 6154626SN/A .flags(total) 6164626SN/A ; 6174626SN/A 6184626SN/A //software prefetching stats 6194626SN/A soft_prefetch_mshr_full 6204626SN/A .init(maxThreadsPerCPU) 6214626SN/A .name(name() + ".soft_prefetch_mshr_full") 6224626SN/A .desc("number of mshr full events for SW prefetching instrutions") 6234626SN/A .flags(total) 6244626SN/A ; 6254626SN/A 6264626SN/A mshr_no_allocate_misses 6274626SN/A .name(name() +".no_allocate_misses") 6284626SN/A .desc("Number of misses that were no-allocate") 6294626SN/A ; 6304626SN/A 6312810SN/A} 6323503SN/A 6333503SN/Aunsigned int 6343503SN/ABaseCache::drain(Event *de) 6353503SN/A{ 6364626SN/A int count = memSidePort->drain(de) + cpuSidePort->drain(de); 6374626SN/A 6383503SN/A // Set status 6394626SN/A if (count != 0) { 6403503SN/A drainEvent = de; 6413503SN/A 6423503SN/A changeState(SimObject::Draining); 6434626SN/A return count; 6443503SN/A } 6453503SN/A 6463503SN/A changeState(SimObject::Drained); 6473503SN/A return 0; 6483503SN/A} 649