base.cc revision 5606
12810SN/A/* 22810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Erik Hallnor 292810SN/A */ 302810SN/A 312810SN/A/** 322810SN/A * @file 332810SN/A * Definition of BaseCache functions. 342810SN/A */ 352810SN/A 363348SN/A#include "cpu/base.hh" 373348SN/A#include "cpu/smt.hh" 385338Sstever@gmail.com#include "mem/cache/base.hh" 395338Sstever@gmail.com#include "mem/cache/mshr.hh" 402810SN/A 412810SN/Ausing namespace std; 422810SN/A 434965SN/ABaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 445314SN/A const std::string &_label, 455314SN/A std::vector<Range<Addr> > filter_ranges) 465314SN/A : SimpleTimingPort(_name, _cache), cache(_cache), 475314SN/A label(_label), otherPort(NULL), 484965SN/A blocked(false), mustSendRetry(false), filterRanges(filter_ranges) 492810SN/A{ 504475SN/A} 514475SN/A 524475SN/A 535034SN/ABaseCache::BaseCache(const Params *p) 545034SN/A : MemObject(p), 555314SN/A mshrQueue("MSHRs", p->mshrs, 4, MSHRQueue_MSHRs), 565314SN/A writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 574628SN/A MSHRQueue_WriteBuffer), 585034SN/A blkSize(p->block_size), 595034SN/A hitLatency(p->latency), 605034SN/A numTarget(p->tgts_per_mshr), 614626SN/A blocked(0), 624626SN/A noTargetMSHR(NULL), 635034SN/A missCount(p->max_miss_count), 644626SN/A drainEvent(NULL) 654458SN/A{ 662810SN/A} 672810SN/A 682811SN/Avoid 692810SN/ABaseCache::CachePort::recvStatusChange(Port::Status status) 702810SN/A{ 714458SN/A if (status == Port::RangeChange) { 724458SN/A otherPort->sendStatusChange(Port::RangeChange); 734458SN/A } 742810SN/A} 752810SN/A 765314SN/A 775314SN/Abool 785314SN/ABaseCache::CachePort::checkFunctional(PacketPtr pkt) 795314SN/A{ 805314SN/A pkt->pushLabel(label); 815314SN/A bool done = SimpleTimingPort::checkFunctional(pkt); 825314SN/A pkt->popLabel(); 835314SN/A return done; 845314SN/A} 855314SN/A 865314SN/A 872810SN/Aint 882810SN/ABaseCache::CachePort::deviceBlockSize() 892810SN/A{ 902810SN/A return cache->getBlockSize(); 912810SN/A} 922810SN/A 933606SN/A 944458SN/Abool 954458SN/ABaseCache::CachePort::recvRetryCommon() 963013SN/A{ 973236SN/A assert(waitingOnRetry); 984458SN/A waitingOnRetry = false; 994458SN/A return false; 1004458SN/A} 1013246SN/A 1023309SN/A 1033013SN/Avoid 1042810SN/ABaseCache::CachePort::setBlocked() 1052810SN/A{ 1063013SN/A assert(!blocked); 1073013SN/A DPRINTF(Cache, "Cache Blocking\n"); 1082810SN/A blocked = true; 1093013SN/A //Clear the retry flag 1103013SN/A mustSendRetry = false; 1112810SN/A} 1122810SN/A 1132810SN/Avoid 1142810SN/ABaseCache::CachePort::clearBlocked() 1152810SN/A{ 1163013SN/A assert(blocked); 1173013SN/A DPRINTF(Cache, "Cache Unblocking\n"); 1183013SN/A blocked = false; 1192897SN/A if (mustSendRetry) 1202897SN/A { 1213013SN/A DPRINTF(Cache, "Cache Sending Retry\n"); 1222897SN/A mustSendRetry = false; 1234666SN/A SendRetryEvent *ev = new SendRetryEvent(this, true); 1244666SN/A // @TODO: need to find a better time (next bus cycle?) 1255606Snate@binkert.org schedule(ev, curTick + 1); 1262897SN/A } 1272810SN/A} 1282810SN/A 1292844SN/A 1302810SN/Avoid 1312858SN/ABaseCache::init() 1322858SN/A{ 1332858SN/A if (!cpuSidePort || !memSidePort) 1342858SN/A panic("Cache not hooked up on both sides\n"); 1352858SN/A cpuSidePort->sendStatusChange(Port::RangeChange); 1362858SN/A} 1372858SN/A 1384628SN/A 1392858SN/Avoid 1402810SN/ABaseCache::regStats() 1412810SN/A{ 1422810SN/A using namespace Stats; 1432810SN/A 1442810SN/A // Hit statistics 1454022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1464022SN/A MemCmd cmd(access_idx); 1474022SN/A const string &cstr = cmd.toString(); 1482810SN/A 1492810SN/A hits[access_idx] 1502810SN/A .init(maxThreadsPerCPU) 1512810SN/A .name(name() + "." + cstr + "_hits") 1522810SN/A .desc("number of " + cstr + " hits") 1532810SN/A .flags(total | nozero | nonan) 1542810SN/A ; 1552810SN/A } 1562810SN/A 1574871SN/A// These macros make it easier to sum the right subset of commands and 1584871SN/A// to change the subset of commands that are considered "demand" vs 1594871SN/A// "non-demand" 1604871SN/A#define SUM_DEMAND(s) \ 1614871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1624871SN/A 1634871SN/A// should writebacks be included here? prior code was inconsistent... 1644871SN/A#define SUM_NON_DEMAND(s) \ 1654871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1664871SN/A 1672810SN/A demandHits 1682810SN/A .name(name() + ".demand_hits") 1692810SN/A .desc("number of demand (read+write) hits") 1702810SN/A .flags(total) 1712810SN/A ; 1724871SN/A demandHits = SUM_DEMAND(hits); 1732810SN/A 1742810SN/A overallHits 1752810SN/A .name(name() + ".overall_hits") 1762810SN/A .desc("number of overall hits") 1772810SN/A .flags(total) 1782810SN/A ; 1794871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 1802810SN/A 1812810SN/A // Miss statistics 1824022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1834022SN/A MemCmd cmd(access_idx); 1844022SN/A const string &cstr = cmd.toString(); 1852810SN/A 1862810SN/A misses[access_idx] 1872810SN/A .init(maxThreadsPerCPU) 1882810SN/A .name(name() + "." + cstr + "_misses") 1892810SN/A .desc("number of " + cstr + " misses") 1902810SN/A .flags(total | nozero | nonan) 1912810SN/A ; 1922810SN/A } 1932810SN/A 1942810SN/A demandMisses 1952810SN/A .name(name() + ".demand_misses") 1962810SN/A .desc("number of demand (read+write) misses") 1972810SN/A .flags(total) 1982810SN/A ; 1994871SN/A demandMisses = SUM_DEMAND(misses); 2002810SN/A 2012810SN/A overallMisses 2022810SN/A .name(name() + ".overall_misses") 2032810SN/A .desc("number of overall misses") 2042810SN/A .flags(total) 2052810SN/A ; 2064871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2072810SN/A 2082810SN/A // Miss latency statistics 2094022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2104022SN/A MemCmd cmd(access_idx); 2114022SN/A const string &cstr = cmd.toString(); 2122810SN/A 2132810SN/A missLatency[access_idx] 2142810SN/A .init(maxThreadsPerCPU) 2152810SN/A .name(name() + "." + cstr + "_miss_latency") 2162810SN/A .desc("number of " + cstr + " miss cycles") 2172810SN/A .flags(total | nozero | nonan) 2182810SN/A ; 2192810SN/A } 2202810SN/A 2212810SN/A demandMissLatency 2222810SN/A .name(name() + ".demand_miss_latency") 2232810SN/A .desc("number of demand (read+write) miss cycles") 2242810SN/A .flags(total) 2252810SN/A ; 2264871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2272810SN/A 2282810SN/A overallMissLatency 2292810SN/A .name(name() + ".overall_miss_latency") 2302810SN/A .desc("number of overall miss cycles") 2312810SN/A .flags(total) 2322810SN/A ; 2334871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2342810SN/A 2352810SN/A // access formulas 2364022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2374022SN/A MemCmd cmd(access_idx); 2384022SN/A const string &cstr = cmd.toString(); 2392810SN/A 2402810SN/A accesses[access_idx] 2412810SN/A .name(name() + "." + cstr + "_accesses") 2422810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2432810SN/A .flags(total | nozero | nonan) 2442810SN/A ; 2452810SN/A 2462810SN/A accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2472810SN/A } 2482810SN/A 2492810SN/A demandAccesses 2502810SN/A .name(name() + ".demand_accesses") 2512810SN/A .desc("number of demand (read+write) accesses") 2522810SN/A .flags(total) 2532810SN/A ; 2542810SN/A demandAccesses = demandHits + demandMisses; 2552810SN/A 2562810SN/A overallAccesses 2572810SN/A .name(name() + ".overall_accesses") 2582810SN/A .desc("number of overall (read+write) accesses") 2592810SN/A .flags(total) 2602810SN/A ; 2612810SN/A overallAccesses = overallHits + overallMisses; 2622810SN/A 2632810SN/A // miss rate formulas 2644022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2654022SN/A MemCmd cmd(access_idx); 2664022SN/A const string &cstr = cmd.toString(); 2672810SN/A 2682810SN/A missRate[access_idx] 2692810SN/A .name(name() + "." + cstr + "_miss_rate") 2702810SN/A .desc("miss rate for " + cstr + " accesses") 2712810SN/A .flags(total | nozero | nonan) 2722810SN/A ; 2732810SN/A 2742810SN/A missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 2752810SN/A } 2762810SN/A 2772810SN/A demandMissRate 2782810SN/A .name(name() + ".demand_miss_rate") 2792810SN/A .desc("miss rate for demand accesses") 2802810SN/A .flags(total) 2812810SN/A ; 2822810SN/A demandMissRate = demandMisses / demandAccesses; 2832810SN/A 2842810SN/A overallMissRate 2852810SN/A .name(name() + ".overall_miss_rate") 2862810SN/A .desc("miss rate for overall accesses") 2872810SN/A .flags(total) 2882810SN/A ; 2892810SN/A overallMissRate = overallMisses / overallAccesses; 2902810SN/A 2912810SN/A // miss latency formulas 2924022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2934022SN/A MemCmd cmd(access_idx); 2944022SN/A const string &cstr = cmd.toString(); 2952810SN/A 2962810SN/A avgMissLatency[access_idx] 2972810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 2982810SN/A .desc("average " + cstr + " miss latency") 2992810SN/A .flags(total | nozero | nonan) 3002810SN/A ; 3012810SN/A 3022810SN/A avgMissLatency[access_idx] = 3032810SN/A missLatency[access_idx] / misses[access_idx]; 3042810SN/A } 3052810SN/A 3062810SN/A demandAvgMissLatency 3072810SN/A .name(name() + ".demand_avg_miss_latency") 3082810SN/A .desc("average overall miss latency") 3092810SN/A .flags(total) 3102810SN/A ; 3112810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3122810SN/A 3132810SN/A overallAvgMissLatency 3142810SN/A .name(name() + ".overall_avg_miss_latency") 3152810SN/A .desc("average overall miss latency") 3162810SN/A .flags(total) 3172810SN/A ; 3182810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3192810SN/A 3202810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3212810SN/A blocked_cycles 3222810SN/A .name(name() + ".blocked_cycles") 3232810SN/A .desc("number of cycles access was blocked") 3242810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3252810SN/A .subname(Blocked_NoTargets, "no_targets") 3262810SN/A ; 3272810SN/A 3282810SN/A 3292810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 3302810SN/A blocked_causes 3312810SN/A .name(name() + ".blocked") 3322810SN/A .desc("number of cycles access was blocked") 3332810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3342810SN/A .subname(Blocked_NoTargets, "no_targets") 3352810SN/A ; 3362810SN/A 3372810SN/A avg_blocked 3382810SN/A .name(name() + ".avg_blocked_cycles") 3392810SN/A .desc("average number of cycles each access was blocked") 3402810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3412810SN/A .subname(Blocked_NoTargets, "no_targets") 3422810SN/A ; 3432810SN/A 3442810SN/A avg_blocked = blocked_cycles / blocked_causes; 3452810SN/A 3462810SN/A fastWrites 3472810SN/A .name(name() + ".fast_writes") 3482810SN/A .desc("number of fast writes performed") 3492810SN/A ; 3502810SN/A 3512810SN/A cacheCopies 3522810SN/A .name(name() + ".cache_copies") 3532810SN/A .desc("number of cache copies performed") 3542810SN/A ; 3552826SN/A 3564626SN/A writebacks 3574626SN/A .init(maxThreadsPerCPU) 3584626SN/A .name(name() + ".writebacks") 3594626SN/A .desc("number of writebacks") 3604626SN/A .flags(total) 3614626SN/A ; 3624626SN/A 3634626SN/A // MSHR statistics 3644626SN/A // MSHR hit statistics 3654626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3664626SN/A MemCmd cmd(access_idx); 3674626SN/A const string &cstr = cmd.toString(); 3684626SN/A 3694626SN/A mshr_hits[access_idx] 3704626SN/A .init(maxThreadsPerCPU) 3714626SN/A .name(name() + "." + cstr + "_mshr_hits") 3724626SN/A .desc("number of " + cstr + " MSHR hits") 3734626SN/A .flags(total | nozero | nonan) 3744626SN/A ; 3754626SN/A } 3764626SN/A 3774626SN/A demandMshrHits 3784626SN/A .name(name() + ".demand_mshr_hits") 3794626SN/A .desc("number of demand (read+write) MSHR hits") 3804626SN/A .flags(total) 3814626SN/A ; 3824871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 3834626SN/A 3844626SN/A overallMshrHits 3854626SN/A .name(name() + ".overall_mshr_hits") 3864626SN/A .desc("number of overall MSHR hits") 3874626SN/A .flags(total) 3884626SN/A ; 3894871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 3904626SN/A 3914626SN/A // MSHR miss statistics 3924626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3934626SN/A MemCmd cmd(access_idx); 3944626SN/A const string &cstr = cmd.toString(); 3954626SN/A 3964626SN/A mshr_misses[access_idx] 3974626SN/A .init(maxThreadsPerCPU) 3984626SN/A .name(name() + "." + cstr + "_mshr_misses") 3994626SN/A .desc("number of " + cstr + " MSHR misses") 4004626SN/A .flags(total | nozero | nonan) 4014626SN/A ; 4024626SN/A } 4034626SN/A 4044626SN/A demandMshrMisses 4054626SN/A .name(name() + ".demand_mshr_misses") 4064626SN/A .desc("number of demand (read+write) MSHR misses") 4074626SN/A .flags(total) 4084626SN/A ; 4094871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4104626SN/A 4114626SN/A overallMshrMisses 4124626SN/A .name(name() + ".overall_mshr_misses") 4134626SN/A .desc("number of overall MSHR misses") 4144626SN/A .flags(total) 4154626SN/A ; 4164871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 4174626SN/A 4184626SN/A // MSHR miss latency statistics 4194626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4204626SN/A MemCmd cmd(access_idx); 4214626SN/A const string &cstr = cmd.toString(); 4224626SN/A 4234626SN/A mshr_miss_latency[access_idx] 4244626SN/A .init(maxThreadsPerCPU) 4254626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 4264626SN/A .desc("number of " + cstr + " MSHR miss cycles") 4274626SN/A .flags(total | nozero | nonan) 4284626SN/A ; 4294626SN/A } 4304626SN/A 4314626SN/A demandMshrMissLatency 4324626SN/A .name(name() + ".demand_mshr_miss_latency") 4334626SN/A .desc("number of demand (read+write) MSHR miss cycles") 4344626SN/A .flags(total) 4354626SN/A ; 4364871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 4374626SN/A 4384626SN/A overallMshrMissLatency 4394626SN/A .name(name() + ".overall_mshr_miss_latency") 4404626SN/A .desc("number of overall MSHR miss cycles") 4414626SN/A .flags(total) 4424626SN/A ; 4434871SN/A overallMshrMissLatency = 4444871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 4454626SN/A 4464626SN/A // MSHR uncacheable statistics 4474626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4484626SN/A MemCmd cmd(access_idx); 4494626SN/A const string &cstr = cmd.toString(); 4504626SN/A 4514626SN/A mshr_uncacheable[access_idx] 4524626SN/A .init(maxThreadsPerCPU) 4534626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 4544626SN/A .desc("number of " + cstr + " MSHR uncacheable") 4554626SN/A .flags(total | nozero | nonan) 4564626SN/A ; 4574626SN/A } 4584626SN/A 4594626SN/A overallMshrUncacheable 4604626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 4614626SN/A .desc("number of overall MSHR uncacheable misses") 4624626SN/A .flags(total) 4634626SN/A ; 4644871SN/A overallMshrUncacheable = 4654871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 4664626SN/A 4674626SN/A // MSHR miss latency statistics 4684626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4694626SN/A MemCmd cmd(access_idx); 4704626SN/A const string &cstr = cmd.toString(); 4714626SN/A 4724626SN/A mshr_uncacheable_lat[access_idx] 4734626SN/A .init(maxThreadsPerCPU) 4744626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 4754626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 4764626SN/A .flags(total | nozero | nonan) 4774626SN/A ; 4784626SN/A } 4794626SN/A 4804626SN/A overallMshrUncacheableLatency 4814626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 4824626SN/A .desc("number of overall MSHR uncacheable cycles") 4834626SN/A .flags(total) 4844626SN/A ; 4854871SN/A overallMshrUncacheableLatency = 4864871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 4874871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 4884626SN/A 4894626SN/A#if 0 4904626SN/A // MSHR access formulas 4914626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4924626SN/A MemCmd cmd(access_idx); 4934626SN/A const string &cstr = cmd.toString(); 4944626SN/A 4954626SN/A mshrAccesses[access_idx] 4964626SN/A .name(name() + "." + cstr + "_mshr_accesses") 4974626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 4984626SN/A .flags(total | nozero | nonan) 4994626SN/A ; 5004626SN/A mshrAccesses[access_idx] = 5014626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 5024626SN/A + mshr_uncacheable[access_idx]; 5034626SN/A } 5044626SN/A 5054626SN/A demandMshrAccesses 5064626SN/A .name(name() + ".demand_mshr_accesses") 5074626SN/A .desc("number of demand (read+write) mshr accesses") 5084626SN/A .flags(total | nozero | nonan) 5094626SN/A ; 5104626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 5114626SN/A 5124626SN/A overallMshrAccesses 5134626SN/A .name(name() + ".overall_mshr_accesses") 5144626SN/A .desc("number of overall (read+write) mshr accesses") 5154626SN/A .flags(total | nozero | nonan) 5164626SN/A ; 5174626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 5184626SN/A + overallMshrUncacheable; 5194626SN/A#endif 5204626SN/A 5214626SN/A // MSHR miss rate formulas 5224626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5234626SN/A MemCmd cmd(access_idx); 5244626SN/A const string &cstr = cmd.toString(); 5254626SN/A 5264626SN/A mshrMissRate[access_idx] 5274626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 5284626SN/A .desc("mshr miss rate for " + cstr + " accesses") 5294626SN/A .flags(total | nozero | nonan) 5304626SN/A ; 5314626SN/A 5324626SN/A mshrMissRate[access_idx] = 5334626SN/A mshr_misses[access_idx] / accesses[access_idx]; 5344626SN/A } 5354626SN/A 5364626SN/A demandMshrMissRate 5374626SN/A .name(name() + ".demand_mshr_miss_rate") 5384626SN/A .desc("mshr miss rate for demand accesses") 5394626SN/A .flags(total) 5404626SN/A ; 5414626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 5424626SN/A 5434626SN/A overallMshrMissRate 5444626SN/A .name(name() + ".overall_mshr_miss_rate") 5454626SN/A .desc("mshr miss rate for overall accesses") 5464626SN/A .flags(total) 5474626SN/A ; 5484626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 5494626SN/A 5504626SN/A // mshrMiss latency formulas 5514626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5524626SN/A MemCmd cmd(access_idx); 5534626SN/A const string &cstr = cmd.toString(); 5544626SN/A 5554626SN/A avgMshrMissLatency[access_idx] 5564626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 5574626SN/A .desc("average " + cstr + " mshr miss latency") 5584626SN/A .flags(total | nozero | nonan) 5594626SN/A ; 5604626SN/A 5614626SN/A avgMshrMissLatency[access_idx] = 5624626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 5634626SN/A } 5644626SN/A 5654626SN/A demandAvgMshrMissLatency 5664626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 5674626SN/A .desc("average overall mshr miss latency") 5684626SN/A .flags(total) 5694626SN/A ; 5704626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 5714626SN/A 5724626SN/A overallAvgMshrMissLatency 5734626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 5744626SN/A .desc("average overall mshr miss latency") 5754626SN/A .flags(total) 5764626SN/A ; 5774626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 5784626SN/A 5794626SN/A // mshrUncacheable latency formulas 5804626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5814626SN/A MemCmd cmd(access_idx); 5824626SN/A const string &cstr = cmd.toString(); 5834626SN/A 5844626SN/A avgMshrUncacheableLatency[access_idx] 5854626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 5864626SN/A .desc("average " + cstr + " mshr uncacheable latency") 5874626SN/A .flags(total | nozero | nonan) 5884626SN/A ; 5894626SN/A 5904626SN/A avgMshrUncacheableLatency[access_idx] = 5914626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 5924626SN/A } 5934626SN/A 5944626SN/A overallAvgMshrUncacheableLatency 5954626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 5964626SN/A .desc("average overall mshr uncacheable latency") 5974626SN/A .flags(total) 5984626SN/A ; 5994626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 6004626SN/A 6014626SN/A mshr_cap_events 6024626SN/A .init(maxThreadsPerCPU) 6034626SN/A .name(name() + ".mshr_cap_events") 6044626SN/A .desc("number of times MSHR cap was activated") 6054626SN/A .flags(total) 6064626SN/A ; 6074626SN/A 6084626SN/A //software prefetching stats 6094626SN/A soft_prefetch_mshr_full 6104626SN/A .init(maxThreadsPerCPU) 6114626SN/A .name(name() + ".soft_prefetch_mshr_full") 6124626SN/A .desc("number of mshr full events for SW prefetching instrutions") 6134626SN/A .flags(total) 6144626SN/A ; 6154626SN/A 6164626SN/A mshr_no_allocate_misses 6174626SN/A .name(name() +".no_allocate_misses") 6184626SN/A .desc("Number of misses that were no-allocate") 6194626SN/A ; 6204626SN/A 6212810SN/A} 6223503SN/A 6233503SN/Aunsigned int 6243503SN/ABaseCache::drain(Event *de) 6253503SN/A{ 6264626SN/A int count = memSidePort->drain(de) + cpuSidePort->drain(de); 6274626SN/A 6283503SN/A // Set status 6294626SN/A if (count != 0) { 6303503SN/A drainEvent = de; 6313503SN/A 6323503SN/A changeState(SimObject::Draining); 6334626SN/A return count; 6343503SN/A } 6353503SN/A 6363503SN/A changeState(SimObject::Drained); 6373503SN/A return 0; 6383503SN/A} 639