base.cc revision 2858
12292SN/A/*
210333Smitch.hayenga@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan
310239Sbinhpham@cs.rutgers.edu * All rights reserved.
48707Sandreas.hansson@arm.com *
58707Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without
68707Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are
78707Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright
88707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer;
98707Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright
108707Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the
118707Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution;
128707Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its
138707Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from
148707Sandreas.hansson@arm.com * this software without specific prior written permission.
152727Sktlim@umich.edu *
162292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
172292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
182292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
192292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
202292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
212292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
222292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
232292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
242292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
252292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
262292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
272292SN/A *
282292SN/A * Authors: Erik Hallnor
292292SN/A */
302292SN/A
312292SN/A/**
322292SN/A * @file
332292SN/A * Definition of BaseCache functions.
342292SN/A */
352292SN/A
362292SN/A#include "mem/cache/base_cache.hh"
372292SN/A#include "cpu/smt.hh"
382292SN/A#include "cpu/base.hh"
392292SN/A
402689Sktlim@umich.eduusing namespace std;
412689Sktlim@umich.edu
422292SN/ABaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache,
432292SN/A                                bool _isCpuSide)
449944Smatt.horsnell@ARM.com    : Port(_name), cache(_cache), isCpuSide(_isCpuSide)
459944Smatt.horsnell@ARM.com{
469944Smatt.horsnell@ARM.com    blocked = false;
472329SN/A    //Start ports at null if more than one is created we should panic
482980Sgblack@eecs.umich.edu    //cpuSidePort = NULL;
492329SN/A    //memSidePort = NULL;
502329SN/A}
5113449Sgabeblack@google.com
522292SN/Avoid
539444SAndreas.Sandberg@ARM.comBaseCache::CachePort::recvStatusChange(Port::Status status)
548232Snate@binkert.org{
558232Snate@binkert.org    cache->recvStatusChange(status, isCpuSide);
568232Snate@binkert.org}
576221Snate@binkert.org
582292SN/Avoid
596221Snate@binkert.orgBaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp,
605529Snate@binkert.org                                       AddrRangeList &snoop)
612292SN/A{
625529Snate@binkert.org    cache->getAddressRanges(resp, snoop, isCpuSide);
638707Sandreas.hansson@arm.com}
6413560Snikos.nikoleris@arm.com
654329Sktlim@umich.eduint
664329Sktlim@umich.eduBaseCache::CachePort::deviceBlockSize()
6713472Srekai.gonzalezalberquilla@arm.com{
6813472Srekai.gonzalezalberquilla@arm.com    return cache->getBlockSize();
6913472Srekai.gonzalezalberquilla@arm.com}
7013472Srekai.gonzalezalberquilla@arm.com
7110333Smitch.hayenga@arm.combool
722292SN/ABaseCache::CachePort::recvTiming(Packet *pkt)
739868Sjthestness@gmail.com{
749868Sjthestness@gmail.com    return cache->doTimingAccess(pkt, this, isCpuSide);
752292SN/A}
762292SN/A
772292SN/ATick
782292SN/ABaseCache::CachePort::recvAtomic(Packet *pkt)
792292SN/A{
8013560Snikos.nikoleris@arm.com    return cache->doAtomicAccess(pkt, isCpuSide);
812292SN/A}
8213560Snikos.nikoleris@arm.com
832292SN/Avoid
848346Sksewell@umich.eduBaseCache::CachePort::recvFunctional(Packet *pkt)
852292SN/A{
8613560Snikos.nikoleris@arm.com    cache->doFunctionalAccess(pkt, isCpuSide);
872292SN/A}
882292SN/A
892292SN/Avoid
902292SN/ABaseCache::CachePort::setBlocked()
912292SN/A{
928346Sksewell@umich.edu    blocked = true;
932292SN/A}
942292SN/A
9513449Sgabeblack@google.comvoid
9613449Sgabeblack@google.comBaseCache::CachePort::clearBlocked()
972292SN/A{
982292SN/A    blocked = false;
9913472Srekai.gonzalezalberquilla@arm.com}
1006221Snate@binkert.org
10113472Srekai.gonzalezalberquilla@arm.comBaseCache::CacheEvent::CacheEvent(CachePort *_cachePort)
10213472Srekai.gonzalezalberquilla@arm.com    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort)
1038850Sandreas.hansson@arm.com{
1042292SN/A    this->setFlags(AutoDelete);
1052292SN/A    pkt = NULL;
1062292SN/A}
1072292SN/A
1082292SN/ABaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt)
1092292SN/A    : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt)
1102292SN/A{
1112292SN/A    this->setFlags(AutoDelete);
1122292SN/A}
1132292SN/A
1142292SN/Avoid
1152292SN/ABaseCache::CacheEvent::process()
1162292SN/A{
1172727Sktlim@umich.edu    if (!pkt)
1182727Sktlim@umich.edu    {
1192727Sktlim@umich.edu        if (!cachePort->isCpuSide)
1206221Snate@binkert.org            pkt = cachePort->cache->getPacket();
1212727Sktlim@umich.edu        else
1222727Sktlim@umich.edu            pkt = cachePort->cache->getCoherencePacket();
1232727Sktlim@umich.edu        bool success = cachePort->sendTiming(pkt);
1242727Sktlim@umich.edu        cachePort->cache->sendResult(pkt, success);
1252727Sktlim@umich.edu        return;
1262727Sktlim@umich.edu    }
1276221Snate@binkert.org    //Know the packet to send, no need to mark in service (must succed)
1282292SN/A    bool success = cachePort->sendTiming(pkt);
1292292SN/A    assert(success);
1302292SN/A}
1312292SN/A
1322292SN/Aconst char *
1332292SN/ABaseCache::CacheEvent::description()
1342307SN/A{
1359444SAndreas.Sandberg@ARM.com    return "timing event\n";
1362307SN/A}
1379444SAndreas.Sandberg@ARM.com
1389444SAndreas.Sandberg@ARM.comPort*
1399444SAndreas.Sandberg@ARM.comBaseCache::getPort(const std::string &if_name, int idx)
1409444SAndreas.Sandberg@ARM.com{
1419444SAndreas.Sandberg@ARM.com    if (if_name == "")
1429444SAndreas.Sandberg@ARM.com    {
1439444SAndreas.Sandberg@ARM.com        if(cpuSidePort == NULL)
1449444SAndreas.Sandberg@ARM.com            cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
1459444SAndreas.Sandberg@ARM.com        return cpuSidePort;
1469444SAndreas.Sandberg@ARM.com    }
1479444SAndreas.Sandberg@ARM.com    else if (if_name == "functional")
1489444SAndreas.Sandberg@ARM.com    {
1499444SAndreas.Sandberg@ARM.com        if(cpuSidePort == NULL)
1509444SAndreas.Sandberg@ARM.com            cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
1519444SAndreas.Sandberg@ARM.com        return cpuSidePort;
1522307SN/A    }
1539444SAndreas.Sandberg@ARM.com    else if (if_name == "cpu_side")
1549444SAndreas.Sandberg@ARM.com    {
1559444SAndreas.Sandberg@ARM.com        if(cpuSidePort == NULL)
1569444SAndreas.Sandberg@ARM.com            cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true);
1579444SAndreas.Sandberg@ARM.com        return cpuSidePort;
1589444SAndreas.Sandberg@ARM.com    }
1599444SAndreas.Sandberg@ARM.com    else if (if_name == "mem_side")
1602307SN/A    {
1612307SN/A        if (memSidePort != NULL)
1622307SN/A            panic("Already have a mem side for this cache\n");
1632307SN/A        memSidePort = new CachePort(name() + "-mem_side_port", this, false);
1642307SN/A        return memSidePort;
1652307SN/A    }
1666221Snate@binkert.org    else panic("Port name %s unrecognized\n", if_name);
1672307SN/A}
1682307SN/A
1692307SN/Avoid
1702307SN/ABaseCache::init()
1712307SN/A{
1722292SN/A    if (!cpuSidePort || !memSidePort)
1736221Snate@binkert.org        panic("Cache not hooked up on both sides\n");
1742292SN/A    cpuSidePort->sendStatusChange(Port::RangeChange);
17513560Snikos.nikoleris@arm.com}
1762292SN/A
1772292SN/Avoid
1782292SN/ABaseCache::regStats()
1792292SN/A{
1802292SN/A    Request temp_req((Addr) NULL, 4, 0);
1812292SN/A    Packet::Command temp_cmd = Packet::ReadReq;
1822292SN/A    Packet temp_pkt(&temp_req, temp_cmd, 0);  //@todo FIx command strings so this isn't neccessary
1832292SN/A    temp_pkt.allocate(); //Temp allocate, all need data
1842292SN/A
1852292SN/A    using namespace Stats;
18613560Snikos.nikoleris@arm.com
1873867Sbinkertn@umich.edu    // Hit statistics
1882292SN/A    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
1892292SN/A        Packet::Command cmd = (Packet::Command)access_idx;
1902292SN/A        const string &cstr = temp_pkt.cmdIdxToString(cmd);
19113560Snikos.nikoleris@arm.com
1922292SN/A        hits[access_idx]
19313560Snikos.nikoleris@arm.com            .init(maxThreadsPerCPU)
19413560Snikos.nikoleris@arm.com            .name(name() + "." + cstr + "_hits")
1952292SN/A            .desc("number of " + cstr + " hits")
1962292SN/A            .flags(total | nozero | nonan)
1972292SN/A            ;
1982292SN/A    }
1992292SN/A
2006221Snate@binkert.org    demandHits
2016221Snate@binkert.org        .name(name() + ".demand_hits")
2023867Sbinkertn@umich.edu        .desc("number of demand (read+write) hits")
2033867Sbinkertn@umich.edu        .flags(total)
2046221Snate@binkert.org        ;
2053867Sbinkertn@umich.edu    demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq];
2063867Sbinkertn@umich.edu
2072292SN/A    overallHits
2082292SN/A        .name(name() + ".overall_hits")
2092292SN/A        .desc("number of overall hits")
2102292SN/A        .flags(total)
2112292SN/A        ;
2122292SN/A    overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq]
2136221Snate@binkert.org        + hits[Packet::Writeback];
2142292SN/A
2152292SN/A    // Miss statistics
2162292SN/A    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
2172292SN/A        Packet::Command cmd = (Packet::Command)access_idx;
2182292SN/A        const string &cstr = temp_pkt.cmdIdxToString(cmd);
2192292SN/A
2202292SN/A        misses[access_idx]
2216221Snate@binkert.org            .init(maxThreadsPerCPU)
2222292SN/A            .name(name() + "." + cstr + "_misses")
2232292SN/A            .desc("number of " + cstr + " misses")
2242292SN/A            .flags(total | nozero | nonan)
2252292SN/A            ;
2262292SN/A    }
2272292SN/A
2282292SN/A    demandMisses
2292292SN/A        .name(name() + ".demand_misses")
2302292SN/A        .desc("number of demand (read+write) misses")
2316221Snate@binkert.org        .flags(total)
2326221Snate@binkert.org        ;
2332292SN/A    demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq];
2343867Sbinkertn@umich.edu
2356221Snate@binkert.org    overallMisses
2362292SN/A        .name(name() + ".overall_misses")
2372292SN/A        .desc("number of overall misses")
2382292SN/A        .flags(total)
2392292SN/A        ;
2402292SN/A    overallMisses = demandMisses + misses[Packet::SoftPFReq] +
2412292SN/A        misses[Packet::HardPFReq] + misses[Packet::Writeback];
2422292SN/A
24313429Srekai.gonzalezalberquilla@arm.com    // Miss latency statistics
2442292SN/A    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
2456221Snate@binkert.org        Packet::Command cmd = (Packet::Command)access_idx;
2462292SN/A        const string &cstr = temp_pkt.cmdIdxToString(cmd);
2472292SN/A
2482292SN/A        missLatency[access_idx]
2492292SN/A            .init(maxThreadsPerCPU)
2502292SN/A            .name(name() + "." + cstr + "_miss_latency")
2512292SN/A            .desc("number of " + cstr + " miss cycles")
25213429Srekai.gonzalezalberquilla@arm.com            .flags(total | nozero | nonan)
2532292SN/A            ;
2546221Snate@binkert.org    }
2552292SN/A
2562292SN/A    demandMissLatency
2572292SN/A        .name(name() + ".demand_miss_latency")
2582292SN/A        .desc("number of demand (read+write) miss cycles")
2592292SN/A        .flags(total)
2602292SN/A        ;
26113429Srekai.gonzalezalberquilla@arm.com    demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq];
2622292SN/A
2636221Snate@binkert.org    overallMissLatency
2642292SN/A        .name(name() + ".overall_miss_latency")
2652292SN/A        .desc("number of overall miss cycles")
2662292SN/A        .flags(total)
2672292SN/A        ;
2682292SN/A    overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] +
2692292SN/A        missLatency[Packet::HardPFReq];
27013429Srekai.gonzalezalberquilla@arm.com
2712292SN/A    // access formulas
2726221Snate@binkert.org    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
2732292SN/A        Packet::Command cmd = (Packet::Command)access_idx;
2742292SN/A        const string &cstr = temp_pkt.cmdIdxToString(cmd);
2752292SN/A
2762292SN/A        accesses[access_idx]
2772292SN/A            .name(name() + "." + cstr + "_accesses")
2782292SN/A            .desc("number of " + cstr + " accesses(hits+misses)")
2792292SN/A            .flags(total | nozero | nonan)
2802292SN/A            ;
2816221Snate@binkert.org
2826221Snate@binkert.org        accesses[access_idx] = hits[access_idx] + misses[access_idx];
2832292SN/A    }
2843867Sbinkertn@umich.edu
2856221Snate@binkert.org    demandAccesses
2862292SN/A        .name(name() + ".demand_accesses")
2872292SN/A        .desc("number of demand (read+write) accesses")
2882329SN/A        .flags(total)
2892329SN/A        ;
2902292SN/A    demandAccesses = demandHits + demandMisses;
2912292SN/A
2922292SN/A    overallAccesses
2932292SN/A        .name(name() + ".overall_accesses")
2942292SN/A        .desc("number of overall (read+write) accesses")
2952292SN/A        .flags(total)
2962292SN/A        ;
2972292SN/A    overallAccesses = overallHits + overallMisses;
2982292SN/A
2992292SN/A    // miss rate formulas
3002292SN/A    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
3016221Snate@binkert.org        Packet::Command cmd = (Packet::Command)access_idx;
3026221Snate@binkert.org        const string &cstr = temp_pkt.cmdIdxToString(cmd);
3032292SN/A
3043867Sbinkertn@umich.edu        missRate[access_idx]
3056221Snate@binkert.org            .name(name() + "." + cstr + "_miss_rate")
3063867Sbinkertn@umich.edu            .desc("miss rate for " + cstr + " accesses")
3072292SN/A            .flags(total | nozero | nonan)
3082292SN/A            ;
3092292SN/A
3102292SN/A        missRate[access_idx] = misses[access_idx] / accesses[access_idx];
3112292SN/A    }
3122292SN/A
3132292SN/A    demandMissRate
3148707Sandreas.hansson@arm.com        .name(name() + ".demand_miss_rate")
3158707Sandreas.hansson@arm.com        .desc("miss rate for demand accesses")
31610713Sandreas.hansson@arm.com        .flags(total)
3178707Sandreas.hansson@arm.com        ;
31810333Smitch.hayenga@arm.com    demandMissRate = demandMisses / demandAccesses;
31910333Smitch.hayenga@arm.com
32010333Smitch.hayenga@arm.com    overallMissRate
32110333Smitch.hayenga@arm.com        .name(name() + ".overall_miss_rate")
3228707Sandreas.hansson@arm.com        .desc("miss rate for overall accesses")
3238707Sandreas.hansson@arm.com        .flags(total)
3248707Sandreas.hansson@arm.com        ;
3258707Sandreas.hansson@arm.com    overallMissRate = overallMisses / overallAccesses;
3268707Sandreas.hansson@arm.com
3278975Sandreas.hansson@arm.com    // miss latency formulas
3288707Sandreas.hansson@arm.com    for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) {
3298707Sandreas.hansson@arm.com        Packet::Command cmd = (Packet::Command)access_idx;
3308707Sandreas.hansson@arm.com        const string &cstr = temp_pkt.cmdIdxToString(cmd);
3318707Sandreas.hansson@arm.com
33210575SMarco.Elver@ARM.com        avgMissLatency[access_idx]
33311435Smitch.hayenga@arm.com            .name(name() + "." + cstr + "_avg_miss_latency")
33411435Smitch.hayenga@arm.com            .desc("average " + cstr + " miss latency")
33510575SMarco.Elver@ARM.com            .flags(total | nozero | nonan)
33610575SMarco.Elver@ARM.com            ;
33710575SMarco.Elver@ARM.com
33810575SMarco.Elver@ARM.com        avgMissLatency[access_idx] =
33910575SMarco.Elver@ARM.com            missLatency[access_idx] / misses[access_idx];
34010575SMarco.Elver@ARM.com    }
34110575SMarco.Elver@ARM.com
34210575SMarco.Elver@ARM.com    demandAvgMissLatency
34310575SMarco.Elver@ARM.com        .name(name() + ".demand_avg_miss_latency")
34410575SMarco.Elver@ARM.com        .desc("average overall miss latency")
34510575SMarco.Elver@ARM.com        .flags(total)
34610575SMarco.Elver@ARM.com        ;
34710575SMarco.Elver@ARM.com    demandAvgMissLatency = demandMissLatency / demandMisses;
34810575SMarco.Elver@ARM.com
34910575SMarco.Elver@ARM.com    overallAvgMissLatency
35010575SMarco.Elver@ARM.com        .name(name() + ".overall_avg_miss_latency")
35110575SMarco.Elver@ARM.com        .desc("average overall miss latency")
35210575SMarco.Elver@ARM.com        .flags(total)
35310575SMarco.Elver@ARM.com        ;
35410575SMarco.Elver@ARM.com    overallAvgMissLatency = overallMissLatency / overallMisses;
35510575SMarco.Elver@ARM.com
35610573Sstephan.diestelhorst@arm.com    blocked_cycles.init(NUM_BLOCKED_CAUSES);
3578948Sandreas.hansson@arm.com    blocked_cycles
3588948Sandreas.hansson@arm.com        .name(name() + ".blocked_cycles")
3598707Sandreas.hansson@arm.com        .desc("number of cycles access was blocked")
3608948Sandreas.hansson@arm.com        .subname(Blocked_NoMSHRs, "no_mshrs")
3618975Sandreas.hansson@arm.com        .subname(Blocked_NoTargets, "no_targets")
3628975Sandreas.hansson@arm.com        ;
3638948Sandreas.hansson@arm.com
3648948Sandreas.hansson@arm.com
3658948Sandreas.hansson@arm.com    blocked_causes.init(NUM_BLOCKED_CAUSES);
3668948Sandreas.hansson@arm.com    blocked_causes
3678948Sandreas.hansson@arm.com        .name(name() + ".blocked")
3688948Sandreas.hansson@arm.com        .desc("number of cycles access was blocked")
3698948Sandreas.hansson@arm.com        .subname(Blocked_NoMSHRs, "no_mshrs")
3708948Sandreas.hansson@arm.com        .subname(Blocked_NoTargets, "no_targets")
3718948Sandreas.hansson@arm.com        ;
3728948Sandreas.hansson@arm.com
3738707Sandreas.hansson@arm.com    avg_blocked
3748707Sandreas.hansson@arm.com        .name(name() + ".avg_blocked_cycles")
3758707Sandreas.hansson@arm.com        .desc("average number of cycles each access was blocked")
3768707Sandreas.hansson@arm.com        .subname(Blocked_NoMSHRs, "no_mshrs")
3772292SN/A        .subname(Blocked_NoTargets, "no_targets")
3782292SN/A        ;
3792292SN/A
3802292SN/A    avg_blocked = blocked_cycles / blocked_causes;
3812292SN/A
3822292SN/A    fastWrites
3836221Snate@binkert.org        .name(name() + ".fast_writes")
3846221Snate@binkert.org        .desc("number of fast writes performed")
3852292SN/A        ;
3863867Sbinkertn@umich.edu
3876221Snate@binkert.org    cacheCopies
3883867Sbinkertn@umich.edu        .name(name() + ".cache_copies")
3892292SN/A        .desc("number of cache copies performed")
3902292SN/A        ;
3912292SN/A
3922292SN/A}
3932292SN/A