base.cc revision 2844
12810Srdreslin@umich.edu/* 211375Sandreas.hansson@arm.com * Copyright (c) 2003-2005 The Regents of The University of Michigan 311051Sandreas.hansson@arm.com * All rights reserved. 411051Sandreas.hansson@arm.com * 511051Sandreas.hansson@arm.com * Redistribution and use in source and binary forms, with or without 611051Sandreas.hansson@arm.com * modification, are permitted provided that the following conditions are 711051Sandreas.hansson@arm.com * met: redistributions of source code must retain the above copyright 811051Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer; 911051Sandreas.hansson@arm.com * redistributions in binary form must reproduce the above copyright 1011051Sandreas.hansson@arm.com * notice, this list of conditions and the following disclaimer in the 1111051Sandreas.hansson@arm.com * documentation and/or other materials provided with the distribution; 1211051Sandreas.hansson@arm.com * neither the name of the copyright holders nor the names of its 1311051Sandreas.hansson@arm.com * contributors may be used to endorse or promote products derived from 1411051Sandreas.hansson@arm.com * this software without specific prior written permission. 1511051Sandreas.hansson@arm.com * 162810Srdreslin@umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810Srdreslin@umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810Srdreslin@umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810Srdreslin@umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810Srdreslin@umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810Srdreslin@umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810Srdreslin@umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810Srdreslin@umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810Srdreslin@umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810Srdreslin@umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810Srdreslin@umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810Srdreslin@umich.edu * 282810Srdreslin@umich.edu * Authors: Erik Hallnor 292810Srdreslin@umich.edu */ 302810Srdreslin@umich.edu 312810Srdreslin@umich.edu/** 322810Srdreslin@umich.edu * @file 332810Srdreslin@umich.edu * Definition of BaseCache functions. 342810Srdreslin@umich.edu */ 352810Srdreslin@umich.edu 362810Srdreslin@umich.edu#include "mem/cache/base_cache.hh" 372810Srdreslin@umich.edu#include "cpu/smt.hh" 382810Srdreslin@umich.edu#include "cpu/base.hh" 392810Srdreslin@umich.edu 402810Srdreslin@umich.eduusing namespace std; 412810Srdreslin@umich.edu 4211051Sandreas.hansson@arm.comBaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, 4311051Sandreas.hansson@arm.com bool _isCpuSide) 442810Srdreslin@umich.edu : Port(_name), cache(_cache), isCpuSide(_isCpuSide) 4511051Sandreas.hansson@arm.com{ 4611051Sandreas.hansson@arm.com blocked = false; 472810Srdreslin@umich.edu //Start ports at null if more than one is created we should panic 482810Srdreslin@umich.edu //cpuSidePort = NULL; 492810Srdreslin@umich.edu //memSidePort = NULL; 502810Srdreslin@umich.edu} 5111051Sandreas.hansson@arm.com 522810Srdreslin@umich.eduvoid 532810Srdreslin@umich.eduBaseCache::CachePort::recvStatusChange(Port::Status status) 5411051Sandreas.hansson@arm.com{ 552810Srdreslin@umich.edu cache->recvStatusChange(status, isCpuSide); 5611051Sandreas.hansson@arm.com} 5711051Sandreas.hansson@arm.com 5811051Sandreas.hansson@arm.comvoid 5911051Sandreas.hansson@arm.comBaseCache::CachePort::getDeviceAddressRanges(AddrRangeList &resp, 6011051Sandreas.hansson@arm.com AddrRangeList &snoop) 6111288Ssteve.reinhardt@amd.com{ 6211051Sandreas.hansson@arm.com cache->getAddressRanges(resp, snoop); 6311051Sandreas.hansson@arm.com} 6411051Sandreas.hansson@arm.com 6511051Sandreas.hansson@arm.comint 6611051Sandreas.hansson@arm.comBaseCache::CachePort::deviceBlockSize() 6711053Sandreas.hansson@arm.com{ 6811053Sandreas.hansson@arm.com return cache->getBlockSize(); 6911051Sandreas.hansson@arm.com} 7011051Sandreas.hansson@arm.com 7111051Sandreas.hansson@arm.combool 7211197Sandreas.hansson@arm.comBaseCache::CachePort::recvTiming(Packet *pkt) 7311197Sandreas.hansson@arm.com{ 7411199Sandreas.hansson@arm.com return cache->doTimingAccess(pkt, this, isCpuSide); 7511197Sandreas.hansson@arm.com} 7611197Sandreas.hansson@arm.com 7711197Sandreas.hansson@arm.comTick 7811051Sandreas.hansson@arm.comBaseCache::CachePort::recvAtomic(Packet *pkt) 7911051Sandreas.hansson@arm.com{ 8011051Sandreas.hansson@arm.com return cache->doAtomicAccess(pkt, isCpuSide); 8111051Sandreas.hansson@arm.com} 8211051Sandreas.hansson@arm.com 8311051Sandreas.hansson@arm.comvoid 8411051Sandreas.hansson@arm.comBaseCache::CachePort::recvFunctional(Packet *pkt) 8511051Sandreas.hansson@arm.com{ 8611051Sandreas.hansson@arm.com cache->doFunctionalAccess(pkt, isCpuSide); 8711051Sandreas.hansson@arm.com} 8811051Sandreas.hansson@arm.com 8911051Sandreas.hansson@arm.comvoid 9011051Sandreas.hansson@arm.comBaseCache::CachePort::setBlocked() 9111051Sandreas.hansson@arm.com{ 9211051Sandreas.hansson@arm.com blocked = true; 9311051Sandreas.hansson@arm.com} 9411051Sandreas.hansson@arm.com 9511051Sandreas.hansson@arm.comvoid 9611051Sandreas.hansson@arm.comBaseCache::CachePort::clearBlocked() 9711051Sandreas.hansson@arm.com{ 9811051Sandreas.hansson@arm.com blocked = false; 9911051Sandreas.hansson@arm.com} 10011051Sandreas.hansson@arm.com 10111051Sandreas.hansson@arm.comBaseCache::CacheEvent::CacheEvent(CachePort *_cachePort) 10211051Sandreas.hansson@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort) 10311051Sandreas.hansson@arm.com{ 10411051Sandreas.hansson@arm.com this->setFlags(AutoDelete); 10511051Sandreas.hansson@arm.com pkt = NULL; 10611051Sandreas.hansson@arm.com} 10711051Sandreas.hansson@arm.com 10811051Sandreas.hansson@arm.comBaseCache::CacheEvent::CacheEvent(CachePort *_cachePort, Packet *_pkt) 10911051Sandreas.hansson@arm.com : Event(&mainEventQueue, CPU_Tick_Pri), cachePort(_cachePort), pkt(_pkt) 11011051Sandreas.hansson@arm.com{ 11111051Sandreas.hansson@arm.com this->setFlags(AutoDelete); 11211051Sandreas.hansson@arm.com} 11311051Sandreas.hansson@arm.com 11411051Sandreas.hansson@arm.comvoid 11511051Sandreas.hansson@arm.comBaseCache::CacheEvent::process() 11611051Sandreas.hansson@arm.com{ 11711051Sandreas.hansson@arm.com if (!pkt) 11811051Sandreas.hansson@arm.com { 11911051Sandreas.hansson@arm.com if (!cachePort->isCpuSide) 12011051Sandreas.hansson@arm.com pkt = cachePort->cache->getPacket(); 12111051Sandreas.hansson@arm.com //Else get coherence req 12211051Sandreas.hansson@arm.com } 12311051Sandreas.hansson@arm.com cachePort->sendTiming(pkt); 12411051Sandreas.hansson@arm.com} 12511051Sandreas.hansson@arm.com 12611051Sandreas.hansson@arm.comconst char * 12711051Sandreas.hansson@arm.comBaseCache::CacheEvent::description() 12811051Sandreas.hansson@arm.com{ 12911051Sandreas.hansson@arm.com return "timing event\n"; 13011051Sandreas.hansson@arm.com} 13111051Sandreas.hansson@arm.com 13211051Sandreas.hansson@arm.comPort* 13311051Sandreas.hansson@arm.comBaseCache::getPort(const std::string &if_name, int idx) 13411051Sandreas.hansson@arm.com{ 13511051Sandreas.hansson@arm.com if (if_name == "") 13611051Sandreas.hansson@arm.com { 13711051Sandreas.hansson@arm.com if(cpuSidePort == NULL) 13811051Sandreas.hansson@arm.com cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true); 13911051Sandreas.hansson@arm.com return cpuSidePort; 14011051Sandreas.hansson@arm.com } 14111051Sandreas.hansson@arm.com if (if_name == "functional") 14211051Sandreas.hansson@arm.com { 14311051Sandreas.hansson@arm.com if(cpuSidePort == NULL) 14411051Sandreas.hansson@arm.com cpuSidePort = new CachePort(name() + "-cpu_side_port", this, true); 14511051Sandreas.hansson@arm.com return cpuSidePort; 14611051Sandreas.hansson@arm.com } 14711051Sandreas.hansson@arm.com else if (if_name == "mem_side") 14811051Sandreas.hansson@arm.com { 14911601Sandreas.hansson@arm.com if (memSidePort != NULL) 15011601Sandreas.hansson@arm.com panic("Already have a mem side for this cache\n"); 15111051Sandreas.hansson@arm.com memSidePort = new CachePort(name() + "-mem_side_port", this, false); 15211051Sandreas.hansson@arm.com return memSidePort; 15311051Sandreas.hansson@arm.com } 15411051Sandreas.hansson@arm.com else panic("Port name %s unrecognized\n", if_name); 15511051Sandreas.hansson@arm.com} 15611051Sandreas.hansson@arm.com 15711051Sandreas.hansson@arm.comvoid 15811051Sandreas.hansson@arm.comBaseCache::regStats() 15911051Sandreas.hansson@arm.com{ 16011051Sandreas.hansson@arm.com Request temp_req((Addr) NULL, 4, 0); 16111284Sandreas.hansson@arm.com Packet::Command temp_cmd = Packet::ReadReq; 16211051Sandreas.hansson@arm.com Packet temp_pkt(&temp_req, temp_cmd, 0); //@todo FIx command strings so this isn't neccessary 16311051Sandreas.hansson@arm.com temp_pkt.allocate(); //Temp allocate, all need data 16411051Sandreas.hansson@arm.com 16511051Sandreas.hansson@arm.com using namespace Stats; 16611051Sandreas.hansson@arm.com 16711051Sandreas.hansson@arm.com // Hit statistics 16811051Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 16911284Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 17011284Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 17111284Sandreas.hansson@arm.com 17211284Sandreas.hansson@arm.com hits[access_idx] 17311051Sandreas.hansson@arm.com .init(maxThreadsPerCPU) 17411284Sandreas.hansson@arm.com .name(name() + "." + cstr + "_hits") 17511051Sandreas.hansson@arm.com .desc("number of " + cstr + " hits") 17611051Sandreas.hansson@arm.com .flags(total | nozero | nonan) 17711051Sandreas.hansson@arm.com ; 17811284Sandreas.hansson@arm.com } 17911284Sandreas.hansson@arm.com 18011284Sandreas.hansson@arm.com demandHits 18111284Sandreas.hansson@arm.com .name(name() + ".demand_hits") 18211051Sandreas.hansson@arm.com .desc("number of demand (read+write) hits") 18311744Snikos.nikoleris@arm.com .flags(total) 18411051Sandreas.hansson@arm.com ; 18511051Sandreas.hansson@arm.com demandHits = hits[Packet::ReadReq] + hits[Packet::WriteReq]; 18611051Sandreas.hansson@arm.com 18711051Sandreas.hansson@arm.com overallHits 18811286Sandreas.hansson@arm.com .name(name() + ".overall_hits") 18911286Sandreas.hansson@arm.com .desc("number of overall hits") 19011286Sandreas.hansson@arm.com .flags(total) 19111051Sandreas.hansson@arm.com ; 19211286Sandreas.hansson@arm.com overallHits = demandHits + hits[Packet::SoftPFReq] + hits[Packet::HardPFReq] 19311600Sandreas.hansson@arm.com + hits[Packet::Writeback]; 19411600Sandreas.hansson@arm.com 19511051Sandreas.hansson@arm.com // Miss statistics 19611051Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 19711051Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 19811284Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 19911051Sandreas.hansson@arm.com 20011051Sandreas.hansson@arm.com misses[access_idx] 20111051Sandreas.hansson@arm.com .init(maxThreadsPerCPU) 20211602Sandreas.hansson@arm.com .name(name() + "." + cstr + "_misses") 20311051Sandreas.hansson@arm.com .desc("number of " + cstr + " misses") 20411051Sandreas.hansson@arm.com .flags(total | nozero | nonan) 20511284Sandreas.hansson@arm.com ; 20611051Sandreas.hansson@arm.com } 20711284Sandreas.hansson@arm.com 20811602Sandreas.hansson@arm.com demandMisses 20911051Sandreas.hansson@arm.com .name(name() + ".demand_misses") 21011051Sandreas.hansson@arm.com .desc("number of demand (read+write) misses") 21111284Sandreas.hansson@arm.com .flags(total) 21211051Sandreas.hansson@arm.com ; 21311284Sandreas.hansson@arm.com demandMisses = misses[Packet::ReadReq] + misses[Packet::WriteReq]; 21411284Sandreas.hansson@arm.com 21511284Sandreas.hansson@arm.com overallMisses 21611051Sandreas.hansson@arm.com .name(name() + ".overall_misses") 21711051Sandreas.hansson@arm.com .desc("number of overall misses") 21811051Sandreas.hansson@arm.com .flags(total) 21911284Sandreas.hansson@arm.com ; 22011284Sandreas.hansson@arm.com overallMisses = demandMisses + misses[Packet::SoftPFReq] + 22111284Sandreas.hansson@arm.com misses[Packet::HardPFReq] + misses[Packet::Writeback]; 22211284Sandreas.hansson@arm.com 22311051Sandreas.hansson@arm.com // Miss latency statistics 22411051Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 22511051Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 22611284Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 22711284Sandreas.hansson@arm.com 22811284Sandreas.hansson@arm.com missLatency[access_idx] 22911197Sandreas.hansson@arm.com .init(maxThreadsPerCPU) 23011601Sandreas.hansson@arm.com .name(name() + "." + cstr + "_miss_latency") 23111601Sandreas.hansson@arm.com .desc("number of " + cstr + " miss cycles") 23211601Sandreas.hansson@arm.com .flags(total | nozero | nonan) 23311601Sandreas.hansson@arm.com ; 23411601Sandreas.hansson@arm.com } 23511601Sandreas.hansson@arm.com 23611601Sandreas.hansson@arm.com demandMissLatency 23711601Sandreas.hansson@arm.com .name(name() + ".demand_miss_latency") 23811197Sandreas.hansson@arm.com .desc("number of demand (read+write) miss cycles") 23911601Sandreas.hansson@arm.com .flags(total) 24011601Sandreas.hansson@arm.com ; 24111601Sandreas.hansson@arm.com demandMissLatency = missLatency[Packet::ReadReq] + missLatency[Packet::WriteReq]; 24211601Sandreas.hansson@arm.com 24311601Sandreas.hansson@arm.com overallMissLatency 24411601Sandreas.hansson@arm.com .name(name() + ".overall_miss_latency") 24511601Sandreas.hansson@arm.com .desc("number of overall miss cycles") 24611051Sandreas.hansson@arm.com .flags(total) 24711051Sandreas.hansson@arm.com ; 24811051Sandreas.hansson@arm.com overallMissLatency = demandMissLatency + missLatency[Packet::SoftPFReq] + 24911051Sandreas.hansson@arm.com missLatency[Packet::HardPFReq]; 25011051Sandreas.hansson@arm.com 25111284Sandreas.hansson@arm.com // access formulas 25211284Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 25311051Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 25411051Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 25511051Sandreas.hansson@arm.com 25611051Sandreas.hansson@arm.com accesses[access_idx] 25711284Sandreas.hansson@arm.com .name(name() + "." + cstr + "_accesses") 25811051Sandreas.hansson@arm.com .desc("number of " + cstr + " accesses(hits+misses)") 25911051Sandreas.hansson@arm.com .flags(total | nozero | nonan) 26011602Sandreas.hansson@arm.com ; 26111602Sandreas.hansson@arm.com 26211602Sandreas.hansson@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 26311602Sandreas.hansson@arm.com } 26411602Sandreas.hansson@arm.com 26511602Sandreas.hansson@arm.com demandAccesses 26611602Sandreas.hansson@arm.com .name(name() + ".demand_accesses") 26711602Sandreas.hansson@arm.com .desc("number of demand (read+write) accesses") 26811602Sandreas.hansson@arm.com .flags(total) 26911602Sandreas.hansson@arm.com ; 27011602Sandreas.hansson@arm.com demandAccesses = demandHits + demandMisses; 27111051Sandreas.hansson@arm.com 27211602Sandreas.hansson@arm.com overallAccesses 27311197Sandreas.hansson@arm.com .name(name() + ".overall_accesses") 27411744Snikos.nikoleris@arm.com .desc("number of overall (read+write) accesses") 27511744Snikos.nikoleris@arm.com .flags(total) 27611051Sandreas.hansson@arm.com ; 27711051Sandreas.hansson@arm.com overallAccesses = overallHits + overallMisses; 27811051Sandreas.hansson@arm.com 27911051Sandreas.hansson@arm.com // miss rate formulas 28011051Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 28111051Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 28211051Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 28311051Sandreas.hansson@arm.com 28411051Sandreas.hansson@arm.com missRate[access_idx] 28511051Sandreas.hansson@arm.com .name(name() + "." + cstr + "_miss_rate") 28611051Sandreas.hansson@arm.com .desc("miss rate for " + cstr + " accesses") 28711051Sandreas.hansson@arm.com .flags(total | nozero | nonan) 28811051Sandreas.hansson@arm.com ; 28911051Sandreas.hansson@arm.com 29011051Sandreas.hansson@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 29111051Sandreas.hansson@arm.com } 29211051Sandreas.hansson@arm.com 29311051Sandreas.hansson@arm.com demandMissRate 29411051Sandreas.hansson@arm.com .name(name() + ".demand_miss_rate") 29511051Sandreas.hansson@arm.com .desc("miss rate for demand accesses") 29611744Snikos.nikoleris@arm.com .flags(total) 29711051Sandreas.hansson@arm.com ; 29811051Sandreas.hansson@arm.com demandMissRate = demandMisses / demandAccesses; 29911744Snikos.nikoleris@arm.com 30011051Sandreas.hansson@arm.com overallMissRate 30111051Sandreas.hansson@arm.com .name(name() + ".overall_miss_rate") 30211051Sandreas.hansson@arm.com .desc("miss rate for overall accesses") 30311051Sandreas.hansson@arm.com .flags(total) 30411199Sandreas.hansson@arm.com ; 30511051Sandreas.hansson@arm.com overallMissRate = overallMisses / overallAccesses; 30611051Sandreas.hansson@arm.com 30711051Sandreas.hansson@arm.com // miss latency formulas 30811051Sandreas.hansson@arm.com for (int access_idx = 0; access_idx < NUM_MEM_CMDS; ++access_idx) { 30911051Sandreas.hansson@arm.com Packet::Command cmd = (Packet::Command)access_idx; 31011051Sandreas.hansson@arm.com const string &cstr = temp_pkt.cmdIdxToString(cmd); 31111051Sandreas.hansson@arm.com 31211484Snikos.nikoleris@arm.com avgMissLatency[access_idx] 31311051Sandreas.hansson@arm.com .name(name() + "." + cstr + "_avg_miss_latency") 31411051Sandreas.hansson@arm.com .desc("average " + cstr + " miss latency") 31511051Sandreas.hansson@arm.com .flags(total | nozero | nonan) 31611051Sandreas.hansson@arm.com ; 31711051Sandreas.hansson@arm.com 31811051Sandreas.hansson@arm.com avgMissLatency[access_idx] = 31911051Sandreas.hansson@arm.com missLatency[access_idx] / misses[access_idx]; 32011051Sandreas.hansson@arm.com } 32111051Sandreas.hansson@arm.com 32211051Sandreas.hansson@arm.com demandAvgMissLatency 32311051Sandreas.hansson@arm.com .name(name() + ".demand_avg_miss_latency") 32411744Snikos.nikoleris@arm.com .desc("average overall miss latency") 32511051Sandreas.hansson@arm.com .flags(total) 32611051Sandreas.hansson@arm.com ; 32711051Sandreas.hansson@arm.com demandAvgMissLatency = demandMissLatency / demandMisses; 32811199Sandreas.hansson@arm.com 32911051Sandreas.hansson@arm.com overallAvgMissLatency 33011051Sandreas.hansson@arm.com .name(name() + ".overall_avg_miss_latency") 33111051Sandreas.hansson@arm.com .desc("average overall miss latency") 33211051Sandreas.hansson@arm.com .flags(total) 33311051Sandreas.hansson@arm.com ; 33411051Sandreas.hansson@arm.com overallAvgMissLatency = overallMissLatency / overallMisses; 33511051Sandreas.hansson@arm.com 33611051Sandreas.hansson@arm.com blocked_cycles.init(NUM_BLOCKED_CAUSES); 33711375Sandreas.hansson@arm.com blocked_cycles 33811375Sandreas.hansson@arm.com .name(name() + ".blocked_cycles") 33911375Sandreas.hansson@arm.com .desc("number of cycles access was blocked") 34011199Sandreas.hansson@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 34111199Sandreas.hansson@arm.com .subname(Blocked_NoTargets, "no_targets") 34211199Sandreas.hansson@arm.com ; 34311199Sandreas.hansson@arm.com 34411199Sandreas.hansson@arm.com 34511199Sandreas.hansson@arm.com blocked_causes.init(NUM_BLOCKED_CAUSES); 34611199Sandreas.hansson@arm.com blocked_causes 34711199Sandreas.hansson@arm.com .name(name() + ".blocked") 34811199Sandreas.hansson@arm.com .desc("number of cycles access was blocked") 34911199Sandreas.hansson@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 35011199Sandreas.hansson@arm.com .subname(Blocked_NoTargets, "no_targets") 35111199Sandreas.hansson@arm.com ; 35211199Sandreas.hansson@arm.com 35311199Sandreas.hansson@arm.com avg_blocked 35411199Sandreas.hansson@arm.com .name(name() + ".avg_blocked_cycles") 35511199Sandreas.hansson@arm.com .desc("average number of cycles each access was blocked") 35611199Sandreas.hansson@arm.com .subname(Blocked_NoMSHRs, "no_mshrs") 35711199Sandreas.hansson@arm.com .subname(Blocked_NoTargets, "no_targets") 35811199Sandreas.hansson@arm.com ; 35911199Sandreas.hansson@arm.com 36011375Sandreas.hansson@arm.com avg_blocked = blocked_cycles / blocked_causes; 36111199Sandreas.hansson@arm.com 36211199Sandreas.hansson@arm.com fastWrites 36311051Sandreas.hansson@arm.com .name(name() + ".fast_writes") 36411051Sandreas.hansson@arm.com .desc("number of fast writes performed") 36511051Sandreas.hansson@arm.com ; 36611051Sandreas.hansson@arm.com 36711051Sandreas.hansson@arm.com cacheCopies 36811199Sandreas.hansson@arm.com .name(name() + ".cache_copies") 36911051Sandreas.hansson@arm.com .desc("number of cache copies performed") 37011199Sandreas.hansson@arm.com ; 37111199Sandreas.hansson@arm.com 37211199Sandreas.hansson@arm.com} 37311199Sandreas.hansson@arm.com