base.cc revision 13216
12810SN/A/* 212724Snikos.nikoleris@arm.com * Copyright (c) 2012-2013, 2018 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 4112724Snikos.nikoleris@arm.com * Nikos Nikoleris 422810SN/A */ 432810SN/A 442810SN/A/** 452810SN/A * @file 462810SN/A * Definition of BaseCache functions. 472810SN/A */ 482810SN/A 4911486Snikos.nikoleris@arm.com#include "mem/cache/base.hh" 5011486Snikos.nikoleris@arm.com 5112724Snikos.nikoleris@arm.com#include "base/compiler.hh" 5212724Snikos.nikoleris@arm.com#include "base/logging.hh" 538232Snate@binkert.org#include "debug/Cache.hh" 5412724Snikos.nikoleris@arm.com#include "debug/CachePort.hh" 5512724Snikos.nikoleris@arm.com#include "debug/CacheVerbose.hh" 5611486Snikos.nikoleris@arm.com#include "mem/cache/mshr.hh" 5712724Snikos.nikoleris@arm.com#include "mem/cache/prefetch/base.hh" 5812724Snikos.nikoleris@arm.com#include "mem/cache/queue_entry.hh" 5912724Snikos.nikoleris@arm.com#include "params/BaseCache.hh" 6012724Snikos.nikoleris@arm.com#include "sim/core.hh" 6112724Snikos.nikoleris@arm.com 6212724Snikos.nikoleris@arm.comclass BaseMasterPort; 6312724Snikos.nikoleris@arm.comclass BaseSlavePort; 642810SN/A 652810SN/Ausing namespace std; 662810SN/A 678856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 688856Sandreas.hansson@arm.com BaseCache *_cache, 698856Sandreas.hansson@arm.com const std::string &_label) 708922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 7112084Sspwilson2@wisc.edu blocked(false), mustSendRetry(false), 7212084Sspwilson2@wisc.edu sendRetryEvent([this]{ processSendRetry(); }, _name) 738856Sandreas.hansson@arm.com{ 748856Sandreas.hansson@arm.com} 754475SN/A 7611053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 775034SN/A : MemObject(p), 7812724Snikos.nikoleris@arm.com cpuSidePort (p->name + ".cpu_side", this, "CpuSidePort"), 7912724Snikos.nikoleris@arm.com memSidePort(p->name + ".mem_side", this, "MemSidePort"), 8011377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 8111377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 8212724Snikos.nikoleris@arm.com tags(p->tags), 8312724Snikos.nikoleris@arm.com prefetcher(p->prefetcher), 8412724Snikos.nikoleris@arm.com prefetchOnAccess(p->prefetch_on_access), 8512724Snikos.nikoleris@arm.com writebackClean(p->writeback_clean), 8612724Snikos.nikoleris@arm.com tempBlockWriteback(nullptr), 8712724Snikos.nikoleris@arm.com writebackTempBlockAtomicEvent([this]{ writebackTempBlockAtomic(); }, 8812724Snikos.nikoleris@arm.com name(), false, 8912724Snikos.nikoleris@arm.com EventBase::Delayed_Writeback_Pri), 9011053Sandreas.hansson@arm.com blkSize(blk_size), 9111722Ssophiane.senni@gmail.com lookupLatency(p->tag_latency), 9211722Ssophiane.senni@gmail.com dataLatency(p->data_latency), 9311722Ssophiane.senni@gmail.com forwardLatency(p->tag_latency), 9411722Ssophiane.senni@gmail.com fillLatency(p->data_latency), 959263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 965034SN/A numTarget(p->tgts_per_mshr), 9711331Sandreas.hansson@arm.com forwardSnoops(true), 9812724Snikos.nikoleris@arm.com clusivity(p->clusivity), 9910884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 1004626SN/A blocked(0), 10110360Sandreas.hansson@arm.com order(0), 10211484Snikos.nikoleris@arm.com noTargetMSHR(nullptr), 1035034SN/A missCount(p->max_miss_count), 1048883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 1058833Sdam.sunwoo@arm.com system(p->system) 1064458SN/A{ 10711377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 10811377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 10911377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 11011377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 11111377Sandreas.hansson@arm.com // buffer before committing to an MSHR 11211377Sandreas.hansson@arm.com 11311331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 11411331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 11512724Snikos.nikoleris@arm.com 11612843Srmk35@cl.cam.ac.uk tempBlock = new TempCacheBlk(blkSize); 11712724Snikos.nikoleris@arm.com 11813216Sodanrc@yahoo.com.br tags->init(this); 11912724Snikos.nikoleris@arm.com if (prefetcher) 12012724Snikos.nikoleris@arm.com prefetcher->setCache(this); 12112724Snikos.nikoleris@arm.com} 12212724Snikos.nikoleris@arm.com 12312724Snikos.nikoleris@arm.comBaseCache::~BaseCache() 12412724Snikos.nikoleris@arm.com{ 12512724Snikos.nikoleris@arm.com delete tempBlock; 1262810SN/A} 1272810SN/A 1283013SN/Avoid 1298856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1302810SN/A{ 1313013SN/A assert(!blocked); 13210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1332810SN/A blocked = true; 1349614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1359614Srene.dejong@arm.com // happened, cancel it 1369614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 13710345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 13810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 13910345SCurtis.Dunham@arm.com mustSendRetry = true; 1409614Srene.dejong@arm.com } 1412810SN/A} 1422810SN/A 1432810SN/Avoid 1448856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1452810SN/A{ 1463013SN/A assert(blocked); 14710714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1483013SN/A blocked = false; 1498856Sandreas.hansson@arm.com if (mustSendRetry) { 15010714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1518922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1522897SN/A } 1532810SN/A} 1542810SN/A 15510344Sandreas.hansson@arm.comvoid 15610344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 15710344Sandreas.hansson@arm.com{ 15810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 15910344Sandreas.hansson@arm.com 16010344Sandreas.hansson@arm.com // reset the flag and call retry 16110344Sandreas.hansson@arm.com mustSendRetry = false; 16210713Sandreas.hansson@arm.com sendRetryReq(); 16310344Sandreas.hansson@arm.com} 1642844SN/A 16512730Sodanrc@yahoo.com.brAddr 16612730Sodanrc@yahoo.com.brBaseCache::regenerateBlkAddr(CacheBlk* blk) 16712730Sodanrc@yahoo.com.br{ 16812730Sodanrc@yahoo.com.br if (blk != tempBlock) { 16912730Sodanrc@yahoo.com.br return tags->regenerateBlkAddr(blk); 17012730Sodanrc@yahoo.com.br } else { 17112730Sodanrc@yahoo.com.br return tempBlock->getAddr(); 17212730Sodanrc@yahoo.com.br } 17312730Sodanrc@yahoo.com.br} 17412730Sodanrc@yahoo.com.br 1752810SN/Avoid 1762858SN/ABaseCache::init() 1772858SN/A{ 17812724Snikos.nikoleris@arm.com if (!cpuSidePort.isConnected() || !memSidePort.isConnected()) 1798922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 18012724Snikos.nikoleris@arm.com cpuSidePort.sendRangeChange(); 18112724Snikos.nikoleris@arm.com forwardSnoops = cpuSidePort.isSnooping(); 1822858SN/A} 1832858SN/A 1849294Sandreas.hansson@arm.comBaseMasterPort & 1859294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1868922Swilliam.wang@arm.com{ 1878922Swilliam.wang@arm.com if (if_name == "mem_side") { 18812724Snikos.nikoleris@arm.com return memSidePort; 1898922Swilliam.wang@arm.com } else { 1908922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1918922Swilliam.wang@arm.com } 1928922Swilliam.wang@arm.com} 1938922Swilliam.wang@arm.com 1949294Sandreas.hansson@arm.comBaseSlavePort & 1959294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1968922Swilliam.wang@arm.com{ 1978922Swilliam.wang@arm.com if (if_name == "cpu_side") { 19812724Snikos.nikoleris@arm.com return cpuSidePort; 1998922Swilliam.wang@arm.com } else { 2008922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 2018922Swilliam.wang@arm.com } 2028922Swilliam.wang@arm.com} 2034628SN/A 20410821Sandreas.hansson@arm.combool 20510821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 20610821Sandreas.hansson@arm.com{ 20710821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 20810821Sandreas.hansson@arm.com if (r.contains(addr)) { 20910821Sandreas.hansson@arm.com return true; 21010821Sandreas.hansson@arm.com } 21110821Sandreas.hansson@arm.com } 21210821Sandreas.hansson@arm.com return false; 21310821Sandreas.hansson@arm.com} 21410821Sandreas.hansson@arm.com 2152858SN/Avoid 21612724Snikos.nikoleris@arm.comBaseCache::handleTimingReqHit(PacketPtr pkt, CacheBlk *blk, Tick request_time) 21712724Snikos.nikoleris@arm.com{ 21812724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 21912724Snikos.nikoleris@arm.com pkt->makeTimingResponse(); 22012724Snikos.nikoleris@arm.com // @todo: Make someone pay for this 22112724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 22212724Snikos.nikoleris@arm.com 22312724Snikos.nikoleris@arm.com // In this case we are considering request_time that takes 22412724Snikos.nikoleris@arm.com // into account the delay of the xbar, if any, and just 22512724Snikos.nikoleris@arm.com // lat, neglecting responseLatency, modelling hit latency 22612724Snikos.nikoleris@arm.com // just as lookupLatency or or the value of lat overriden 22712724Snikos.nikoleris@arm.com // by access(), that calls accessBlock() function. 22812724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, request_time, true); 22912724Snikos.nikoleris@arm.com } else { 23012724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s satisfied %s, no response needed\n", __func__, 23112724Snikos.nikoleris@arm.com pkt->print()); 23212724Snikos.nikoleris@arm.com 23312724Snikos.nikoleris@arm.com // queue the packet for deletion, as the sending cache is 23412724Snikos.nikoleris@arm.com // still relying on it; if the block is found in access(), 23512724Snikos.nikoleris@arm.com // CleanEvict and Writeback messages will be deleted 23612724Snikos.nikoleris@arm.com // here as well 23712724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 23812724Snikos.nikoleris@arm.com } 23912724Snikos.nikoleris@arm.com} 24012724Snikos.nikoleris@arm.com 24112724Snikos.nikoleris@arm.comvoid 24212724Snikos.nikoleris@arm.comBaseCache::handleTimingReqMiss(PacketPtr pkt, MSHR *mshr, CacheBlk *blk, 24312724Snikos.nikoleris@arm.com Tick forward_time, Tick request_time) 24412724Snikos.nikoleris@arm.com{ 24512724Snikos.nikoleris@arm.com if (mshr) { 24612724Snikos.nikoleris@arm.com /// MSHR hit 24712724Snikos.nikoleris@arm.com /// @note writebacks will be checked in getNextMSHR() 24812724Snikos.nikoleris@arm.com /// for any conflicting requests to the same block 24912724Snikos.nikoleris@arm.com 25012724Snikos.nikoleris@arm.com //@todo remove hw_pf here 25112724Snikos.nikoleris@arm.com 25212724Snikos.nikoleris@arm.com // Coalesce unless it was a software prefetch (see above). 25312724Snikos.nikoleris@arm.com if (pkt) { 25412724Snikos.nikoleris@arm.com assert(!pkt->isWriteback()); 25512724Snikos.nikoleris@arm.com // CleanEvicts corresponding to blocks which have 25612724Snikos.nikoleris@arm.com // outstanding requests in MSHRs are simply sunk here 25712724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::CleanEvict) { 25812724Snikos.nikoleris@arm.com pendingDelete.reset(pkt); 25912724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 26012724Snikos.nikoleris@arm.com // A WriteClean should never coalesce with any 26112724Snikos.nikoleris@arm.com // outstanding cache maintenance requests. 26212724Snikos.nikoleris@arm.com 26312724Snikos.nikoleris@arm.com // We use forward_time here because there is an 26412724Snikos.nikoleris@arm.com // uncached memory write, forwarded to WriteBuffer. 26512724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 26612724Snikos.nikoleris@arm.com } else { 26712724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s coalescing MSHR for %s\n", __func__, 26812724Snikos.nikoleris@arm.com pkt->print()); 26912724Snikos.nikoleris@arm.com 27012724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 27112724Snikos.nikoleris@arm.com mshr_hits[pkt->cmdToIndex()][pkt->req->masterId()]++; 27212724Snikos.nikoleris@arm.com 27312724Snikos.nikoleris@arm.com // We use forward_time here because it is the same 27412724Snikos.nikoleris@arm.com // considering new targets. We have multiple 27512724Snikos.nikoleris@arm.com // requests for the same address here. It 27612724Snikos.nikoleris@arm.com // specifies the latency to allocate an internal 27712724Snikos.nikoleris@arm.com // buffer and to schedule an event to the queued 27812724Snikos.nikoleris@arm.com // port and also takes into account the additional 27912724Snikos.nikoleris@arm.com // delay of the xbar. 28012724Snikos.nikoleris@arm.com mshr->allocateTarget(pkt, forward_time, order++, 28112724Snikos.nikoleris@arm.com allocOnFill(pkt->cmd)); 28212724Snikos.nikoleris@arm.com if (mshr->getNumTargets() == numTarget) { 28312724Snikos.nikoleris@arm.com noTargetMSHR = mshr; 28412724Snikos.nikoleris@arm.com setBlocked(Blocked_NoTargets); 28512724Snikos.nikoleris@arm.com // need to be careful with this... if this mshr isn't 28612724Snikos.nikoleris@arm.com // ready yet (i.e. time > curTick()), we don't want to 28712724Snikos.nikoleris@arm.com // move it ahead of mshrs that are ready 28812724Snikos.nikoleris@arm.com // mshrQueue.moveToFront(mshr); 28912724Snikos.nikoleris@arm.com } 29012724Snikos.nikoleris@arm.com } 29112724Snikos.nikoleris@arm.com } 29212724Snikos.nikoleris@arm.com } else { 29312724Snikos.nikoleris@arm.com // no MSHR 29412724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 29512724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 29612724Snikos.nikoleris@arm.com 29712724Snikos.nikoleris@arm.com if (pkt->isEviction() || pkt->cmd == MemCmd::WriteClean) { 29812724Snikos.nikoleris@arm.com // We use forward_time here because there is an 29912724Snikos.nikoleris@arm.com // writeback or writeclean, forwarded to WriteBuffer. 30012724Snikos.nikoleris@arm.com allocateWriteBuffer(pkt, forward_time); 30112724Snikos.nikoleris@arm.com } else { 30212724Snikos.nikoleris@arm.com if (blk && blk->isValid()) { 30312724Snikos.nikoleris@arm.com // If we have a write miss to a valid block, we 30412724Snikos.nikoleris@arm.com // need to mark the block non-readable. Otherwise 30512724Snikos.nikoleris@arm.com // if we allow reads while there's an outstanding 30612724Snikos.nikoleris@arm.com // write miss, the read could return stale data 30712724Snikos.nikoleris@arm.com // out of the cache block... a more aggressive 30812724Snikos.nikoleris@arm.com // system could detect the overlap (if any) and 30912724Snikos.nikoleris@arm.com // forward data out of the MSHRs, but we don't do 31012724Snikos.nikoleris@arm.com // that yet. Note that we do need to leave the 31112724Snikos.nikoleris@arm.com // block valid so that it stays in the cache, in 31212724Snikos.nikoleris@arm.com // case we get an upgrade response (and hence no 31312724Snikos.nikoleris@arm.com // new data) when the write miss completes. 31412724Snikos.nikoleris@arm.com // As long as CPUs do proper store/load forwarding 31512724Snikos.nikoleris@arm.com // internally, and have a sufficiently weak memory 31612724Snikos.nikoleris@arm.com // model, this is probably unnecessary, but at some 31712724Snikos.nikoleris@arm.com // point it must have seemed like we needed it... 31812724Snikos.nikoleris@arm.com assert((pkt->needsWritable() && !blk->isWritable()) || 31912724Snikos.nikoleris@arm.com pkt->req->isCacheMaintenance()); 32012724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 32112724Snikos.nikoleris@arm.com } 32212724Snikos.nikoleris@arm.com // Here we are using forward_time, modelling the latency of 32312724Snikos.nikoleris@arm.com // a miss (outbound) just as forwardLatency, neglecting the 32412724Snikos.nikoleris@arm.com // lookupLatency component. 32512724Snikos.nikoleris@arm.com allocateMissBuffer(pkt, forward_time); 32612724Snikos.nikoleris@arm.com } 32712724Snikos.nikoleris@arm.com } 32812724Snikos.nikoleris@arm.com} 32912724Snikos.nikoleris@arm.com 33012724Snikos.nikoleris@arm.comvoid 33112724Snikos.nikoleris@arm.comBaseCache::recvTimingReq(PacketPtr pkt) 33212724Snikos.nikoleris@arm.com{ 33312724Snikos.nikoleris@arm.com // anything that is merely forwarded pays for the forward latency and 33412724Snikos.nikoleris@arm.com // the delay provided by the crossbar 33512724Snikos.nikoleris@arm.com Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 33612724Snikos.nikoleris@arm.com 33712724Snikos.nikoleris@arm.com // We use lookupLatency here because it is used to specify the latency 33812724Snikos.nikoleris@arm.com // to access. 33912724Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 34012724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 34112724Snikos.nikoleris@arm.com bool satisfied = false; 34212724Snikos.nikoleris@arm.com { 34312724Snikos.nikoleris@arm.com PacketList writebacks; 34412724Snikos.nikoleris@arm.com // Note that lat is passed by reference here. The function 34512724Snikos.nikoleris@arm.com // access() calls accessBlock() which can modify lat value. 34612724Snikos.nikoleris@arm.com satisfied = access(pkt, blk, lat, writebacks); 34712724Snikos.nikoleris@arm.com 34812724Snikos.nikoleris@arm.com // copy writebacks to write buffer here to ensure they logically 34912820Srmk35@cl.cam.ac.uk // precede anything happening below 35012724Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 35112724Snikos.nikoleris@arm.com } 35212724Snikos.nikoleris@arm.com 35312724Snikos.nikoleris@arm.com // Here we charge the headerDelay that takes into account the latencies 35412724Snikos.nikoleris@arm.com // of the bus, if the packet comes from it. 35512724Snikos.nikoleris@arm.com // The latency charged it is just lat that is the value of lookupLatency 35612724Snikos.nikoleris@arm.com // modified by access() function, or if not just lookupLatency. 35712724Snikos.nikoleris@arm.com // In case of a hit we are neglecting response latency. 35812724Snikos.nikoleris@arm.com // In case of a miss we are neglecting forward latency. 35912724Snikos.nikoleris@arm.com Tick request_time = clockEdge(lat) + pkt->headerDelay; 36012724Snikos.nikoleris@arm.com // Here we reset the timing of the packet. 36112724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 36212724Snikos.nikoleris@arm.com // track time of availability of next prefetch, if any 36312724Snikos.nikoleris@arm.com Tick next_pf_time = MaxTick; 36412724Snikos.nikoleris@arm.com 36512724Snikos.nikoleris@arm.com if (satisfied) { 36612724Snikos.nikoleris@arm.com // if need to notify the prefetcher we have to do it before 36712724Snikos.nikoleris@arm.com // anything else as later handleTimingReqHit might turn the 36812724Snikos.nikoleris@arm.com // packet in a response 36912724Snikos.nikoleris@arm.com if (prefetcher && 37012724Snikos.nikoleris@arm.com (prefetchOnAccess || (blk && blk->wasPrefetched()))) { 37112724Snikos.nikoleris@arm.com if (blk) 37212724Snikos.nikoleris@arm.com blk->status &= ~BlkHWPrefetched; 37312724Snikos.nikoleris@arm.com 37412724Snikos.nikoleris@arm.com // Don't notify on SWPrefetch 37512724Snikos.nikoleris@arm.com if (!pkt->cmd.isSWPrefetch()) { 37612724Snikos.nikoleris@arm.com assert(!pkt->req->isCacheMaintenance()); 37712724Snikos.nikoleris@arm.com next_pf_time = prefetcher->notify(pkt); 37812724Snikos.nikoleris@arm.com } 37912724Snikos.nikoleris@arm.com } 38012724Snikos.nikoleris@arm.com 38112724Snikos.nikoleris@arm.com handleTimingReqHit(pkt, blk, request_time); 38212724Snikos.nikoleris@arm.com } else { 38312724Snikos.nikoleris@arm.com handleTimingReqMiss(pkt, blk, forward_time, request_time); 38412724Snikos.nikoleris@arm.com 38512724Snikos.nikoleris@arm.com // We should call the prefetcher reguardless if the request is 38612724Snikos.nikoleris@arm.com // satisfied or not, reguardless if the request is in the MSHR 38712724Snikos.nikoleris@arm.com // or not. The request could be a ReadReq hit, but still not 38812724Snikos.nikoleris@arm.com // satisfied (potentially because of a prior write to the same 38912724Snikos.nikoleris@arm.com // cache line. So, even when not satisfied, there is an MSHR 39012724Snikos.nikoleris@arm.com // already allocated for this, we need to let the prefetcher 39112724Snikos.nikoleris@arm.com // know about the request 39212724Snikos.nikoleris@arm.com 39312724Snikos.nikoleris@arm.com // Don't notify prefetcher on SWPrefetch or cache maintenance 39412724Snikos.nikoleris@arm.com // operations 39512724Snikos.nikoleris@arm.com if (prefetcher && pkt && 39612724Snikos.nikoleris@arm.com !pkt->cmd.isSWPrefetch() && 39712724Snikos.nikoleris@arm.com !pkt->req->isCacheMaintenance()) { 39812724Snikos.nikoleris@arm.com next_pf_time = prefetcher->notify(pkt); 39912724Snikos.nikoleris@arm.com } 40012724Snikos.nikoleris@arm.com } 40112724Snikos.nikoleris@arm.com 40212724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) { 40312724Snikos.nikoleris@arm.com schedMemSideSendEvent(next_pf_time); 40412724Snikos.nikoleris@arm.com } 40512724Snikos.nikoleris@arm.com} 40612724Snikos.nikoleris@arm.com 40712724Snikos.nikoleris@arm.comvoid 40812724Snikos.nikoleris@arm.comBaseCache::handleUncacheableWriteResp(PacketPtr pkt) 40912724Snikos.nikoleris@arm.com{ 41012724Snikos.nikoleris@arm.com Tick completion_time = clockEdge(responseLatency) + 41112724Snikos.nikoleris@arm.com pkt->headerDelay + pkt->payloadDelay; 41212724Snikos.nikoleris@arm.com 41312724Snikos.nikoleris@arm.com // Reset the bus additional time as it is now accounted for 41412724Snikos.nikoleris@arm.com pkt->headerDelay = pkt->payloadDelay = 0; 41512724Snikos.nikoleris@arm.com 41612724Snikos.nikoleris@arm.com cpuSidePort.schedTimingResp(pkt, completion_time, true); 41712724Snikos.nikoleris@arm.com} 41812724Snikos.nikoleris@arm.com 41912724Snikos.nikoleris@arm.comvoid 42012724Snikos.nikoleris@arm.comBaseCache::recvTimingResp(PacketPtr pkt) 42112724Snikos.nikoleris@arm.com{ 42212724Snikos.nikoleris@arm.com assert(pkt->isResponse()); 42312724Snikos.nikoleris@arm.com 42412724Snikos.nikoleris@arm.com // all header delay should be paid for by the crossbar, unless 42512724Snikos.nikoleris@arm.com // this is a prefetch response from above 42612724Snikos.nikoleris@arm.com panic_if(pkt->headerDelay != 0 && pkt->cmd != MemCmd::HardPFResp, 42712724Snikos.nikoleris@arm.com "%s saw a non-zero packet delay\n", name()); 42812724Snikos.nikoleris@arm.com 42912724Snikos.nikoleris@arm.com const bool is_error = pkt->isError(); 43012724Snikos.nikoleris@arm.com 43112724Snikos.nikoleris@arm.com if (is_error) { 43212724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Cache received %s with error\n", __func__, 43312724Snikos.nikoleris@arm.com pkt->print()); 43412724Snikos.nikoleris@arm.com } 43512724Snikos.nikoleris@arm.com 43612724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: Handling response %s\n", __func__, 43712724Snikos.nikoleris@arm.com pkt->print()); 43812724Snikos.nikoleris@arm.com 43912724Snikos.nikoleris@arm.com // if this is a write, we should be looking at an uncacheable 44012724Snikos.nikoleris@arm.com // write 44112724Snikos.nikoleris@arm.com if (pkt->isWrite()) { 44212724Snikos.nikoleris@arm.com assert(pkt->req->isUncacheable()); 44312724Snikos.nikoleris@arm.com handleUncacheableWriteResp(pkt); 44412724Snikos.nikoleris@arm.com return; 44512724Snikos.nikoleris@arm.com } 44612724Snikos.nikoleris@arm.com 44712724Snikos.nikoleris@arm.com // we have dealt with any (uncacheable) writes above, from here on 44812724Snikos.nikoleris@arm.com // we know we are dealing with an MSHR due to a miss or a prefetch 44912724Snikos.nikoleris@arm.com MSHR *mshr = dynamic_cast<MSHR*>(pkt->popSenderState()); 45012724Snikos.nikoleris@arm.com assert(mshr); 45112724Snikos.nikoleris@arm.com 45212724Snikos.nikoleris@arm.com if (mshr == noTargetMSHR) { 45312724Snikos.nikoleris@arm.com // we always clear at least one target 45412724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoTargets); 45512724Snikos.nikoleris@arm.com noTargetMSHR = nullptr; 45612724Snikos.nikoleris@arm.com } 45712724Snikos.nikoleris@arm.com 45812724Snikos.nikoleris@arm.com // Initial target is used just for stats 45912724Snikos.nikoleris@arm.com MSHR::Target *initial_tgt = mshr->getTarget(); 46012724Snikos.nikoleris@arm.com int stats_cmd_idx = initial_tgt->pkt->cmdToIndex(); 46112724Snikos.nikoleris@arm.com Tick miss_latency = curTick() - initial_tgt->recvTime; 46212724Snikos.nikoleris@arm.com 46312724Snikos.nikoleris@arm.com if (pkt->req->isUncacheable()) { 46412724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 46512724Snikos.nikoleris@arm.com mshr_uncacheable_lat[stats_cmd_idx][pkt->req->masterId()] += 46612724Snikos.nikoleris@arm.com miss_latency; 46712724Snikos.nikoleris@arm.com } else { 46812724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 46912724Snikos.nikoleris@arm.com mshr_miss_latency[stats_cmd_idx][pkt->req->masterId()] += 47012724Snikos.nikoleris@arm.com miss_latency; 47112724Snikos.nikoleris@arm.com } 47212724Snikos.nikoleris@arm.com 47312724Snikos.nikoleris@arm.com PacketList writebacks; 47412724Snikos.nikoleris@arm.com 47512724Snikos.nikoleris@arm.com bool is_fill = !mshr->isForward && 47612724Snikos.nikoleris@arm.com (pkt->isRead() || pkt->cmd == MemCmd::UpgradeResp); 47712724Snikos.nikoleris@arm.com 47812724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), pkt->isSecure()); 47912724Snikos.nikoleris@arm.com 48012724Snikos.nikoleris@arm.com if (is_fill && !is_error) { 48112724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block for addr %#llx being updated in Cache\n", 48212724Snikos.nikoleris@arm.com pkt->getAddr()); 48312724Snikos.nikoleris@arm.com 48412724Snikos.nikoleris@arm.com blk = handleFill(pkt, blk, writebacks, mshr->allocOnFill()); 48512724Snikos.nikoleris@arm.com assert(blk != nullptr); 48612724Snikos.nikoleris@arm.com } 48712724Snikos.nikoleris@arm.com 48812724Snikos.nikoleris@arm.com if (blk && blk->isValid() && pkt->isClean() && !pkt->isInvalidate()) { 48912724Snikos.nikoleris@arm.com // The block was marked not readable while there was a pending 49012724Snikos.nikoleris@arm.com // cache maintenance operation, restore its flag. 49112724Snikos.nikoleris@arm.com blk->status |= BlkReadable; 49212794Snikos.nikoleris@arm.com 49312794Snikos.nikoleris@arm.com // This was a cache clean operation (without invalidate) 49412794Snikos.nikoleris@arm.com // and we have a copy of the block already. Since there 49512794Snikos.nikoleris@arm.com // is no invalidation, we can promote targets that don't 49612794Snikos.nikoleris@arm.com // require a writable copy 49712794Snikos.nikoleris@arm.com mshr->promoteReadable(); 49812724Snikos.nikoleris@arm.com } 49912724Snikos.nikoleris@arm.com 50012724Snikos.nikoleris@arm.com if (blk && blk->isWritable() && !pkt->req->isCacheInvalidate()) { 50112724Snikos.nikoleris@arm.com // If at this point the referenced block is writable and the 50212724Snikos.nikoleris@arm.com // response is not a cache invalidate, we promote targets that 50312724Snikos.nikoleris@arm.com // were deferred as we couldn't guarrantee a writable copy 50412724Snikos.nikoleris@arm.com mshr->promoteWritable(); 50512724Snikos.nikoleris@arm.com } 50612724Snikos.nikoleris@arm.com 50712724Snikos.nikoleris@arm.com serviceMSHRTargets(mshr, pkt, blk, writebacks); 50812724Snikos.nikoleris@arm.com 50912724Snikos.nikoleris@arm.com if (mshr->promoteDeferredTargets()) { 51012724Snikos.nikoleris@arm.com // avoid later read getting stale data while write miss is 51112724Snikos.nikoleris@arm.com // outstanding.. see comment in timingAccess() 51212724Snikos.nikoleris@arm.com if (blk) { 51312724Snikos.nikoleris@arm.com blk->status &= ~BlkReadable; 51412724Snikos.nikoleris@arm.com } 51512724Snikos.nikoleris@arm.com mshrQueue.markPending(mshr); 51612724Snikos.nikoleris@arm.com schedMemSideSendEvent(clockEdge() + pkt->payloadDelay); 51712724Snikos.nikoleris@arm.com } else { 51812724Snikos.nikoleris@arm.com // while we deallocate an mshr from the queue we still have to 51912724Snikos.nikoleris@arm.com // check the isFull condition before and after as we might 52012724Snikos.nikoleris@arm.com // have been using the reserved entries already 52112724Snikos.nikoleris@arm.com const bool was_full = mshrQueue.isFull(); 52212724Snikos.nikoleris@arm.com mshrQueue.deallocate(mshr); 52312724Snikos.nikoleris@arm.com if (was_full && !mshrQueue.isFull()) { 52412724Snikos.nikoleris@arm.com clearBlocked(Blocked_NoMSHRs); 52512724Snikos.nikoleris@arm.com } 52612724Snikos.nikoleris@arm.com 52712724Snikos.nikoleris@arm.com // Request the bus for a prefetch if this deallocation freed enough 52812724Snikos.nikoleris@arm.com // MSHRs for a prefetch to take place 52912724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 53012724Snikos.nikoleris@arm.com Tick next_pf_time = std::max(prefetcher->nextPrefetchReadyTime(), 53112724Snikos.nikoleris@arm.com clockEdge()); 53212724Snikos.nikoleris@arm.com if (next_pf_time != MaxTick) 53312724Snikos.nikoleris@arm.com schedMemSideSendEvent(next_pf_time); 53412724Snikos.nikoleris@arm.com } 53512724Snikos.nikoleris@arm.com } 53612724Snikos.nikoleris@arm.com 53712724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and then clear it out 53812724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 53912724Snikos.nikoleris@arm.com evictBlock(blk, writebacks); 54012724Snikos.nikoleris@arm.com } 54112724Snikos.nikoleris@arm.com 54212724Snikos.nikoleris@arm.com const Tick forward_time = clockEdge(forwardLatency) + pkt->headerDelay; 54312724Snikos.nikoleris@arm.com // copy writebacks to write buffer 54412724Snikos.nikoleris@arm.com doWritebacks(writebacks, forward_time); 54512724Snikos.nikoleris@arm.com 54612724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: Leaving with %s\n", __func__, pkt->print()); 54712724Snikos.nikoleris@arm.com delete pkt; 54812724Snikos.nikoleris@arm.com} 54912724Snikos.nikoleris@arm.com 55012724Snikos.nikoleris@arm.com 55112724Snikos.nikoleris@arm.comTick 55212724Snikos.nikoleris@arm.comBaseCache::recvAtomic(PacketPtr pkt) 55312724Snikos.nikoleris@arm.com{ 55412724Snikos.nikoleris@arm.com // We are in atomic mode so we pay just for lookupLatency here. 55512724Snikos.nikoleris@arm.com Cycles lat = lookupLatency; 55612724Snikos.nikoleris@arm.com 55712724Snikos.nikoleris@arm.com // follow the same flow as in recvTimingReq, and check if a cache 55812724Snikos.nikoleris@arm.com // above us is responding 55912724Snikos.nikoleris@arm.com if (pkt->cacheResponding() && !pkt->isClean()) { 56012724Snikos.nikoleris@arm.com assert(!pkt->req->isCacheInvalidate()); 56112724Snikos.nikoleris@arm.com DPRINTF(Cache, "Cache above responding to %s: not responding\n", 56212724Snikos.nikoleris@arm.com pkt->print()); 56312724Snikos.nikoleris@arm.com 56412724Snikos.nikoleris@arm.com // if a cache is responding, and it had the line in Owned 56512724Snikos.nikoleris@arm.com // rather than Modified state, we need to invalidate any 56612724Snikos.nikoleris@arm.com // copies that are not on the same path to memory 56712724Snikos.nikoleris@arm.com assert(pkt->needsWritable() && !pkt->responderHadWritable()); 56812724Snikos.nikoleris@arm.com lat += ticksToCycles(memSidePort.sendAtomic(pkt)); 56912724Snikos.nikoleris@arm.com 57012724Snikos.nikoleris@arm.com return lat * clockPeriod(); 57112724Snikos.nikoleris@arm.com } 57212724Snikos.nikoleris@arm.com 57312724Snikos.nikoleris@arm.com // should assert here that there are no outstanding MSHRs or 57412724Snikos.nikoleris@arm.com // writebacks... that would mean that someone used an atomic 57512724Snikos.nikoleris@arm.com // access in timing mode 57612724Snikos.nikoleris@arm.com 57712724Snikos.nikoleris@arm.com CacheBlk *blk = nullptr; 57812724Snikos.nikoleris@arm.com PacketList writebacks; 57912724Snikos.nikoleris@arm.com bool satisfied = access(pkt, blk, lat, writebacks); 58012724Snikos.nikoleris@arm.com 58112724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 58212724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 58312724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 58412724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 58512724Snikos.nikoleris@arm.com // until the point of reference. 58612724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 58712724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 58812724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), pkt->id); 58912724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 59012724Snikos.nikoleris@arm.com pkt->setSatisfied(); 59112724Snikos.nikoleris@arm.com } 59212724Snikos.nikoleris@arm.com 59312724Snikos.nikoleris@arm.com // handle writebacks resulting from the access here to ensure they 59412820Srmk35@cl.cam.ac.uk // logically precede anything happening below 59512724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 59612724Snikos.nikoleris@arm.com assert(writebacks.empty()); 59712724Snikos.nikoleris@arm.com 59812724Snikos.nikoleris@arm.com if (!satisfied) { 59912724Snikos.nikoleris@arm.com lat += handleAtomicReqMiss(pkt, blk, writebacks); 60012724Snikos.nikoleris@arm.com } 60112724Snikos.nikoleris@arm.com 60212724Snikos.nikoleris@arm.com // Note that we don't invoke the prefetcher at all in atomic mode. 60312724Snikos.nikoleris@arm.com // It's not clear how to do it properly, particularly for 60412724Snikos.nikoleris@arm.com // prefetchers that aggressively generate prefetch candidates and 60512724Snikos.nikoleris@arm.com // rely on bandwidth contention to throttle them; these will tend 60612724Snikos.nikoleris@arm.com // to pollute the cache in atomic mode since there is no bandwidth 60712724Snikos.nikoleris@arm.com // contention. If we ever do want to enable prefetching in atomic 60812724Snikos.nikoleris@arm.com // mode, though, this is the place to do it... see timingAccess() 60912724Snikos.nikoleris@arm.com // for an example (though we'd want to issue the prefetch(es) 61012724Snikos.nikoleris@arm.com // immediately rather than calling requestMemSideBus() as we do 61112724Snikos.nikoleris@arm.com // there). 61212724Snikos.nikoleris@arm.com 61312724Snikos.nikoleris@arm.com // do any writebacks resulting from the response handling 61412724Snikos.nikoleris@arm.com doWritebacksAtomic(writebacks); 61512724Snikos.nikoleris@arm.com 61612724Snikos.nikoleris@arm.com // if we used temp block, check to see if its valid and if so 61712724Snikos.nikoleris@arm.com // clear it out, but only do so after the call to recvAtomic is 61812724Snikos.nikoleris@arm.com // finished so that any downstream observers (such as a snoop 61912724Snikos.nikoleris@arm.com // filter), first see the fill, and only then see the eviction 62012724Snikos.nikoleris@arm.com if (blk == tempBlock && tempBlock->isValid()) { 62112724Snikos.nikoleris@arm.com // the atomic CPU calls recvAtomic for fetch and load/store 62212724Snikos.nikoleris@arm.com // sequentuially, and we may already have a tempBlock 62312724Snikos.nikoleris@arm.com // writeback from the fetch that we have not yet sent 62412724Snikos.nikoleris@arm.com if (tempBlockWriteback) { 62512724Snikos.nikoleris@arm.com // if that is the case, write the prevoius one back, and 62612724Snikos.nikoleris@arm.com // do not schedule any new event 62712724Snikos.nikoleris@arm.com writebackTempBlockAtomic(); 62812724Snikos.nikoleris@arm.com } else { 62912724Snikos.nikoleris@arm.com // the writeback/clean eviction happens after the call to 63012724Snikos.nikoleris@arm.com // recvAtomic has finished (but before any successive 63112724Snikos.nikoleris@arm.com // calls), so that the response handling from the fill is 63212724Snikos.nikoleris@arm.com // allowed to happen first 63312724Snikos.nikoleris@arm.com schedule(writebackTempBlockAtomicEvent, curTick()); 63412724Snikos.nikoleris@arm.com } 63512724Snikos.nikoleris@arm.com 63612724Snikos.nikoleris@arm.com tempBlockWriteback = evictBlock(blk); 63712724Snikos.nikoleris@arm.com } 63812724Snikos.nikoleris@arm.com 63912724Snikos.nikoleris@arm.com if (pkt->needsResponse()) { 64012724Snikos.nikoleris@arm.com pkt->makeAtomicResponse(); 64112724Snikos.nikoleris@arm.com } 64212724Snikos.nikoleris@arm.com 64312724Snikos.nikoleris@arm.com return lat * clockPeriod(); 64412724Snikos.nikoleris@arm.com} 64512724Snikos.nikoleris@arm.com 64612724Snikos.nikoleris@arm.comvoid 64712724Snikos.nikoleris@arm.comBaseCache::functionalAccess(PacketPtr pkt, bool from_cpu_side) 64812724Snikos.nikoleris@arm.com{ 64912724Snikos.nikoleris@arm.com Addr blk_addr = pkt->getBlockAddr(blkSize); 65012724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 65112724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(pkt->getAddr(), is_secure); 65212724Snikos.nikoleris@arm.com MSHR *mshr = mshrQueue.findMatch(blk_addr, is_secure); 65312724Snikos.nikoleris@arm.com 65412724Snikos.nikoleris@arm.com pkt->pushLabel(name()); 65512724Snikos.nikoleris@arm.com 65612724Snikos.nikoleris@arm.com CacheBlkPrintWrapper cbpw(blk); 65712724Snikos.nikoleris@arm.com 65812724Snikos.nikoleris@arm.com // Note that just because an L2/L3 has valid data doesn't mean an 65912724Snikos.nikoleris@arm.com // L1 doesn't have a more up-to-date modified copy that still 66012724Snikos.nikoleris@arm.com // needs to be found. As a result we always update the request if 66112724Snikos.nikoleris@arm.com // we have it, but only declare it satisfied if we are the owner. 66212724Snikos.nikoleris@arm.com 66312724Snikos.nikoleris@arm.com // see if we have data at all (owned or otherwise) 66412724Snikos.nikoleris@arm.com bool have_data = blk && blk->isValid() 66512823Srmk35@cl.cam.ac.uk && pkt->trySatisfyFunctional(&cbpw, blk_addr, is_secure, blkSize, 66612823Srmk35@cl.cam.ac.uk blk->data); 66712724Snikos.nikoleris@arm.com 66812724Snikos.nikoleris@arm.com // data we have is dirty if marked as such or if we have an 66912724Snikos.nikoleris@arm.com // in-service MSHR that is pending a modified line 67012724Snikos.nikoleris@arm.com bool have_dirty = 67112724Snikos.nikoleris@arm.com have_data && (blk->isDirty() || 67212724Snikos.nikoleris@arm.com (mshr && mshr->inService && mshr->isPendingModified())); 67312724Snikos.nikoleris@arm.com 67412724Snikos.nikoleris@arm.com bool done = have_dirty || 67512823Srmk35@cl.cam.ac.uk cpuSidePort.trySatisfyFunctional(pkt) || 67612823Srmk35@cl.cam.ac.uk mshrQueue.trySatisfyFunctional(pkt, blk_addr) || 67712823Srmk35@cl.cam.ac.uk writeBuffer.trySatisfyFunctional(pkt, blk_addr) || 67812823Srmk35@cl.cam.ac.uk memSidePort.trySatisfyFunctional(pkt); 67912724Snikos.nikoleris@arm.com 68012724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: %s %s%s%s\n", __func__, pkt->print(), 68112724Snikos.nikoleris@arm.com (blk && blk->isValid()) ? "valid " : "", 68212724Snikos.nikoleris@arm.com have_data ? "data " : "", done ? "done " : ""); 68312724Snikos.nikoleris@arm.com 68412724Snikos.nikoleris@arm.com // We're leaving the cache, so pop cache->name() label 68512724Snikos.nikoleris@arm.com pkt->popLabel(); 68612724Snikos.nikoleris@arm.com 68712724Snikos.nikoleris@arm.com if (done) { 68812724Snikos.nikoleris@arm.com pkt->makeResponse(); 68912724Snikos.nikoleris@arm.com } else { 69012724Snikos.nikoleris@arm.com // if it came as a request from the CPU side then make sure it 69112724Snikos.nikoleris@arm.com // continues towards the memory side 69212724Snikos.nikoleris@arm.com if (from_cpu_side) { 69312724Snikos.nikoleris@arm.com memSidePort.sendFunctional(pkt); 69412724Snikos.nikoleris@arm.com } else if (cpuSidePort.isSnooping()) { 69512724Snikos.nikoleris@arm.com // if it came from the memory side, it must be a snoop request 69612724Snikos.nikoleris@arm.com // and we should only forward it if we are forwarding snoops 69712724Snikos.nikoleris@arm.com cpuSidePort.sendFunctionalSnoop(pkt); 69812724Snikos.nikoleris@arm.com } 69912724Snikos.nikoleris@arm.com } 70012724Snikos.nikoleris@arm.com} 70112724Snikos.nikoleris@arm.com 70212724Snikos.nikoleris@arm.com 70312724Snikos.nikoleris@arm.comvoid 70412724Snikos.nikoleris@arm.comBaseCache::cmpAndSwap(CacheBlk *blk, PacketPtr pkt) 70512724Snikos.nikoleris@arm.com{ 70612724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 70712724Snikos.nikoleris@arm.com 70812724Snikos.nikoleris@arm.com uint64_t overwrite_val; 70912724Snikos.nikoleris@arm.com bool overwrite_mem; 71012724Snikos.nikoleris@arm.com uint64_t condition_val64; 71112724Snikos.nikoleris@arm.com uint32_t condition_val32; 71212724Snikos.nikoleris@arm.com 71312724Snikos.nikoleris@arm.com int offset = pkt->getOffset(blkSize); 71412724Snikos.nikoleris@arm.com uint8_t *blk_data = blk->data + offset; 71512724Snikos.nikoleris@arm.com 71612724Snikos.nikoleris@arm.com assert(sizeof(uint64_t) >= pkt->getSize()); 71712724Snikos.nikoleris@arm.com 71812724Snikos.nikoleris@arm.com overwrite_mem = true; 71912724Snikos.nikoleris@arm.com // keep a copy of our possible write value, and copy what is at the 72012724Snikos.nikoleris@arm.com // memory address into the packet 72112724Snikos.nikoleris@arm.com pkt->writeData((uint8_t *)&overwrite_val); 72212724Snikos.nikoleris@arm.com pkt->setData(blk_data); 72312724Snikos.nikoleris@arm.com 72412724Snikos.nikoleris@arm.com if (pkt->req->isCondSwap()) { 72512724Snikos.nikoleris@arm.com if (pkt->getSize() == sizeof(uint64_t)) { 72612724Snikos.nikoleris@arm.com condition_val64 = pkt->req->getExtraData(); 72712724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val64, blk_data, 72812724Snikos.nikoleris@arm.com sizeof(uint64_t)); 72912724Snikos.nikoleris@arm.com } else if (pkt->getSize() == sizeof(uint32_t)) { 73012724Snikos.nikoleris@arm.com condition_val32 = (uint32_t)pkt->req->getExtraData(); 73112724Snikos.nikoleris@arm.com overwrite_mem = !std::memcmp(&condition_val32, blk_data, 73212724Snikos.nikoleris@arm.com sizeof(uint32_t)); 73312724Snikos.nikoleris@arm.com } else 73412724Snikos.nikoleris@arm.com panic("Invalid size for conditional read/write\n"); 73512724Snikos.nikoleris@arm.com } 73612724Snikos.nikoleris@arm.com 73712724Snikos.nikoleris@arm.com if (overwrite_mem) { 73812724Snikos.nikoleris@arm.com std::memcpy(blk_data, &overwrite_val, pkt->getSize()); 73912724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 74012724Snikos.nikoleris@arm.com } 74112724Snikos.nikoleris@arm.com} 74212724Snikos.nikoleris@arm.com 74312724Snikos.nikoleris@arm.comQueueEntry* 74412724Snikos.nikoleris@arm.comBaseCache::getNextQueueEntry() 74512724Snikos.nikoleris@arm.com{ 74612724Snikos.nikoleris@arm.com // Check both MSHR queue and write buffer for potential requests, 74712724Snikos.nikoleris@arm.com // note that null does not mean there is no request, it could 74812724Snikos.nikoleris@arm.com // simply be that it is not ready 74912724Snikos.nikoleris@arm.com MSHR *miss_mshr = mshrQueue.getNext(); 75012724Snikos.nikoleris@arm.com WriteQueueEntry *wq_entry = writeBuffer.getNext(); 75112724Snikos.nikoleris@arm.com 75212724Snikos.nikoleris@arm.com // If we got a write buffer request ready, first priority is a 75312724Snikos.nikoleris@arm.com // full write buffer, otherwise we favour the miss requests 75412724Snikos.nikoleris@arm.com if (wq_entry && (writeBuffer.isFull() || !miss_mshr)) { 75512724Snikos.nikoleris@arm.com // need to search MSHR queue for conflicting earlier miss. 75612724Snikos.nikoleris@arm.com MSHR *conflict_mshr = 75712724Snikos.nikoleris@arm.com mshrQueue.findPending(wq_entry->blkAddr, 75812724Snikos.nikoleris@arm.com wq_entry->isSecure); 75912724Snikos.nikoleris@arm.com 76012724Snikos.nikoleris@arm.com if (conflict_mshr && conflict_mshr->order < wq_entry->order) { 76112724Snikos.nikoleris@arm.com // Service misses in order until conflict is cleared. 76212724Snikos.nikoleris@arm.com return conflict_mshr; 76312724Snikos.nikoleris@arm.com 76412724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 76512724Snikos.nikoleris@arm.com } 76612724Snikos.nikoleris@arm.com 76712724Snikos.nikoleris@arm.com // No conflicts; issue write 76812724Snikos.nikoleris@arm.com return wq_entry; 76912724Snikos.nikoleris@arm.com } else if (miss_mshr) { 77012724Snikos.nikoleris@arm.com // need to check for conflicting earlier writeback 77112724Snikos.nikoleris@arm.com WriteQueueEntry *conflict_mshr = 77212724Snikos.nikoleris@arm.com writeBuffer.findPending(miss_mshr->blkAddr, 77312724Snikos.nikoleris@arm.com miss_mshr->isSecure); 77412724Snikos.nikoleris@arm.com if (conflict_mshr) { 77512724Snikos.nikoleris@arm.com // not sure why we don't check order here... it was in the 77612724Snikos.nikoleris@arm.com // original code but commented out. 77712724Snikos.nikoleris@arm.com 77812724Snikos.nikoleris@arm.com // The only way this happens is if we are 77912724Snikos.nikoleris@arm.com // doing a write and we didn't have permissions 78012724Snikos.nikoleris@arm.com // then subsequently saw a writeback (owned got evicted) 78112724Snikos.nikoleris@arm.com // We need to make sure to perform the writeback first 78212724Snikos.nikoleris@arm.com // To preserve the dirty data, then we can issue the write 78312724Snikos.nikoleris@arm.com 78412724Snikos.nikoleris@arm.com // should we return wq_entry here instead? I.e. do we 78512724Snikos.nikoleris@arm.com // have to flush writes in order? I don't think so... not 78612724Snikos.nikoleris@arm.com // for Alpha anyway. Maybe for x86? 78712724Snikos.nikoleris@arm.com return conflict_mshr; 78812724Snikos.nikoleris@arm.com 78912724Snikos.nikoleris@arm.com // @todo Note that we ignore the ready time of the conflict here 79012724Snikos.nikoleris@arm.com } 79112724Snikos.nikoleris@arm.com 79212724Snikos.nikoleris@arm.com // No conflicts; issue read 79312724Snikos.nikoleris@arm.com return miss_mshr; 79412724Snikos.nikoleris@arm.com } 79512724Snikos.nikoleris@arm.com 79612724Snikos.nikoleris@arm.com // fall through... no pending requests. Try a prefetch. 79712724Snikos.nikoleris@arm.com assert(!miss_mshr && !wq_entry); 79812724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 79912724Snikos.nikoleris@arm.com // If we have a miss queue slot, we can try a prefetch 80012724Snikos.nikoleris@arm.com PacketPtr pkt = prefetcher->getPacket(); 80112724Snikos.nikoleris@arm.com if (pkt) { 80212724Snikos.nikoleris@arm.com Addr pf_addr = pkt->getBlockAddr(blkSize); 80312724Snikos.nikoleris@arm.com if (!tags->findBlock(pf_addr, pkt->isSecure()) && 80412724Snikos.nikoleris@arm.com !mshrQueue.findMatch(pf_addr, pkt->isSecure()) && 80512724Snikos.nikoleris@arm.com !writeBuffer.findMatch(pf_addr, pkt->isSecure())) { 80612724Snikos.nikoleris@arm.com // Update statistic on number of prefetches issued 80712724Snikos.nikoleris@arm.com // (hwpf_mshr_misses) 80812724Snikos.nikoleris@arm.com assert(pkt->req->masterId() < system->maxMasters()); 80912724Snikos.nikoleris@arm.com mshr_misses[pkt->cmdToIndex()][pkt->req->masterId()]++; 81012724Snikos.nikoleris@arm.com 81112724Snikos.nikoleris@arm.com // allocate an MSHR and return it, note 81212724Snikos.nikoleris@arm.com // that we send the packet straight away, so do not 81312724Snikos.nikoleris@arm.com // schedule the send 81412724Snikos.nikoleris@arm.com return allocateMissBuffer(pkt, curTick(), false); 81512724Snikos.nikoleris@arm.com } else { 81612724Snikos.nikoleris@arm.com // free the request and packet 81712724Snikos.nikoleris@arm.com delete pkt; 81812724Snikos.nikoleris@arm.com } 81912724Snikos.nikoleris@arm.com } 82012724Snikos.nikoleris@arm.com } 82112724Snikos.nikoleris@arm.com 82212724Snikos.nikoleris@arm.com return nullptr; 82312724Snikos.nikoleris@arm.com} 82412724Snikos.nikoleris@arm.com 82512724Snikos.nikoleris@arm.comvoid 82612724Snikos.nikoleris@arm.comBaseCache::satisfyRequest(PacketPtr pkt, CacheBlk *blk, bool, bool) 82712724Snikos.nikoleris@arm.com{ 82812724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 82912724Snikos.nikoleris@arm.com 83012724Snikos.nikoleris@arm.com assert(blk && blk->isValid()); 83112724Snikos.nikoleris@arm.com // Occasionally this is not true... if we are a lower-level cache 83212724Snikos.nikoleris@arm.com // satisfying a string of Read and ReadEx requests from 83312724Snikos.nikoleris@arm.com // upper-level caches, a Read will mark the block as shared but we 83412724Snikos.nikoleris@arm.com // can satisfy a following ReadEx anyway since we can rely on the 83512724Snikos.nikoleris@arm.com // Read requester(s) to have buffered the ReadEx snoop and to 83612724Snikos.nikoleris@arm.com // invalidate their blocks after receiving them. 83712724Snikos.nikoleris@arm.com // assert(!pkt->needsWritable() || blk->isWritable()); 83812724Snikos.nikoleris@arm.com assert(pkt->getOffset(blkSize) + pkt->getSize() <= blkSize); 83912724Snikos.nikoleris@arm.com 84012724Snikos.nikoleris@arm.com // Check RMW operations first since both isRead() and 84112724Snikos.nikoleris@arm.com // isWrite() will be true for them 84212724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::SwapReq) { 84312766Sqtt2@cornell.edu if (pkt->isAtomicOp()) { 84412766Sqtt2@cornell.edu // extract data from cache and save it into the data field in 84512766Sqtt2@cornell.edu // the packet as a return value from this atomic op 84612766Sqtt2@cornell.edu 84712766Sqtt2@cornell.edu int offset = tags->extractBlkOffset(pkt->getAddr()); 84812766Sqtt2@cornell.edu uint8_t *blk_data = blk->data + offset; 84912766Sqtt2@cornell.edu std::memcpy(pkt->getPtr<uint8_t>(), blk_data, pkt->getSize()); 85012766Sqtt2@cornell.edu 85112766Sqtt2@cornell.edu // execute AMO operation 85212766Sqtt2@cornell.edu (*(pkt->getAtomicOp()))(blk_data); 85312766Sqtt2@cornell.edu 85412766Sqtt2@cornell.edu // set block status to dirty 85512766Sqtt2@cornell.edu blk->status |= BlkDirty; 85612766Sqtt2@cornell.edu } else { 85712766Sqtt2@cornell.edu cmpAndSwap(blk, pkt); 85812766Sqtt2@cornell.edu } 85912724Snikos.nikoleris@arm.com } else if (pkt->isWrite()) { 86012724Snikos.nikoleris@arm.com // we have the block in a writable state and can go ahead, 86112724Snikos.nikoleris@arm.com // note that the line may be also be considered writable in 86212724Snikos.nikoleris@arm.com // downstream caches along the path to memory, but always 86312724Snikos.nikoleris@arm.com // Exclusive, and never Modified 86412724Snikos.nikoleris@arm.com assert(blk->isWritable()); 86512724Snikos.nikoleris@arm.com // Write or WriteLine at the first cache with block in writable state 86612724Snikos.nikoleris@arm.com if (blk->checkWrite(pkt)) { 86712724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 86812724Snikos.nikoleris@arm.com } 86912724Snikos.nikoleris@arm.com // Always mark the line as dirty (and thus transition to the 87012724Snikos.nikoleris@arm.com // Modified state) even if we are a failed StoreCond so we 87112724Snikos.nikoleris@arm.com // supply data to any snoops that have appended themselves to 87212724Snikos.nikoleris@arm.com // this cache before knowing the store will fail. 87312724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 87412724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (write)\n", __func__, pkt->print()); 87512724Snikos.nikoleris@arm.com } else if (pkt->isRead()) { 87612724Snikos.nikoleris@arm.com if (pkt->isLLSC()) { 87712724Snikos.nikoleris@arm.com blk->trackLoadLocked(pkt); 87812724Snikos.nikoleris@arm.com } 87912724Snikos.nikoleris@arm.com 88012724Snikos.nikoleris@arm.com // all read responses have a data payload 88112724Snikos.nikoleris@arm.com assert(pkt->hasRespData()); 88212724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 88312724Snikos.nikoleris@arm.com } else if (pkt->isUpgrade()) { 88412724Snikos.nikoleris@arm.com // sanity check 88512724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 88612724Snikos.nikoleris@arm.com 88712724Snikos.nikoleris@arm.com if (blk->isDirty()) { 88812724Snikos.nikoleris@arm.com // we were in the Owned state, and a cache above us that 88912724Snikos.nikoleris@arm.com // has the line in Shared state needs to be made aware 89012724Snikos.nikoleris@arm.com // that the data it already has is in fact dirty 89112724Snikos.nikoleris@arm.com pkt->setCacheResponding(); 89212724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 89312724Snikos.nikoleris@arm.com } 89412794Snikos.nikoleris@arm.com } else if (pkt->isClean()) { 89512794Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 89612724Snikos.nikoleris@arm.com } else { 89712724Snikos.nikoleris@arm.com assert(pkt->isInvalidate()); 89812724Snikos.nikoleris@arm.com invalidateBlock(blk); 89912724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s for %s (invalidation)\n", __func__, 90012724Snikos.nikoleris@arm.com pkt->print()); 90112724Snikos.nikoleris@arm.com } 90212724Snikos.nikoleris@arm.com} 90312724Snikos.nikoleris@arm.com 90412724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 90512724Snikos.nikoleris@arm.com// 90612724Snikos.nikoleris@arm.com// Access path: requests coming in from the CPU side 90712724Snikos.nikoleris@arm.com// 90812724Snikos.nikoleris@arm.com///////////////////////////////////////////////////// 90912724Snikos.nikoleris@arm.com 91012724Snikos.nikoleris@arm.combool 91112724Snikos.nikoleris@arm.comBaseCache::access(PacketPtr pkt, CacheBlk *&blk, Cycles &lat, 91212724Snikos.nikoleris@arm.com PacketList &writebacks) 91312724Snikos.nikoleris@arm.com{ 91412724Snikos.nikoleris@arm.com // sanity check 91512724Snikos.nikoleris@arm.com assert(pkt->isRequest()); 91612724Snikos.nikoleris@arm.com 91712724Snikos.nikoleris@arm.com chatty_assert(!(isReadOnly && pkt->isWrite()), 91812724Snikos.nikoleris@arm.com "Should never see a write in a read-only cache %s\n", 91912724Snikos.nikoleris@arm.com name()); 92012724Snikos.nikoleris@arm.com 92112724Snikos.nikoleris@arm.com // Here lat is the value passed as parameter to accessBlock() function 92212724Snikos.nikoleris@arm.com // that can modify its value. 92312724Snikos.nikoleris@arm.com blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat); 92412724Snikos.nikoleris@arm.com 92512724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s for %s %s\n", __func__, pkt->print(), 92612724Snikos.nikoleris@arm.com blk ? "hit " + blk->print() : "miss"); 92712724Snikos.nikoleris@arm.com 92812724Snikos.nikoleris@arm.com if (pkt->req->isCacheMaintenance()) { 92912724Snikos.nikoleris@arm.com // A cache maintenance operation is always forwarded to the 93012724Snikos.nikoleris@arm.com // memory below even if the block is found in dirty state. 93112724Snikos.nikoleris@arm.com 93212724Snikos.nikoleris@arm.com // We defer any changes to the state of the block until we 93312724Snikos.nikoleris@arm.com // create and mark as in service the mshr for the downstream 93412724Snikos.nikoleris@arm.com // packet. 93512724Snikos.nikoleris@arm.com return false; 93612724Snikos.nikoleris@arm.com } 93712724Snikos.nikoleris@arm.com 93812724Snikos.nikoleris@arm.com if (pkt->isEviction()) { 93912724Snikos.nikoleris@arm.com // We check for presence of block in above caches before issuing 94012724Snikos.nikoleris@arm.com // Writeback or CleanEvict to write buffer. Therefore the only 94112724Snikos.nikoleris@arm.com // possible cases can be of a CleanEvict packet coming from above 94212724Snikos.nikoleris@arm.com // encountering a Writeback generated in this cache peer cache and 94312724Snikos.nikoleris@arm.com // waiting in the write buffer. Cases of upper level peer caches 94412724Snikos.nikoleris@arm.com // generating CleanEvict and Writeback or simply CleanEvict and 94512724Snikos.nikoleris@arm.com // CleanEvict almost simultaneously will be caught by snoops sent out 94612724Snikos.nikoleris@arm.com // by crossbar. 94712724Snikos.nikoleris@arm.com WriteQueueEntry *wb_entry = writeBuffer.findMatch(pkt->getAddr(), 94812724Snikos.nikoleris@arm.com pkt->isSecure()); 94912724Snikos.nikoleris@arm.com if (wb_entry) { 95012724Snikos.nikoleris@arm.com assert(wb_entry->getNumTargets() == 1); 95112724Snikos.nikoleris@arm.com PacketPtr wbPkt = wb_entry->getTarget()->pkt; 95212724Snikos.nikoleris@arm.com assert(wbPkt->isWriteback()); 95312724Snikos.nikoleris@arm.com 95412724Snikos.nikoleris@arm.com if (pkt->isCleanEviction()) { 95512724Snikos.nikoleris@arm.com // The CleanEvict and WritebackClean snoops into other 95612724Snikos.nikoleris@arm.com // peer caches of the same level while traversing the 95712724Snikos.nikoleris@arm.com // crossbar. If a copy of the block is found, the 95812724Snikos.nikoleris@arm.com // packet is deleted in the crossbar. Hence, none of 95912724Snikos.nikoleris@arm.com // the other upper level caches connected to this 96012724Snikos.nikoleris@arm.com // cache have the block, so we can clear the 96112724Snikos.nikoleris@arm.com // BLOCK_CACHED flag in the Writeback if set and 96212724Snikos.nikoleris@arm.com // discard the CleanEvict by returning true. 96312724Snikos.nikoleris@arm.com wbPkt->clearBlockCached(); 96412724Snikos.nikoleris@arm.com return true; 96512724Snikos.nikoleris@arm.com } else { 96612724Snikos.nikoleris@arm.com assert(pkt->cmd == MemCmd::WritebackDirty); 96712724Snikos.nikoleris@arm.com // Dirty writeback from above trumps our clean 96812724Snikos.nikoleris@arm.com // writeback... discard here 96912724Snikos.nikoleris@arm.com // Note: markInService will remove entry from writeback buffer. 97012724Snikos.nikoleris@arm.com markInService(wb_entry); 97112724Snikos.nikoleris@arm.com delete wbPkt; 97212724Snikos.nikoleris@arm.com } 97312724Snikos.nikoleris@arm.com } 97412724Snikos.nikoleris@arm.com } 97512724Snikos.nikoleris@arm.com 97612724Snikos.nikoleris@arm.com // Writeback handling is special case. We can write the block into 97712724Snikos.nikoleris@arm.com // the cache without having a writeable copy (or any copy at all). 97812724Snikos.nikoleris@arm.com if (pkt->isWriteback()) { 97912724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 98012724Snikos.nikoleris@arm.com 98112724Snikos.nikoleris@arm.com // we could get a clean writeback while we are having 98212724Snikos.nikoleris@arm.com // outstanding accesses to a block, do the simple thing for 98312724Snikos.nikoleris@arm.com // now and drop the clean writeback so that we do not upset 98412724Snikos.nikoleris@arm.com // any ordering/decisions about ownership already taken 98512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackClean && 98612724Snikos.nikoleris@arm.com mshrQueue.findMatch(pkt->getAddr(), pkt->isSecure())) { 98712724Snikos.nikoleris@arm.com DPRINTF(Cache, "Clean writeback %#llx to block with MSHR, " 98812724Snikos.nikoleris@arm.com "dropping\n", pkt->getAddr()); 98912724Snikos.nikoleris@arm.com return true; 99012724Snikos.nikoleris@arm.com } 99112724Snikos.nikoleris@arm.com 99212724Snikos.nikoleris@arm.com if (!blk) { 99312724Snikos.nikoleris@arm.com // need to do a replacement 99412754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 99512724Snikos.nikoleris@arm.com if (!blk) { 99612724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to next level. 99712724Snikos.nikoleris@arm.com incMissCount(pkt); 99812724Snikos.nikoleris@arm.com return false; 99912724Snikos.nikoleris@arm.com } 100012724Snikos.nikoleris@arm.com 100112724Snikos.nikoleris@arm.com blk->status |= (BlkValid | BlkReadable); 100212724Snikos.nikoleris@arm.com } 100312724Snikos.nikoleris@arm.com // only mark the block dirty if we got a writeback command, 100412724Snikos.nikoleris@arm.com // and leave it as is for a clean writeback 100512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WritebackDirty) { 100612724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 100712724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 100812724Snikos.nikoleris@arm.com } 100912724Snikos.nikoleris@arm.com // if the packet does not have sharers, it is passing 101012724Snikos.nikoleris@arm.com // writable, and we got the writeback in Modified or Exclusive 101112724Snikos.nikoleris@arm.com // state, if not we are in the Owned or Shared state 101212724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 101312724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 101412724Snikos.nikoleris@arm.com } 101512724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 101612724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 101712724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 101812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 101912724Snikos.nikoleris@arm.com incHitCount(pkt); 102012724Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 102112724Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 102212724Snikos.nikoleris@arm.com pkt->payloadDelay; 102312724Snikos.nikoleris@arm.com return true; 102412724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::CleanEvict) { 102512724Snikos.nikoleris@arm.com if (blk) { 102612724Snikos.nikoleris@arm.com // Found the block in the tags, need to stop CleanEvict from 102712724Snikos.nikoleris@arm.com // propagating further down the hierarchy. Returning true will 102812724Snikos.nikoleris@arm.com // treat the CleanEvict like a satisfied write request and delete 102912724Snikos.nikoleris@arm.com // it. 103012724Snikos.nikoleris@arm.com return true; 103112724Snikos.nikoleris@arm.com } 103212724Snikos.nikoleris@arm.com // We didn't find the block here, propagate the CleanEvict further 103312724Snikos.nikoleris@arm.com // down the memory hierarchy. Returning false will treat the CleanEvict 103412724Snikos.nikoleris@arm.com // like a Writeback which could not find a replaceable block so has to 103512724Snikos.nikoleris@arm.com // go to next level. 103612724Snikos.nikoleris@arm.com return false; 103712724Snikos.nikoleris@arm.com } else if (pkt->cmd == MemCmd::WriteClean) { 103812724Snikos.nikoleris@arm.com // WriteClean handling is a special case. We can allocate a 103912724Snikos.nikoleris@arm.com // block directly if it doesn't exist and we can update the 104012724Snikos.nikoleris@arm.com // block immediately. The WriteClean transfers the ownership 104112724Snikos.nikoleris@arm.com // of the block as well. 104212724Snikos.nikoleris@arm.com assert(blkSize == pkt->getSize()); 104312724Snikos.nikoleris@arm.com 104412724Snikos.nikoleris@arm.com if (!blk) { 104512724Snikos.nikoleris@arm.com if (pkt->writeThrough()) { 104612724Snikos.nikoleris@arm.com // if this is a write through packet, we don't try to 104712724Snikos.nikoleris@arm.com // allocate if the block is not present 104812724Snikos.nikoleris@arm.com return false; 104912724Snikos.nikoleris@arm.com } else { 105012724Snikos.nikoleris@arm.com // a writeback that misses needs to allocate a new block 105112754Sodanrc@yahoo.com.br blk = allocateBlock(pkt, writebacks); 105212724Snikos.nikoleris@arm.com if (!blk) { 105312724Snikos.nikoleris@arm.com // no replaceable block available: give up, fwd to 105412724Snikos.nikoleris@arm.com // next level. 105512724Snikos.nikoleris@arm.com incMissCount(pkt); 105612724Snikos.nikoleris@arm.com return false; 105712724Snikos.nikoleris@arm.com } 105812724Snikos.nikoleris@arm.com 105912724Snikos.nikoleris@arm.com blk->status |= (BlkValid | BlkReadable); 106012724Snikos.nikoleris@arm.com } 106112724Snikos.nikoleris@arm.com } 106212724Snikos.nikoleris@arm.com 106312724Snikos.nikoleris@arm.com // at this point either this is a writeback or a write-through 106412724Snikos.nikoleris@arm.com // write clean operation and the block is already in this 106512724Snikos.nikoleris@arm.com // cache, we need to update the data and the block flags 106612724Snikos.nikoleris@arm.com assert(blk); 106712724Snikos.nikoleris@arm.com // TODO: the coherent cache can assert(!blk->isDirty()); 106812724Snikos.nikoleris@arm.com if (!pkt->writeThrough()) { 106912724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 107012724Snikos.nikoleris@arm.com } 107112724Snikos.nikoleris@arm.com // nothing else to do; writeback doesn't expect response 107212724Snikos.nikoleris@arm.com assert(!pkt->needsResponse()); 107312724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 107412724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s new state is %s\n", __func__, blk->print()); 107512724Snikos.nikoleris@arm.com 107612724Snikos.nikoleris@arm.com incHitCount(pkt); 107712724Snikos.nikoleris@arm.com // populate the time when the block will be ready to access. 107812724Snikos.nikoleris@arm.com blk->whenReady = clockEdge(fillLatency) + pkt->headerDelay + 107912724Snikos.nikoleris@arm.com pkt->payloadDelay; 108012724Snikos.nikoleris@arm.com // if this a write-through packet it will be sent to cache 108112724Snikos.nikoleris@arm.com // below 108212724Snikos.nikoleris@arm.com return !pkt->writeThrough(); 108312724Snikos.nikoleris@arm.com } else if (blk && (pkt->needsWritable() ? blk->isWritable() : 108412724Snikos.nikoleris@arm.com blk->isReadable())) { 108512724Snikos.nikoleris@arm.com // OK to satisfy access 108612724Snikos.nikoleris@arm.com incHitCount(pkt); 108712724Snikos.nikoleris@arm.com satisfyRequest(pkt, blk); 108812724Snikos.nikoleris@arm.com maintainClusivity(pkt->fromCache(), blk); 108912724Snikos.nikoleris@arm.com 109012724Snikos.nikoleris@arm.com return true; 109112724Snikos.nikoleris@arm.com } 109212724Snikos.nikoleris@arm.com 109312724Snikos.nikoleris@arm.com // Can't satisfy access normally... either no block (blk == nullptr) 109412724Snikos.nikoleris@arm.com // or have block but need writable 109512724Snikos.nikoleris@arm.com 109612724Snikos.nikoleris@arm.com incMissCount(pkt); 109712724Snikos.nikoleris@arm.com 109812724Snikos.nikoleris@arm.com if (!blk && pkt->isLLSC() && pkt->isWrite()) { 109912724Snikos.nikoleris@arm.com // complete miss on store conditional... just give up now 110012724Snikos.nikoleris@arm.com pkt->req->setExtraData(0); 110112724Snikos.nikoleris@arm.com return true; 110212724Snikos.nikoleris@arm.com } 110312724Snikos.nikoleris@arm.com 110412724Snikos.nikoleris@arm.com return false; 110512724Snikos.nikoleris@arm.com} 110612724Snikos.nikoleris@arm.com 110712724Snikos.nikoleris@arm.comvoid 110812724Snikos.nikoleris@arm.comBaseCache::maintainClusivity(bool from_cache, CacheBlk *blk) 110912724Snikos.nikoleris@arm.com{ 111012724Snikos.nikoleris@arm.com if (from_cache && blk && blk->isValid() && !blk->isDirty() && 111112724Snikos.nikoleris@arm.com clusivity == Enums::mostly_excl) { 111212724Snikos.nikoleris@arm.com // if we have responded to a cache, and our block is still 111312724Snikos.nikoleris@arm.com // valid, but not dirty, and this cache is mostly exclusive 111412724Snikos.nikoleris@arm.com // with respect to the cache above, drop the block 111512724Snikos.nikoleris@arm.com invalidateBlock(blk); 111612724Snikos.nikoleris@arm.com } 111712724Snikos.nikoleris@arm.com} 111812724Snikos.nikoleris@arm.com 111912724Snikos.nikoleris@arm.comCacheBlk* 112012724Snikos.nikoleris@arm.comBaseCache::handleFill(PacketPtr pkt, CacheBlk *blk, PacketList &writebacks, 112112724Snikos.nikoleris@arm.com bool allocate) 112212724Snikos.nikoleris@arm.com{ 112312724Snikos.nikoleris@arm.com assert(pkt->isResponse() || pkt->cmd == MemCmd::WriteLineReq); 112412724Snikos.nikoleris@arm.com Addr addr = pkt->getAddr(); 112512724Snikos.nikoleris@arm.com bool is_secure = pkt->isSecure(); 112612724Snikos.nikoleris@arm.com#if TRACING_ON 112712724Snikos.nikoleris@arm.com CacheBlk::State old_state = blk ? blk->status : 0; 112812724Snikos.nikoleris@arm.com#endif 112912724Snikos.nikoleris@arm.com 113012724Snikos.nikoleris@arm.com // When handling a fill, we should have no writes to this line. 113112724Snikos.nikoleris@arm.com assert(addr == pkt->getBlockAddr(blkSize)); 113212724Snikos.nikoleris@arm.com assert(!writeBuffer.findMatch(addr, is_secure)); 113312724Snikos.nikoleris@arm.com 113412724Snikos.nikoleris@arm.com if (!blk) { 113512724Snikos.nikoleris@arm.com // better have read new data... 113612724Snikos.nikoleris@arm.com assert(pkt->hasData()); 113712724Snikos.nikoleris@arm.com 113812724Snikos.nikoleris@arm.com // only read responses and write-line requests have data; 113912724Snikos.nikoleris@arm.com // note that we don't write the data here for write-line - that 114012724Snikos.nikoleris@arm.com // happens in the subsequent call to satisfyRequest 114112724Snikos.nikoleris@arm.com assert(pkt->isRead() || pkt->cmd == MemCmd::WriteLineReq); 114212724Snikos.nikoleris@arm.com 114312724Snikos.nikoleris@arm.com // need to do a replacement if allocating, otherwise we stick 114412724Snikos.nikoleris@arm.com // with the temporary storage 114512754Sodanrc@yahoo.com.br blk = allocate ? allocateBlock(pkt, writebacks) : nullptr; 114612724Snikos.nikoleris@arm.com 114712724Snikos.nikoleris@arm.com if (!blk) { 114812724Snikos.nikoleris@arm.com // No replaceable block or a mostly exclusive 114912724Snikos.nikoleris@arm.com // cache... just use temporary storage to complete the 115012724Snikos.nikoleris@arm.com // current request and then get rid of it 115112724Snikos.nikoleris@arm.com assert(!tempBlock->isValid()); 115212724Snikos.nikoleris@arm.com blk = tempBlock; 115312730Sodanrc@yahoo.com.br tempBlock->insert(addr, is_secure); 115412724Snikos.nikoleris@arm.com DPRINTF(Cache, "using temp block for %#llx (%s)\n", addr, 115512724Snikos.nikoleris@arm.com is_secure ? "s" : "ns"); 115612724Snikos.nikoleris@arm.com } 115712724Snikos.nikoleris@arm.com 115812724Snikos.nikoleris@arm.com // we should never be overwriting a valid block 115912724Snikos.nikoleris@arm.com assert(!blk->isValid()); 116012724Snikos.nikoleris@arm.com } else { 116112724Snikos.nikoleris@arm.com // existing block... probably an upgrade 116212747Sodanrc@yahoo.com.br assert(regenerateBlkAddr(blk) == addr); 116312729Sodanrc@yahoo.com.br assert(blk->isSecure() == is_secure); 116412724Snikos.nikoleris@arm.com // either we're getting new data or the block should already be valid 116512724Snikos.nikoleris@arm.com assert(pkt->hasData() || blk->isValid()); 116612724Snikos.nikoleris@arm.com // don't clear block status... if block is already dirty we 116712724Snikos.nikoleris@arm.com // don't want to lose that 116812724Snikos.nikoleris@arm.com } 116912724Snikos.nikoleris@arm.com 117012724Snikos.nikoleris@arm.com blk->status |= BlkValid | BlkReadable; 117112724Snikos.nikoleris@arm.com 117212724Snikos.nikoleris@arm.com // sanity check for whole-line writes, which should always be 117312724Snikos.nikoleris@arm.com // marked as writable as part of the fill, and then later marked 117412724Snikos.nikoleris@arm.com // dirty as part of satisfyRequest 117512724Snikos.nikoleris@arm.com if (pkt->cmd == MemCmd::WriteLineReq) { 117612724Snikos.nikoleris@arm.com assert(!pkt->hasSharers()); 117712724Snikos.nikoleris@arm.com } 117812724Snikos.nikoleris@arm.com 117912724Snikos.nikoleris@arm.com // here we deal with setting the appropriate state of the line, 118012724Snikos.nikoleris@arm.com // and we start by looking at the hasSharers flag, and ignore the 118112724Snikos.nikoleris@arm.com // cacheResponding flag (normally signalling dirty data) if the 118212724Snikos.nikoleris@arm.com // packet has sharers, thus the line is never allocated as Owned 118312724Snikos.nikoleris@arm.com // (dirty but not writable), and always ends up being either 118412724Snikos.nikoleris@arm.com // Shared, Exclusive or Modified, see Packet::setCacheResponding 118512724Snikos.nikoleris@arm.com // for more details 118612724Snikos.nikoleris@arm.com if (!pkt->hasSharers()) { 118712724Snikos.nikoleris@arm.com // we could get a writable line from memory (rather than a 118812724Snikos.nikoleris@arm.com // cache) even in a read-only cache, note that we set this bit 118912724Snikos.nikoleris@arm.com // even for a read-only cache, possibly revisit this decision 119012724Snikos.nikoleris@arm.com blk->status |= BlkWritable; 119112724Snikos.nikoleris@arm.com 119212724Snikos.nikoleris@arm.com // check if we got this via cache-to-cache transfer (i.e., from a 119312724Snikos.nikoleris@arm.com // cache that had the block in Modified or Owned state) 119412724Snikos.nikoleris@arm.com if (pkt->cacheResponding()) { 119512724Snikos.nikoleris@arm.com // we got the block in Modified state, and invalidated the 119612724Snikos.nikoleris@arm.com // owners copy 119712724Snikos.nikoleris@arm.com blk->status |= BlkDirty; 119812724Snikos.nikoleris@arm.com 119912724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly, "Should never see dirty snoop response " 120012724Snikos.nikoleris@arm.com "in read-only cache %s\n", name()); 120112724Snikos.nikoleris@arm.com } 120212724Snikos.nikoleris@arm.com } 120312724Snikos.nikoleris@arm.com 120412724Snikos.nikoleris@arm.com DPRINTF(Cache, "Block addr %#llx (%s) moving from state %x to %s\n", 120512724Snikos.nikoleris@arm.com addr, is_secure ? "s" : "ns", old_state, blk->print()); 120612724Snikos.nikoleris@arm.com 120712724Snikos.nikoleris@arm.com // if we got new data, copy it in (checking for a read response 120812724Snikos.nikoleris@arm.com // and a response that has data is the same in the end) 120912724Snikos.nikoleris@arm.com if (pkt->isRead()) { 121012724Snikos.nikoleris@arm.com // sanity checks 121112724Snikos.nikoleris@arm.com assert(pkt->hasData()); 121212724Snikos.nikoleris@arm.com assert(pkt->getSize() == blkSize); 121312724Snikos.nikoleris@arm.com 121412724Snikos.nikoleris@arm.com pkt->writeDataToBlock(blk->data, blkSize); 121512724Snikos.nikoleris@arm.com } 121612724Snikos.nikoleris@arm.com // We pay for fillLatency here. 121712724Snikos.nikoleris@arm.com blk->whenReady = clockEdge() + fillLatency * clockPeriod() + 121812724Snikos.nikoleris@arm.com pkt->payloadDelay; 121912724Snikos.nikoleris@arm.com 122012724Snikos.nikoleris@arm.com return blk; 122112724Snikos.nikoleris@arm.com} 122212724Snikos.nikoleris@arm.com 122312724Snikos.nikoleris@arm.comCacheBlk* 122412754Sodanrc@yahoo.com.brBaseCache::allocateBlock(const PacketPtr pkt, PacketList &writebacks) 122512724Snikos.nikoleris@arm.com{ 122612754Sodanrc@yahoo.com.br // Get address 122712754Sodanrc@yahoo.com.br const Addr addr = pkt->getAddr(); 122812754Sodanrc@yahoo.com.br 122912754Sodanrc@yahoo.com.br // Get secure bit 123012754Sodanrc@yahoo.com.br const bool is_secure = pkt->isSecure(); 123112754Sodanrc@yahoo.com.br 123212724Snikos.nikoleris@arm.com // Find replacement victim 123312744Sodanrc@yahoo.com.br std::vector<CacheBlk*> evict_blks; 123412746Sodanrc@yahoo.com.br CacheBlk *victim = tags->findVictim(addr, is_secure, evict_blks); 123512724Snikos.nikoleris@arm.com 123612724Snikos.nikoleris@arm.com // It is valid to return nullptr if there is no victim 123712744Sodanrc@yahoo.com.br if (!victim) 123812724Snikos.nikoleris@arm.com return nullptr; 123912724Snikos.nikoleris@arm.com 124012744Sodanrc@yahoo.com.br // Check for transient state allocations. If any of the entries listed 124112744Sodanrc@yahoo.com.br // for eviction has a transient state, the allocation fails 124212744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 124312744Sodanrc@yahoo.com.br if (blk->isValid()) { 124412744Sodanrc@yahoo.com.br Addr repl_addr = regenerateBlkAddr(blk); 124512744Sodanrc@yahoo.com.br MSHR *repl_mshr = mshrQueue.findMatch(repl_addr, blk->isSecure()); 124612744Sodanrc@yahoo.com.br if (repl_mshr) { 124712744Sodanrc@yahoo.com.br // must be an outstanding upgrade or clean request 124812744Sodanrc@yahoo.com.br // on a block we're about to replace... 124912744Sodanrc@yahoo.com.br assert((!blk->isWritable() && repl_mshr->needsWritable()) || 125012744Sodanrc@yahoo.com.br repl_mshr->isCleaning()); 125112724Snikos.nikoleris@arm.com 125212744Sodanrc@yahoo.com.br // too hard to replace block with transient state 125312744Sodanrc@yahoo.com.br // allocation failed, block not inserted 125412744Sodanrc@yahoo.com.br return nullptr; 125512744Sodanrc@yahoo.com.br } 125612744Sodanrc@yahoo.com.br } 125712744Sodanrc@yahoo.com.br } 125812744Sodanrc@yahoo.com.br 125912744Sodanrc@yahoo.com.br // The victim will be replaced by a new entry, so increase the replacement 126012744Sodanrc@yahoo.com.br // counter if a valid block is being replaced 126112744Sodanrc@yahoo.com.br if (victim->isValid()) { 126212744Sodanrc@yahoo.com.br DPRINTF(Cache, "replacement: replacing %#llx (%s) with %#llx " 126312744Sodanrc@yahoo.com.br "(%s): %s\n", regenerateBlkAddr(victim), 126412744Sodanrc@yahoo.com.br victim->isSecure() ? "s" : "ns", 126512744Sodanrc@yahoo.com.br addr, is_secure ? "s" : "ns", 126612744Sodanrc@yahoo.com.br victim->isDirty() ? "writeback" : "clean"); 126712744Sodanrc@yahoo.com.br 126812744Sodanrc@yahoo.com.br replacements++; 126912744Sodanrc@yahoo.com.br } 127012744Sodanrc@yahoo.com.br 127112744Sodanrc@yahoo.com.br // Evict valid blocks associated to this victim block 127212744Sodanrc@yahoo.com.br for (const auto& blk : evict_blks) { 127312744Sodanrc@yahoo.com.br if (blk->isValid()) { 127412724Snikos.nikoleris@arm.com if (blk->wasPrefetched()) { 127512724Snikos.nikoleris@arm.com unusedPrefetches++; 127612724Snikos.nikoleris@arm.com } 127712744Sodanrc@yahoo.com.br 127812724Snikos.nikoleris@arm.com evictBlock(blk, writebacks); 127912724Snikos.nikoleris@arm.com } 128012724Snikos.nikoleris@arm.com } 128112724Snikos.nikoleris@arm.com 128212754Sodanrc@yahoo.com.br // Insert new block at victimized entry 128313215Sodanrc@yahoo.com.br tags->insertBlock(addr, is_secure, pkt->req->masterId(), 128413215Sodanrc@yahoo.com.br pkt->req->taskId(), victim); 128512754Sodanrc@yahoo.com.br 128612744Sodanrc@yahoo.com.br return victim; 128712724Snikos.nikoleris@arm.com} 128812724Snikos.nikoleris@arm.com 128912724Snikos.nikoleris@arm.comvoid 129012724Snikos.nikoleris@arm.comBaseCache::invalidateBlock(CacheBlk *blk) 129112724Snikos.nikoleris@arm.com{ 129212724Snikos.nikoleris@arm.com if (blk != tempBlock) 129312724Snikos.nikoleris@arm.com tags->invalidate(blk); 129412724Snikos.nikoleris@arm.com blk->invalidate(); 129512724Snikos.nikoleris@arm.com} 129612724Snikos.nikoleris@arm.com 129712724Snikos.nikoleris@arm.comPacketPtr 129812724Snikos.nikoleris@arm.comBaseCache::writebackBlk(CacheBlk *blk) 129912724Snikos.nikoleris@arm.com{ 130012724Snikos.nikoleris@arm.com chatty_assert(!isReadOnly || writebackClean, 130112724Snikos.nikoleris@arm.com "Writeback from read-only cache"); 130212724Snikos.nikoleris@arm.com assert(blk && blk->isValid() && (blk->isDirty() || writebackClean)); 130312724Snikos.nikoleris@arm.com 130412724Snikos.nikoleris@arm.com writebacks[Request::wbMasterId]++; 130512724Snikos.nikoleris@arm.com 130612749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 130712749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 130812749Sgiacomo.travaglini@arm.com 130912724Snikos.nikoleris@arm.com if (blk->isSecure()) 131012724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 131112724Snikos.nikoleris@arm.com 131212724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 131312724Snikos.nikoleris@arm.com 131412724Snikos.nikoleris@arm.com PacketPtr pkt = 131512724Snikos.nikoleris@arm.com new Packet(req, blk->isDirty() ? 131612724Snikos.nikoleris@arm.com MemCmd::WritebackDirty : MemCmd::WritebackClean); 131712724Snikos.nikoleris@arm.com 131812724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create Writeback %s writable: %d, dirty: %d\n", 131912724Snikos.nikoleris@arm.com pkt->print(), blk->isWritable(), blk->isDirty()); 132012724Snikos.nikoleris@arm.com 132112724Snikos.nikoleris@arm.com if (blk->isWritable()) { 132212724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 132312724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 132412724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 132512724Snikos.nikoleris@arm.com } else { 132612724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 132712724Snikos.nikoleris@arm.com pkt->setHasSharers(); 132812724Snikos.nikoleris@arm.com } 132912724Snikos.nikoleris@arm.com 133012724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 133112724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 133212724Snikos.nikoleris@arm.com 133312724Snikos.nikoleris@arm.com pkt->allocate(); 133412724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 133512724Snikos.nikoleris@arm.com 133612724Snikos.nikoleris@arm.com return pkt; 133712724Snikos.nikoleris@arm.com} 133812724Snikos.nikoleris@arm.com 133912724Snikos.nikoleris@arm.comPacketPtr 134012724Snikos.nikoleris@arm.comBaseCache::writecleanBlk(CacheBlk *blk, Request::Flags dest, PacketId id) 134112724Snikos.nikoleris@arm.com{ 134212749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>( 134312749Sgiacomo.travaglini@arm.com regenerateBlkAddr(blk), blkSize, 0, Request::wbMasterId); 134412749Sgiacomo.travaglini@arm.com 134512724Snikos.nikoleris@arm.com if (blk->isSecure()) { 134612724Snikos.nikoleris@arm.com req->setFlags(Request::SECURE); 134712724Snikos.nikoleris@arm.com } 134812724Snikos.nikoleris@arm.com req->taskId(blk->task_id); 134912724Snikos.nikoleris@arm.com 135012724Snikos.nikoleris@arm.com PacketPtr pkt = new Packet(req, MemCmd::WriteClean, blkSize, id); 135112724Snikos.nikoleris@arm.com 135212724Snikos.nikoleris@arm.com if (dest) { 135312724Snikos.nikoleris@arm.com req->setFlags(dest); 135412724Snikos.nikoleris@arm.com pkt->setWriteThrough(); 135512724Snikos.nikoleris@arm.com } 135612724Snikos.nikoleris@arm.com 135712724Snikos.nikoleris@arm.com DPRINTF(Cache, "Create %s writable: %d, dirty: %d\n", pkt->print(), 135812724Snikos.nikoleris@arm.com blk->isWritable(), blk->isDirty()); 135912724Snikos.nikoleris@arm.com 136012724Snikos.nikoleris@arm.com if (blk->isWritable()) { 136112724Snikos.nikoleris@arm.com // not asserting shared means we pass the block in modified 136212724Snikos.nikoleris@arm.com // state, mark our own block non-writeable 136312724Snikos.nikoleris@arm.com blk->status &= ~BlkWritable; 136412724Snikos.nikoleris@arm.com } else { 136512724Snikos.nikoleris@arm.com // we are in the Owned state, tell the receiver 136612724Snikos.nikoleris@arm.com pkt->setHasSharers(); 136712724Snikos.nikoleris@arm.com } 136812724Snikos.nikoleris@arm.com 136912724Snikos.nikoleris@arm.com // make sure the block is not marked dirty 137012724Snikos.nikoleris@arm.com blk->status &= ~BlkDirty; 137112724Snikos.nikoleris@arm.com 137212724Snikos.nikoleris@arm.com pkt->allocate(); 137312724Snikos.nikoleris@arm.com pkt->setDataFromBlock(blk->data, blkSize); 137412724Snikos.nikoleris@arm.com 137512724Snikos.nikoleris@arm.com return pkt; 137612724Snikos.nikoleris@arm.com} 137712724Snikos.nikoleris@arm.com 137812724Snikos.nikoleris@arm.com 137912724Snikos.nikoleris@arm.comvoid 138012724Snikos.nikoleris@arm.comBaseCache::memWriteback() 138112724Snikos.nikoleris@arm.com{ 138212728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { writebackVisitor(blk); }); 138312724Snikos.nikoleris@arm.com} 138412724Snikos.nikoleris@arm.com 138512724Snikos.nikoleris@arm.comvoid 138612724Snikos.nikoleris@arm.comBaseCache::memInvalidate() 138712724Snikos.nikoleris@arm.com{ 138812728Snikos.nikoleris@arm.com tags->forEachBlk([this](CacheBlk &blk) { invalidateVisitor(blk); }); 138912724Snikos.nikoleris@arm.com} 139012724Snikos.nikoleris@arm.com 139112724Snikos.nikoleris@arm.combool 139212724Snikos.nikoleris@arm.comBaseCache::isDirty() const 139312724Snikos.nikoleris@arm.com{ 139412728Snikos.nikoleris@arm.com return tags->anyBlk([](CacheBlk &blk) { return blk.isDirty(); }); 139512724Snikos.nikoleris@arm.com} 139612724Snikos.nikoleris@arm.com 139712728Snikos.nikoleris@arm.comvoid 139812724Snikos.nikoleris@arm.comBaseCache::writebackVisitor(CacheBlk &blk) 139912724Snikos.nikoleris@arm.com{ 140012724Snikos.nikoleris@arm.com if (blk.isDirty()) { 140112724Snikos.nikoleris@arm.com assert(blk.isValid()); 140212724Snikos.nikoleris@arm.com 140312749Sgiacomo.travaglini@arm.com RequestPtr request = std::make_shared<Request>( 140412749Sgiacomo.travaglini@arm.com regenerateBlkAddr(&blk), blkSize, 0, Request::funcMasterId); 140512749Sgiacomo.travaglini@arm.com 140612749Sgiacomo.travaglini@arm.com request->taskId(blk.task_id); 140712724Snikos.nikoleris@arm.com if (blk.isSecure()) { 140812749Sgiacomo.travaglini@arm.com request->setFlags(Request::SECURE); 140912724Snikos.nikoleris@arm.com } 141012724Snikos.nikoleris@arm.com 141112749Sgiacomo.travaglini@arm.com Packet packet(request, MemCmd::WriteReq); 141212724Snikos.nikoleris@arm.com packet.dataStatic(blk.data); 141312724Snikos.nikoleris@arm.com 141412724Snikos.nikoleris@arm.com memSidePort.sendFunctional(&packet); 141512724Snikos.nikoleris@arm.com 141612724Snikos.nikoleris@arm.com blk.status &= ~BlkDirty; 141712724Snikos.nikoleris@arm.com } 141812724Snikos.nikoleris@arm.com} 141912724Snikos.nikoleris@arm.com 142012728Snikos.nikoleris@arm.comvoid 142112724Snikos.nikoleris@arm.comBaseCache::invalidateVisitor(CacheBlk &blk) 142212724Snikos.nikoleris@arm.com{ 142312724Snikos.nikoleris@arm.com if (blk.isDirty()) 142412724Snikos.nikoleris@arm.com warn_once("Invalidating dirty cache lines. " \ 142512724Snikos.nikoleris@arm.com "Expect things to break.\n"); 142612724Snikos.nikoleris@arm.com 142712724Snikos.nikoleris@arm.com if (blk.isValid()) { 142812724Snikos.nikoleris@arm.com assert(!blk.isDirty()); 142912724Snikos.nikoleris@arm.com invalidateBlock(&blk); 143012724Snikos.nikoleris@arm.com } 143112724Snikos.nikoleris@arm.com} 143212724Snikos.nikoleris@arm.com 143312724Snikos.nikoleris@arm.comTick 143412724Snikos.nikoleris@arm.comBaseCache::nextQueueReadyTime() const 143512724Snikos.nikoleris@arm.com{ 143612724Snikos.nikoleris@arm.com Tick nextReady = std::min(mshrQueue.nextReadyTime(), 143712724Snikos.nikoleris@arm.com writeBuffer.nextReadyTime()); 143812724Snikos.nikoleris@arm.com 143912724Snikos.nikoleris@arm.com // Don't signal prefetch ready time if no MSHRs available 144012724Snikos.nikoleris@arm.com // Will signal once enoguh MSHRs are deallocated 144112724Snikos.nikoleris@arm.com if (prefetcher && mshrQueue.canPrefetch()) { 144212724Snikos.nikoleris@arm.com nextReady = std::min(nextReady, 144312724Snikos.nikoleris@arm.com prefetcher->nextPrefetchReadyTime()); 144412724Snikos.nikoleris@arm.com } 144512724Snikos.nikoleris@arm.com 144612724Snikos.nikoleris@arm.com return nextReady; 144712724Snikos.nikoleris@arm.com} 144812724Snikos.nikoleris@arm.com 144912724Snikos.nikoleris@arm.com 145012724Snikos.nikoleris@arm.combool 145112724Snikos.nikoleris@arm.comBaseCache::sendMSHRQueuePacket(MSHR* mshr) 145212724Snikos.nikoleris@arm.com{ 145312724Snikos.nikoleris@arm.com assert(mshr); 145412724Snikos.nikoleris@arm.com 145512724Snikos.nikoleris@arm.com // use request from 1st target 145612724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = mshr->getTarget()->pkt; 145712724Snikos.nikoleris@arm.com 145812724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: MSHR %s\n", __func__, tgt_pkt->print()); 145912724Snikos.nikoleris@arm.com 146012724Snikos.nikoleris@arm.com CacheBlk *blk = tags->findBlock(mshr->blkAddr, mshr->isSecure); 146112724Snikos.nikoleris@arm.com 146212724Snikos.nikoleris@arm.com // either a prefetch that is not present upstream, or a normal 146312724Snikos.nikoleris@arm.com // MSHR request, proceed to get the packet to send downstream 146412724Snikos.nikoleris@arm.com PacketPtr pkt = createMissPacket(tgt_pkt, blk, mshr->needsWritable()); 146512724Snikos.nikoleris@arm.com 146612724Snikos.nikoleris@arm.com mshr->isForward = (pkt == nullptr); 146712724Snikos.nikoleris@arm.com 146812724Snikos.nikoleris@arm.com if (mshr->isForward) { 146912724Snikos.nikoleris@arm.com // not a cache block request, but a response is expected 147012724Snikos.nikoleris@arm.com // make copy of current packet to forward, keep current 147112724Snikos.nikoleris@arm.com // copy for response handling 147212724Snikos.nikoleris@arm.com pkt = new Packet(tgt_pkt, false, true); 147312724Snikos.nikoleris@arm.com assert(!pkt->isWrite()); 147412724Snikos.nikoleris@arm.com } 147512724Snikos.nikoleris@arm.com 147612724Snikos.nikoleris@arm.com // play it safe and append (rather than set) the sender state, 147712724Snikos.nikoleris@arm.com // as forwarded packets may already have existing state 147812724Snikos.nikoleris@arm.com pkt->pushSenderState(mshr); 147912724Snikos.nikoleris@arm.com 148012724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 148112724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty block. Mark 148212724Snikos.nikoleris@arm.com // the packet so that the destination xbar can determine that 148312724Snikos.nikoleris@arm.com // there will be a follow-up write packet as well. 148412724Snikos.nikoleris@arm.com pkt->setSatisfied(); 148512724Snikos.nikoleris@arm.com } 148612724Snikos.nikoleris@arm.com 148712724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(pkt)) { 148812724Snikos.nikoleris@arm.com // we are awaiting a retry, but we 148912724Snikos.nikoleris@arm.com // delete the packet and will be creating a new packet 149012724Snikos.nikoleris@arm.com // when we get the opportunity 149112724Snikos.nikoleris@arm.com delete pkt; 149212724Snikos.nikoleris@arm.com 149312724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 149412724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 149512724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 149612724Snikos.nikoleris@arm.com // care about this packet and might override it before 149712724Snikos.nikoleris@arm.com // it gets retried 149812724Snikos.nikoleris@arm.com return true; 149912724Snikos.nikoleris@arm.com } else { 150012724Snikos.nikoleris@arm.com // As part of the call to sendTimingReq the packet is 150112724Snikos.nikoleris@arm.com // forwarded to all neighbouring caches (and any caches 150212724Snikos.nikoleris@arm.com // above them) as a snoop. Thus at this point we know if 150312724Snikos.nikoleris@arm.com // any of the neighbouring caches are responding, and if 150412724Snikos.nikoleris@arm.com // so, we know it is dirty, and we can determine if it is 150512724Snikos.nikoleris@arm.com // being passed as Modified, making our MSHR the ordering 150612724Snikos.nikoleris@arm.com // point 150712724Snikos.nikoleris@arm.com bool pending_modified_resp = !pkt->hasSharers() && 150812724Snikos.nikoleris@arm.com pkt->cacheResponding(); 150912724Snikos.nikoleris@arm.com markInService(mshr, pending_modified_resp); 151012724Snikos.nikoleris@arm.com 151112724Snikos.nikoleris@arm.com if (pkt->isClean() && blk && blk->isDirty()) { 151212724Snikos.nikoleris@arm.com // A cache clean opearation is looking for a dirty 151312724Snikos.nikoleris@arm.com // block. If a dirty block is encountered a WriteClean 151412724Snikos.nikoleris@arm.com // will update any copies to the path to the memory 151512724Snikos.nikoleris@arm.com // until the point of reference. 151612724Snikos.nikoleris@arm.com DPRINTF(CacheVerbose, "%s: packet %s found block: %s\n", 151712724Snikos.nikoleris@arm.com __func__, pkt->print(), blk->print()); 151812724Snikos.nikoleris@arm.com PacketPtr wb_pkt = writecleanBlk(blk, pkt->req->getDest(), 151912724Snikos.nikoleris@arm.com pkt->id); 152012724Snikos.nikoleris@arm.com PacketList writebacks; 152112724Snikos.nikoleris@arm.com writebacks.push_back(wb_pkt); 152212724Snikos.nikoleris@arm.com doWritebacks(writebacks, 0); 152312724Snikos.nikoleris@arm.com } 152412724Snikos.nikoleris@arm.com 152512724Snikos.nikoleris@arm.com return false; 152612724Snikos.nikoleris@arm.com } 152712724Snikos.nikoleris@arm.com} 152812724Snikos.nikoleris@arm.com 152912724Snikos.nikoleris@arm.combool 153012724Snikos.nikoleris@arm.comBaseCache::sendWriteQueuePacket(WriteQueueEntry* wq_entry) 153112724Snikos.nikoleris@arm.com{ 153212724Snikos.nikoleris@arm.com assert(wq_entry); 153312724Snikos.nikoleris@arm.com 153412724Snikos.nikoleris@arm.com // always a single target for write queue entries 153512724Snikos.nikoleris@arm.com PacketPtr tgt_pkt = wq_entry->getTarget()->pkt; 153612724Snikos.nikoleris@arm.com 153712724Snikos.nikoleris@arm.com DPRINTF(Cache, "%s: write %s\n", __func__, tgt_pkt->print()); 153812724Snikos.nikoleris@arm.com 153912724Snikos.nikoleris@arm.com // forward as is, both for evictions and uncacheable writes 154012724Snikos.nikoleris@arm.com if (!memSidePort.sendTimingReq(tgt_pkt)) { 154112724Snikos.nikoleris@arm.com // note that we have now masked any requestBus and 154212724Snikos.nikoleris@arm.com // schedSendEvent (we will wait for a retry before 154312724Snikos.nikoleris@arm.com // doing anything), and this is so even if we do not 154412724Snikos.nikoleris@arm.com // care about this packet and might override it before 154512724Snikos.nikoleris@arm.com // it gets retried 154612724Snikos.nikoleris@arm.com return true; 154712724Snikos.nikoleris@arm.com } else { 154812724Snikos.nikoleris@arm.com markInService(wq_entry); 154912724Snikos.nikoleris@arm.com return false; 155012724Snikos.nikoleris@arm.com } 155112724Snikos.nikoleris@arm.com} 155212724Snikos.nikoleris@arm.com 155312724Snikos.nikoleris@arm.comvoid 155412724Snikos.nikoleris@arm.comBaseCache::serialize(CheckpointOut &cp) const 155512724Snikos.nikoleris@arm.com{ 155612724Snikos.nikoleris@arm.com bool dirty(isDirty()); 155712724Snikos.nikoleris@arm.com 155812724Snikos.nikoleris@arm.com if (dirty) { 155912724Snikos.nikoleris@arm.com warn("*** The cache still contains dirty data. ***\n"); 156012724Snikos.nikoleris@arm.com warn(" Make sure to drain the system using the correct flags.\n"); 156112724Snikos.nikoleris@arm.com warn(" This checkpoint will not restore correctly " \ 156212724Snikos.nikoleris@arm.com "and dirty data in the cache will be lost!\n"); 156312724Snikos.nikoleris@arm.com } 156412724Snikos.nikoleris@arm.com 156512724Snikos.nikoleris@arm.com // Since we don't checkpoint the data in the cache, any dirty data 156612724Snikos.nikoleris@arm.com // will be lost when restoring from a checkpoint of a system that 156712724Snikos.nikoleris@arm.com // wasn't drained properly. Flag the checkpoint as invalid if the 156812724Snikos.nikoleris@arm.com // cache contains dirty data. 156912724Snikos.nikoleris@arm.com bool bad_checkpoint(dirty); 157012724Snikos.nikoleris@arm.com SERIALIZE_SCALAR(bad_checkpoint); 157112724Snikos.nikoleris@arm.com} 157212724Snikos.nikoleris@arm.com 157312724Snikos.nikoleris@arm.comvoid 157412724Snikos.nikoleris@arm.comBaseCache::unserialize(CheckpointIn &cp) 157512724Snikos.nikoleris@arm.com{ 157612724Snikos.nikoleris@arm.com bool bad_checkpoint; 157712724Snikos.nikoleris@arm.com UNSERIALIZE_SCALAR(bad_checkpoint); 157812724Snikos.nikoleris@arm.com if (bad_checkpoint) { 157912724Snikos.nikoleris@arm.com fatal("Restoring from checkpoints with dirty caches is not " 158012724Snikos.nikoleris@arm.com "supported in the classic memory system. Please remove any " 158112724Snikos.nikoleris@arm.com "caches or drain them properly before taking checkpoints.\n"); 158212724Snikos.nikoleris@arm.com } 158312724Snikos.nikoleris@arm.com} 158412724Snikos.nikoleris@arm.com 158512724Snikos.nikoleris@arm.comvoid 15862810SN/ABaseCache::regStats() 15872810SN/A{ 158811522Sstephan.diestelhorst@arm.com MemObject::regStats(); 158911522Sstephan.diestelhorst@arm.com 15902810SN/A using namespace Stats; 15912810SN/A 15922810SN/A // Hit statistics 15934022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 15944022SN/A MemCmd cmd(access_idx); 15954022SN/A const string &cstr = cmd.toString(); 15962810SN/A 15972810SN/A hits[access_idx] 15988833Sdam.sunwoo@arm.com .init(system->maxMasters()) 15992810SN/A .name(name() + "." + cstr + "_hits") 16002810SN/A .desc("number of " + cstr + " hits") 16012810SN/A .flags(total | nozero | nonan) 16022810SN/A ; 16038833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16048833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 16058833Sdam.sunwoo@arm.com } 16062810SN/A } 16072810SN/A 16084871SN/A// These macros make it easier to sum the right subset of commands and 16094871SN/A// to change the subset of commands that are considered "demand" vs 16104871SN/A// "non-demand" 16114871SN/A#define SUM_DEMAND(s) \ 161211455Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \ 161310885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 16144871SN/A 16154871SN/A// should writebacks be included here? prior code was inconsistent... 16164871SN/A#define SUM_NON_DEMAND(s) \ 16174871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 16184871SN/A 16192810SN/A demandHits 16202810SN/A .name(name() + ".demand_hits") 16212810SN/A .desc("number of demand (read+write) hits") 16228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16232810SN/A ; 16244871SN/A demandHits = SUM_DEMAND(hits); 16258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16268833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 16278833Sdam.sunwoo@arm.com } 16282810SN/A 16292810SN/A overallHits 16302810SN/A .name(name() + ".overall_hits") 16312810SN/A .desc("number of overall hits") 16328833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16332810SN/A ; 16344871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 16358833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16368833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 16378833Sdam.sunwoo@arm.com } 16382810SN/A 16392810SN/A // Miss statistics 16404022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 16414022SN/A MemCmd cmd(access_idx); 16424022SN/A const string &cstr = cmd.toString(); 16432810SN/A 16442810SN/A misses[access_idx] 16458833Sdam.sunwoo@arm.com .init(system->maxMasters()) 16462810SN/A .name(name() + "." + cstr + "_misses") 16472810SN/A .desc("number of " + cstr + " misses") 16482810SN/A .flags(total | nozero | nonan) 16492810SN/A ; 16508833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16518833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 16528833Sdam.sunwoo@arm.com } 16532810SN/A } 16542810SN/A 16552810SN/A demandMisses 16562810SN/A .name(name() + ".demand_misses") 16572810SN/A .desc("number of demand (read+write) misses") 16588833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16592810SN/A ; 16604871SN/A demandMisses = SUM_DEMAND(misses); 16618833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16628833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 16638833Sdam.sunwoo@arm.com } 16642810SN/A 16652810SN/A overallMisses 16662810SN/A .name(name() + ".overall_misses") 16672810SN/A .desc("number of overall misses") 16688833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16692810SN/A ; 16704871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 16718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16728833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 16738833Sdam.sunwoo@arm.com } 16742810SN/A 16752810SN/A // Miss latency statistics 16764022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 16774022SN/A MemCmd cmd(access_idx); 16784022SN/A const string &cstr = cmd.toString(); 16792810SN/A 16802810SN/A missLatency[access_idx] 16818833Sdam.sunwoo@arm.com .init(system->maxMasters()) 16822810SN/A .name(name() + "." + cstr + "_miss_latency") 16832810SN/A .desc("number of " + cstr + " miss cycles") 16842810SN/A .flags(total | nozero | nonan) 16852810SN/A ; 16868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16878833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 16888833Sdam.sunwoo@arm.com } 16892810SN/A } 16902810SN/A 16912810SN/A demandMissLatency 16922810SN/A .name(name() + ".demand_miss_latency") 16932810SN/A .desc("number of demand (read+write) miss cycles") 16948833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 16952810SN/A ; 16964871SN/A demandMissLatency = SUM_DEMAND(missLatency); 16978833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 16988833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 16998833Sdam.sunwoo@arm.com } 17002810SN/A 17012810SN/A overallMissLatency 17022810SN/A .name(name() + ".overall_miss_latency") 17032810SN/A .desc("number of overall miss cycles") 17048833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17052810SN/A ; 17064871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 17078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17088833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 17098833Sdam.sunwoo@arm.com } 17102810SN/A 17112810SN/A // access formulas 17124022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17134022SN/A MemCmd cmd(access_idx); 17144022SN/A const string &cstr = cmd.toString(); 17152810SN/A 17162810SN/A accesses[access_idx] 17172810SN/A .name(name() + "." + cstr + "_accesses") 17182810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 17192810SN/A .flags(total | nozero | nonan) 17202810SN/A ; 17218833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 17222810SN/A 17238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17248833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 17258833Sdam.sunwoo@arm.com } 17262810SN/A } 17272810SN/A 17282810SN/A demandAccesses 17292810SN/A .name(name() + ".demand_accesses") 17302810SN/A .desc("number of demand (read+write) accesses") 17318833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17322810SN/A ; 17332810SN/A demandAccesses = demandHits + demandMisses; 17348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17358833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 17368833Sdam.sunwoo@arm.com } 17372810SN/A 17382810SN/A overallAccesses 17392810SN/A .name(name() + ".overall_accesses") 17402810SN/A .desc("number of overall (read+write) accesses") 17418833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17422810SN/A ; 17432810SN/A overallAccesses = overallHits + overallMisses; 17448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17458833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 17468833Sdam.sunwoo@arm.com } 17472810SN/A 17482810SN/A // miss rate formulas 17494022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17504022SN/A MemCmd cmd(access_idx); 17514022SN/A const string &cstr = cmd.toString(); 17522810SN/A 17532810SN/A missRate[access_idx] 17542810SN/A .name(name() + "." + cstr + "_miss_rate") 17552810SN/A .desc("miss rate for " + cstr + " accesses") 17562810SN/A .flags(total | nozero | nonan) 17572810SN/A ; 17588833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 17592810SN/A 17608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17618833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 17628833Sdam.sunwoo@arm.com } 17632810SN/A } 17642810SN/A 17652810SN/A demandMissRate 17662810SN/A .name(name() + ".demand_miss_rate") 17672810SN/A .desc("miss rate for demand accesses") 17688833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17692810SN/A ; 17702810SN/A demandMissRate = demandMisses / demandAccesses; 17718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17728833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 17738833Sdam.sunwoo@arm.com } 17742810SN/A 17752810SN/A overallMissRate 17762810SN/A .name(name() + ".overall_miss_rate") 17772810SN/A .desc("miss rate for overall accesses") 17788833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 17792810SN/A ; 17802810SN/A overallMissRate = overallMisses / overallAccesses; 17818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17828833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 17838833Sdam.sunwoo@arm.com } 17842810SN/A 17852810SN/A // miss latency formulas 17864022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 17874022SN/A MemCmd cmd(access_idx); 17884022SN/A const string &cstr = cmd.toString(); 17892810SN/A 17902810SN/A avgMissLatency[access_idx] 17912810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 17922810SN/A .desc("average " + cstr + " miss latency") 17932810SN/A .flags(total | nozero | nonan) 17942810SN/A ; 17952810SN/A avgMissLatency[access_idx] = 17962810SN/A missLatency[access_idx] / misses[access_idx]; 17978833Sdam.sunwoo@arm.com 17988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 17998833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 18008833Sdam.sunwoo@arm.com } 18012810SN/A } 18022810SN/A 18032810SN/A demandAvgMissLatency 18042810SN/A .name(name() + ".demand_avg_miss_latency") 18052810SN/A .desc("average overall miss latency") 18068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18072810SN/A ; 18082810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 18098833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18108833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 18118833Sdam.sunwoo@arm.com } 18122810SN/A 18132810SN/A overallAvgMissLatency 18142810SN/A .name(name() + ".overall_avg_miss_latency") 18152810SN/A .desc("average overall miss latency") 18168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18172810SN/A ; 18182810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 18198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18208833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 18218833Sdam.sunwoo@arm.com } 18222810SN/A 18232810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 18242810SN/A blocked_cycles 18252810SN/A .name(name() + ".blocked_cycles") 18262810SN/A .desc("number of cycles access was blocked") 18272810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18282810SN/A .subname(Blocked_NoTargets, "no_targets") 18292810SN/A ; 18302810SN/A 18312810SN/A 18322810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 18332810SN/A blocked_causes 18342810SN/A .name(name() + ".blocked") 18352810SN/A .desc("number of cycles access was blocked") 18362810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18372810SN/A .subname(Blocked_NoTargets, "no_targets") 18382810SN/A ; 18392810SN/A 18402810SN/A avg_blocked 18412810SN/A .name(name() + ".avg_blocked_cycles") 18422810SN/A .desc("average number of cycles each access was blocked") 18432810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 18442810SN/A .subname(Blocked_NoTargets, "no_targets") 18452810SN/A ; 18462810SN/A 18472810SN/A avg_blocked = blocked_cycles / blocked_causes; 18482810SN/A 184911436SRekai.GonzalezAlberquilla@arm.com unusedPrefetches 185011436SRekai.GonzalezAlberquilla@arm.com .name(name() + ".unused_prefetches") 185111436SRekai.GonzalezAlberquilla@arm.com .desc("number of HardPF blocks evicted w/o reference") 185211436SRekai.GonzalezAlberquilla@arm.com .flags(nozero) 185311436SRekai.GonzalezAlberquilla@arm.com ; 185411436SRekai.GonzalezAlberquilla@arm.com 18554626SN/A writebacks 18568833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18574626SN/A .name(name() + ".writebacks") 18584626SN/A .desc("number of writebacks") 18598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18604626SN/A ; 18618833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18628833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 18638833Sdam.sunwoo@arm.com } 18644626SN/A 18654626SN/A // MSHR statistics 18664626SN/A // MSHR hit statistics 18674626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 18684626SN/A MemCmd cmd(access_idx); 18694626SN/A const string &cstr = cmd.toString(); 18704626SN/A 18714626SN/A mshr_hits[access_idx] 18728833Sdam.sunwoo@arm.com .init(system->maxMasters()) 18734626SN/A .name(name() + "." + cstr + "_mshr_hits") 18744626SN/A .desc("number of " + cstr + " MSHR hits") 18754626SN/A .flags(total | nozero | nonan) 18764626SN/A ; 18778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18788833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 18798833Sdam.sunwoo@arm.com } 18804626SN/A } 18814626SN/A 18824626SN/A demandMshrHits 18834626SN/A .name(name() + ".demand_mshr_hits") 18844626SN/A .desc("number of demand (read+write) MSHR hits") 18858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18864626SN/A ; 18874871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 18888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18898833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 18908833Sdam.sunwoo@arm.com } 18914626SN/A 18924626SN/A overallMshrHits 18934626SN/A .name(name() + ".overall_mshr_hits") 18944626SN/A .desc("number of overall MSHR hits") 18958833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 18964626SN/A ; 18974871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 18988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 18998833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 19008833Sdam.sunwoo@arm.com } 19014626SN/A 19024626SN/A // MSHR miss statistics 19034626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19044626SN/A MemCmd cmd(access_idx); 19054626SN/A const string &cstr = cmd.toString(); 19064626SN/A 19074626SN/A mshr_misses[access_idx] 19088833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19094626SN/A .name(name() + "." + cstr + "_mshr_misses") 19104626SN/A .desc("number of " + cstr + " MSHR misses") 19114626SN/A .flags(total | nozero | nonan) 19124626SN/A ; 19138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19148833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 19158833Sdam.sunwoo@arm.com } 19164626SN/A } 19174626SN/A 19184626SN/A demandMshrMisses 19194626SN/A .name(name() + ".demand_mshr_misses") 19204626SN/A .desc("number of demand (read+write) MSHR misses") 19218833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19224626SN/A ; 19234871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 19248833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19258833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 19268833Sdam.sunwoo@arm.com } 19274626SN/A 19284626SN/A overallMshrMisses 19294626SN/A .name(name() + ".overall_mshr_misses") 19304626SN/A .desc("number of overall MSHR misses") 19318833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19324626SN/A ; 19334871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 19348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19358833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 19368833Sdam.sunwoo@arm.com } 19374626SN/A 19384626SN/A // MSHR miss latency statistics 19394626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19404626SN/A MemCmd cmd(access_idx); 19414626SN/A const string &cstr = cmd.toString(); 19424626SN/A 19434626SN/A mshr_miss_latency[access_idx] 19448833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19454626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 19464626SN/A .desc("number of " + cstr + " MSHR miss cycles") 19474626SN/A .flags(total | nozero | nonan) 19484626SN/A ; 19498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19508833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 19518833Sdam.sunwoo@arm.com } 19524626SN/A } 19534626SN/A 19544626SN/A demandMshrMissLatency 19554626SN/A .name(name() + ".demand_mshr_miss_latency") 19564626SN/A .desc("number of demand (read+write) MSHR miss cycles") 19578833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19584626SN/A ; 19594871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 19608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19618833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 19628833Sdam.sunwoo@arm.com } 19634626SN/A 19644626SN/A overallMshrMissLatency 19654626SN/A .name(name() + ".overall_mshr_miss_latency") 19664626SN/A .desc("number of overall MSHR miss cycles") 19678833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19684626SN/A ; 19694871SN/A overallMshrMissLatency = 19704871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 19718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19728833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 19738833Sdam.sunwoo@arm.com } 19744626SN/A 19754626SN/A // MSHR uncacheable statistics 19764626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 19774626SN/A MemCmd cmd(access_idx); 19784626SN/A const string &cstr = cmd.toString(); 19794626SN/A 19804626SN/A mshr_uncacheable[access_idx] 19818833Sdam.sunwoo@arm.com .init(system->maxMasters()) 19824626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 19834626SN/A .desc("number of " + cstr + " MSHR uncacheable") 19844626SN/A .flags(total | nozero | nonan) 19854626SN/A ; 19868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19878833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 19888833Sdam.sunwoo@arm.com } 19894626SN/A } 19904626SN/A 19914626SN/A overallMshrUncacheable 19924626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 19934626SN/A .desc("number of overall MSHR uncacheable misses") 19948833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 19954626SN/A ; 19964871SN/A overallMshrUncacheable = 19974871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 19988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 19998833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 20008833Sdam.sunwoo@arm.com } 20014626SN/A 20024626SN/A // MSHR miss latency statistics 20034626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20044626SN/A MemCmd cmd(access_idx); 20054626SN/A const string &cstr = cmd.toString(); 20064626SN/A 20074626SN/A mshr_uncacheable_lat[access_idx] 20088833Sdam.sunwoo@arm.com .init(system->maxMasters()) 20094626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 20104626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 20114626SN/A .flags(total | nozero | nonan) 20124626SN/A ; 20138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 201411483Snikos.nikoleris@arm.com mshr_uncacheable_lat[access_idx].subname( 201511483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 20168833Sdam.sunwoo@arm.com } 20174626SN/A } 20184626SN/A 20194626SN/A overallMshrUncacheableLatency 20204626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 20214626SN/A .desc("number of overall MSHR uncacheable cycles") 20228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20234626SN/A ; 20244871SN/A overallMshrUncacheableLatency = 20254871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 20264871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 20278833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20288833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 20298833Sdam.sunwoo@arm.com } 20304626SN/A 20314626SN/A#if 0 20324626SN/A // MSHR access formulas 20334626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20344626SN/A MemCmd cmd(access_idx); 20354626SN/A const string &cstr = cmd.toString(); 20364626SN/A 20374626SN/A mshrAccesses[access_idx] 20384626SN/A .name(name() + "." + cstr + "_mshr_accesses") 20394626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 20404626SN/A .flags(total | nozero | nonan) 20414626SN/A ; 20424626SN/A mshrAccesses[access_idx] = 20434626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 20444626SN/A + mshr_uncacheable[access_idx]; 20454626SN/A } 20464626SN/A 20474626SN/A demandMshrAccesses 20484626SN/A .name(name() + ".demand_mshr_accesses") 20494626SN/A .desc("number of demand (read+write) mshr accesses") 20504626SN/A .flags(total | nozero | nonan) 20514626SN/A ; 20524626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 20534626SN/A 20544626SN/A overallMshrAccesses 20554626SN/A .name(name() + ".overall_mshr_accesses") 20564626SN/A .desc("number of overall (read+write) mshr accesses") 20574626SN/A .flags(total | nozero | nonan) 20584626SN/A ; 20594626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 20604626SN/A + overallMshrUncacheable; 20614626SN/A#endif 20624626SN/A 20634626SN/A // MSHR miss rate formulas 20644626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 20654626SN/A MemCmd cmd(access_idx); 20664626SN/A const string &cstr = cmd.toString(); 20674626SN/A 20684626SN/A mshrMissRate[access_idx] 20694626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 20704626SN/A .desc("mshr miss rate for " + cstr + " accesses") 20714626SN/A .flags(total | nozero | nonan) 20724626SN/A ; 20734626SN/A mshrMissRate[access_idx] = 20744626SN/A mshr_misses[access_idx] / accesses[access_idx]; 20758833Sdam.sunwoo@arm.com 20768833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20778833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 20788833Sdam.sunwoo@arm.com } 20794626SN/A } 20804626SN/A 20814626SN/A demandMshrMissRate 20824626SN/A .name(name() + ".demand_mshr_miss_rate") 20834626SN/A .desc("mshr miss rate for demand accesses") 20848833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20854626SN/A ; 20864626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 20878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20888833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 20898833Sdam.sunwoo@arm.com } 20904626SN/A 20914626SN/A overallMshrMissRate 20924626SN/A .name(name() + ".overall_mshr_miss_rate") 20934626SN/A .desc("mshr miss rate for overall accesses") 20948833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 20954626SN/A ; 20964626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 20978833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 20988833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 20998833Sdam.sunwoo@arm.com } 21004626SN/A 21014626SN/A // mshrMiss latency formulas 21024626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21034626SN/A MemCmd cmd(access_idx); 21044626SN/A const string &cstr = cmd.toString(); 21054626SN/A 21064626SN/A avgMshrMissLatency[access_idx] 21074626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 21084626SN/A .desc("average " + cstr + " mshr miss latency") 21094626SN/A .flags(total | nozero | nonan) 21104626SN/A ; 21114626SN/A avgMshrMissLatency[access_idx] = 21124626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 21138833Sdam.sunwoo@arm.com 21148833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 211511483Snikos.nikoleris@arm.com avgMshrMissLatency[access_idx].subname( 211611483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 21178833Sdam.sunwoo@arm.com } 21184626SN/A } 21194626SN/A 21204626SN/A demandAvgMshrMissLatency 21214626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 21224626SN/A .desc("average overall mshr miss latency") 21238833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21244626SN/A ; 21254626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 21268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21278833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 21288833Sdam.sunwoo@arm.com } 21294626SN/A 21304626SN/A overallAvgMshrMissLatency 21314626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 21324626SN/A .desc("average overall mshr miss latency") 21338833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21344626SN/A ; 21354626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 21368833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21378833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 21388833Sdam.sunwoo@arm.com } 21394626SN/A 21404626SN/A // mshrUncacheable latency formulas 21414626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 21424626SN/A MemCmd cmd(access_idx); 21434626SN/A const string &cstr = cmd.toString(); 21444626SN/A 21454626SN/A avgMshrUncacheableLatency[access_idx] 21464626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 21474626SN/A .desc("average " + cstr + " mshr uncacheable latency") 21484626SN/A .flags(total | nozero | nonan) 21494626SN/A ; 21504626SN/A avgMshrUncacheableLatency[access_idx] = 21514626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 21528833Sdam.sunwoo@arm.com 21538833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 215411483Snikos.nikoleris@arm.com avgMshrUncacheableLatency[access_idx].subname( 215511483Snikos.nikoleris@arm.com i, system->getMasterName(i)); 21568833Sdam.sunwoo@arm.com } 21574626SN/A } 21584626SN/A 21594626SN/A overallAvgMshrUncacheableLatency 21604626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 21614626SN/A .desc("average overall mshr uncacheable latency") 21628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 21634626SN/A ; 216411483Snikos.nikoleris@arm.com overallAvgMshrUncacheableLatency = 216511483Snikos.nikoleris@arm.com overallMshrUncacheableLatency / overallMshrUncacheable; 21668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 21678833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 21688833Sdam.sunwoo@arm.com } 21694626SN/A 217012702Snikos.nikoleris@arm.com replacements 217112702Snikos.nikoleris@arm.com .name(name() + ".replacements") 217212702Snikos.nikoleris@arm.com .desc("number of replacements") 217312702Snikos.nikoleris@arm.com ; 21742810SN/A} 217512724Snikos.nikoleris@arm.com 217612724Snikos.nikoleris@arm.com/////////////// 217712724Snikos.nikoleris@arm.com// 217812724Snikos.nikoleris@arm.com// CpuSidePort 217912724Snikos.nikoleris@arm.com// 218012724Snikos.nikoleris@arm.com/////////////// 218112724Snikos.nikoleris@arm.combool 218212724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingSnoopResp(PacketPtr pkt) 218312724Snikos.nikoleris@arm.com{ 218412725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 218512725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 218612725Snikos.nikoleris@arm.com 218712725Snikos.nikoleris@arm.com assert(pkt->isResponse()); 218812725Snikos.nikoleris@arm.com 218912724Snikos.nikoleris@arm.com // Express snoop responses from master to slave, e.g., from L1 to L2 219012724Snikos.nikoleris@arm.com cache->recvTimingSnoopResp(pkt); 219112724Snikos.nikoleris@arm.com return true; 219212724Snikos.nikoleris@arm.com} 219312724Snikos.nikoleris@arm.com 219412724Snikos.nikoleris@arm.com 219512724Snikos.nikoleris@arm.combool 219612724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::tryTiming(PacketPtr pkt) 219712724Snikos.nikoleris@arm.com{ 219812725Snikos.nikoleris@arm.com if (cache->system->bypassCaches() || pkt->isExpressSnoop()) { 219912724Snikos.nikoleris@arm.com // always let express snoop packets through even if blocked 220012724Snikos.nikoleris@arm.com return true; 220112724Snikos.nikoleris@arm.com } else if (blocked || mustSendRetry) { 220212724Snikos.nikoleris@arm.com // either already committed to send a retry, or blocked 220312724Snikos.nikoleris@arm.com mustSendRetry = true; 220412724Snikos.nikoleris@arm.com return false; 220512724Snikos.nikoleris@arm.com } 220612724Snikos.nikoleris@arm.com mustSendRetry = false; 220712724Snikos.nikoleris@arm.com return true; 220812724Snikos.nikoleris@arm.com} 220912724Snikos.nikoleris@arm.com 221012724Snikos.nikoleris@arm.combool 221112724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvTimingReq(PacketPtr pkt) 221212724Snikos.nikoleris@arm.com{ 221312725Snikos.nikoleris@arm.com assert(pkt->isRequest()); 221412725Snikos.nikoleris@arm.com 221512725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 221612725Snikos.nikoleris@arm.com // Just forward the packet if caches are disabled. 221712725Snikos.nikoleris@arm.com // @todo This should really enqueue the packet rather 221812725Snikos.nikoleris@arm.com bool M5_VAR_USED success = cache->memSidePort.sendTimingReq(pkt); 221912725Snikos.nikoleris@arm.com assert(success); 222012725Snikos.nikoleris@arm.com return true; 222112725Snikos.nikoleris@arm.com } else if (tryTiming(pkt)) { 222212724Snikos.nikoleris@arm.com cache->recvTimingReq(pkt); 222312724Snikos.nikoleris@arm.com return true; 222412724Snikos.nikoleris@arm.com } 222512724Snikos.nikoleris@arm.com return false; 222612724Snikos.nikoleris@arm.com} 222712724Snikos.nikoleris@arm.com 222812724Snikos.nikoleris@arm.comTick 222912724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvAtomic(PacketPtr pkt) 223012724Snikos.nikoleris@arm.com{ 223112725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 223212725Snikos.nikoleris@arm.com // Forward the request if the system is in cache bypass mode. 223312725Snikos.nikoleris@arm.com return cache->memSidePort.sendAtomic(pkt); 223412725Snikos.nikoleris@arm.com } else { 223512725Snikos.nikoleris@arm.com return cache->recvAtomic(pkt); 223612725Snikos.nikoleris@arm.com } 223712724Snikos.nikoleris@arm.com} 223812724Snikos.nikoleris@arm.com 223912724Snikos.nikoleris@arm.comvoid 224012724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::recvFunctional(PacketPtr pkt) 224112724Snikos.nikoleris@arm.com{ 224212725Snikos.nikoleris@arm.com if (cache->system->bypassCaches()) { 224312725Snikos.nikoleris@arm.com // The cache should be flushed if we are in cache bypass mode, 224412725Snikos.nikoleris@arm.com // so we don't need to check if we need to update anything. 224512725Snikos.nikoleris@arm.com cache->memSidePort.sendFunctional(pkt); 224612725Snikos.nikoleris@arm.com return; 224712725Snikos.nikoleris@arm.com } 224812725Snikos.nikoleris@arm.com 224912724Snikos.nikoleris@arm.com // functional request 225012724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, true); 225112724Snikos.nikoleris@arm.com} 225212724Snikos.nikoleris@arm.com 225312724Snikos.nikoleris@arm.comAddrRangeList 225412724Snikos.nikoleris@arm.comBaseCache::CpuSidePort::getAddrRanges() const 225512724Snikos.nikoleris@arm.com{ 225612724Snikos.nikoleris@arm.com return cache->getAddrRanges(); 225712724Snikos.nikoleris@arm.com} 225812724Snikos.nikoleris@arm.com 225912724Snikos.nikoleris@arm.com 226012724Snikos.nikoleris@arm.comBaseCache:: 226112724Snikos.nikoleris@arm.comCpuSidePort::CpuSidePort(const std::string &_name, BaseCache *_cache, 226212724Snikos.nikoleris@arm.com const std::string &_label) 226312724Snikos.nikoleris@arm.com : CacheSlavePort(_name, _cache, _label), cache(_cache) 226412724Snikos.nikoleris@arm.com{ 226512724Snikos.nikoleris@arm.com} 226612724Snikos.nikoleris@arm.com 226712724Snikos.nikoleris@arm.com/////////////// 226812724Snikos.nikoleris@arm.com// 226912724Snikos.nikoleris@arm.com// MemSidePort 227012724Snikos.nikoleris@arm.com// 227112724Snikos.nikoleris@arm.com/////////////// 227212724Snikos.nikoleris@arm.combool 227312724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingResp(PacketPtr pkt) 227412724Snikos.nikoleris@arm.com{ 227512724Snikos.nikoleris@arm.com cache->recvTimingResp(pkt); 227612724Snikos.nikoleris@arm.com return true; 227712724Snikos.nikoleris@arm.com} 227812724Snikos.nikoleris@arm.com 227912724Snikos.nikoleris@arm.com// Express snooping requests to memside port 228012724Snikos.nikoleris@arm.comvoid 228112724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvTimingSnoopReq(PacketPtr pkt) 228212724Snikos.nikoleris@arm.com{ 228312725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 228412725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 228512725Snikos.nikoleris@arm.com 228612724Snikos.nikoleris@arm.com // handle snooping requests 228712724Snikos.nikoleris@arm.com cache->recvTimingSnoopReq(pkt); 228812724Snikos.nikoleris@arm.com} 228912724Snikos.nikoleris@arm.com 229012724Snikos.nikoleris@arm.comTick 229112724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvAtomicSnoop(PacketPtr pkt) 229212724Snikos.nikoleris@arm.com{ 229312725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 229412725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 229512725Snikos.nikoleris@arm.com 229612724Snikos.nikoleris@arm.com return cache->recvAtomicSnoop(pkt); 229712724Snikos.nikoleris@arm.com} 229812724Snikos.nikoleris@arm.com 229912724Snikos.nikoleris@arm.comvoid 230012724Snikos.nikoleris@arm.comBaseCache::MemSidePort::recvFunctionalSnoop(PacketPtr pkt) 230112724Snikos.nikoleris@arm.com{ 230212725Snikos.nikoleris@arm.com // Snoops shouldn't happen when bypassing caches 230312725Snikos.nikoleris@arm.com assert(!cache->system->bypassCaches()); 230412725Snikos.nikoleris@arm.com 230512724Snikos.nikoleris@arm.com // functional snoop (note that in contrast to atomic we don't have 230612724Snikos.nikoleris@arm.com // a specific functionalSnoop method, as they have the same 230712724Snikos.nikoleris@arm.com // behaviour regardless) 230812724Snikos.nikoleris@arm.com cache->functionalAccess(pkt, false); 230912724Snikos.nikoleris@arm.com} 231012724Snikos.nikoleris@arm.com 231112724Snikos.nikoleris@arm.comvoid 231212724Snikos.nikoleris@arm.comBaseCache::CacheReqPacketQueue::sendDeferredPacket() 231312724Snikos.nikoleris@arm.com{ 231412724Snikos.nikoleris@arm.com // sanity check 231512724Snikos.nikoleris@arm.com assert(!waitingOnRetry); 231612724Snikos.nikoleris@arm.com 231712724Snikos.nikoleris@arm.com // there should never be any deferred request packets in the 231812724Snikos.nikoleris@arm.com // queue, instead we resly on the cache to provide the packets 231912724Snikos.nikoleris@arm.com // from the MSHR queue or write queue 232012724Snikos.nikoleris@arm.com assert(deferredPacketReadyTime() == MaxTick); 232112724Snikos.nikoleris@arm.com 232212724Snikos.nikoleris@arm.com // check for request packets (requests & writebacks) 232312724Snikos.nikoleris@arm.com QueueEntry* entry = cache.getNextQueueEntry(); 232412724Snikos.nikoleris@arm.com 232512724Snikos.nikoleris@arm.com if (!entry) { 232612724Snikos.nikoleris@arm.com // can happen if e.g. we attempt a writeback and fail, but 232712724Snikos.nikoleris@arm.com // before the retry, the writeback is eliminated because 232812724Snikos.nikoleris@arm.com // we snoop another cache's ReadEx. 232912724Snikos.nikoleris@arm.com } else { 233012724Snikos.nikoleris@arm.com // let our snoop responses go first if there are responses to 233112724Snikos.nikoleris@arm.com // the same addresses 233212724Snikos.nikoleris@arm.com if (checkConflictingSnoop(entry->blkAddr)) { 233312724Snikos.nikoleris@arm.com return; 233412724Snikos.nikoleris@arm.com } 233512724Snikos.nikoleris@arm.com waitingOnRetry = entry->sendPacket(cache); 233612724Snikos.nikoleris@arm.com } 233712724Snikos.nikoleris@arm.com 233812724Snikos.nikoleris@arm.com // if we succeeded and are not waiting for a retry, schedule the 233912724Snikos.nikoleris@arm.com // next send considering when the next queue is ready, note that 234012724Snikos.nikoleris@arm.com // snoop responses have their own packet queue and thus schedule 234112724Snikos.nikoleris@arm.com // their own events 234212724Snikos.nikoleris@arm.com if (!waitingOnRetry) { 234312724Snikos.nikoleris@arm.com schedSendEvent(cache.nextQueueReadyTime()); 234412724Snikos.nikoleris@arm.com } 234512724Snikos.nikoleris@arm.com} 234612724Snikos.nikoleris@arm.com 234712724Snikos.nikoleris@arm.comBaseCache::MemSidePort::MemSidePort(const std::string &_name, 234812724Snikos.nikoleris@arm.com BaseCache *_cache, 234912724Snikos.nikoleris@arm.com const std::string &_label) 235012724Snikos.nikoleris@arm.com : CacheMasterPort(_name, _cache, _reqQueue, _snoopRespQueue), 235112724Snikos.nikoleris@arm.com _reqQueue(*_cache, *this, _snoopRespQueue, _label), 235212724Snikos.nikoleris@arm.com _snoopRespQueue(*_cache, *this, _label), cache(_cache) 235312724Snikos.nikoleris@arm.com{ 235412724Snikos.nikoleris@arm.com} 2355