base.cc revision 11486
19243SN/A/*
210206Sandreas.hansson@arm.com * Copyright (c) 2012-2013 ARM Limited
39243SN/A * All rights reserved.
49243SN/A *
59243SN/A * The license below extends only to copyright in the software and shall
69243SN/A * not be construed as granting a license to any other intellectual
79243SN/A * property including but not limited to intellectual property relating
89243SN/A * to a hardware implementation of the functionality of the software
99243SN/A * licensed hereunder.  You may use the software subject to the license
109243SN/A * terms below provided that you ensure that this notice is replicated
119243SN/A * unmodified and in its entirety in all distributions of the software,
129243SN/A * modified or unmodified, in source code or in binary form.
139243SN/A *
149831SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan
159831SN/A * All rights reserved.
169831SN/A *
179243SN/A * Redistribution and use in source and binary forms, with or without
189243SN/A * modification, are permitted provided that the following conditions are
199243SN/A * met: redistributions of source code must retain the above copyright
209243SN/A * notice, this list of conditions and the following disclaimer;
219243SN/A * redistributions in binary form must reproduce the above copyright
229243SN/A * notice, this list of conditions and the following disclaimer in the
239243SN/A * documentation and/or other materials provided with the distribution;
249243SN/A * neither the name of the copyright holders nor the names of its
259243SN/A * contributors may be used to endorse or promote products derived from
269243SN/A * this software without specific prior written permission.
279243SN/A *
289243SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
299243SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
309243SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
319243SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
329243SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
339243SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
349243SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
359243SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
369243SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
379243SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
389243SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
399243SN/A *
409243SN/A * Authors: Erik Hallnor
419243SN/A */
429967SN/A
4310618SOmar.Naji@arm.com/**
449243SN/A * @file
459243SN/A * Definition of BaseCache functions.
4610146Sandreas.hansson@arm.com */
479356SN/A
4810146Sandreas.hansson@arm.com#include "mem/cache/base.hh"
4910247Sandreas.hansson@arm.com
5010208Sandreas.hansson@arm.com#include "debug/Cache.hh"
519352SN/A#include "debug/Drain.hh"
5210146Sandreas.hansson@arm.com#include "mem/cache/cache.hh"
539814SN/A#include "mem/cache/mshr.hh"
549243SN/A#include "mem/cache/tags/fa_lru.hh"
559243SN/A#include "mem/cache/tags/lru.hh"
5610432SOmar.Naji@arm.com#include "mem/cache/tags/random_repl.hh"
579243SN/A#include "sim/full_system.hh"
5810146Sandreas.hansson@arm.com
599243SN/Ausing namespace std;
6010619Sandreas.hansson@arm.com
619243SN/ABaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name,
6210211Sandreas.hansson@arm.com                                          BaseCache *_cache,
6310618SOmar.Naji@arm.com                                          const std::string &_label)
6410208Sandreas.hansson@arm.com    : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label),
6510489SOmar.Naji@arm.com      blocked(false), mustSendRetry(false), sendRetryEvent(this)
669831SN/A{
679831SN/A}
689831SN/A
699831SN/ABaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size)
709831SN/A    : MemObject(p),
7110140SN/A      cpuSidePort(nullptr), memSidePort(nullptr),
7210286Sandreas.hansson@arm.com      mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below
739243SN/A      writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below
7410394Swendy.elsasser@arm.com      blkSize(blk_size),
7510394Swendy.elsasser@arm.com      lookupLatency(p->hit_latency),
769566SN/A      forwardLatency(p->hit_latency),
779243SN/A      fillLatency(p->response_latency),
789243SN/A      responseLatency(p->response_latency),
7910140SN/A      numTarget(p->tgts_per_mshr),
8010140SN/A      forwardSnoops(true),
8110147Sandreas.hansson@arm.com      isReadOnly(p->is_read_only),
8210147Sandreas.hansson@arm.com      blocked(0),
8310393Swendy.elsasser@arm.com      order(0),
8410394Swendy.elsasser@arm.com      noTargetMSHR(nullptr),
8510394Swendy.elsasser@arm.com      missCount(p->max_miss_count),
8610394Swendy.elsasser@arm.com      addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()),
879243SN/A      system(p->system)
889243SN/A{
8910141SN/A    // the MSHR queue has no reserve entries as we check the MSHR
909726SN/A    // queue on every single allocation, whereas the write queue has
919726SN/A    // as many reserve entries as we have MSHRs, since every MSHR may
9210618SOmar.Naji@arm.com    // eventually require a writeback, and we do not check the write
9310618SOmar.Naji@arm.com    // buffer before committing to an MSHR
949243SN/A
9510620Sandreas.hansson@arm.com    // forward snoops is overridden in init() once we can query
9610620Sandreas.hansson@arm.com    // whether the connected master is actually snooping or not
9710620Sandreas.hansson@arm.com}
9810620Sandreas.hansson@arm.com
9910620Sandreas.hansson@arm.comvoid
10010618SOmar.Naji@arm.comBaseCache::CacheSlavePort::setBlocked()
10110618SOmar.Naji@arm.com{
10210618SOmar.Naji@arm.com    assert(!blocked);
10310432SOmar.Naji@arm.com    DPRINTF(CachePort, "Port is blocking new requests\n");
10410618SOmar.Naji@arm.com    blocked = true;
10510618SOmar.Naji@arm.com    // if we already scheduled a retry in this cycle, but it has not yet
10610618SOmar.Naji@arm.com    // happened, cancel it
10710432SOmar.Naji@arm.com    if (sendRetryEvent.scheduled()) {
10810246Sandreas.hansson@arm.com        owner.deschedule(sendRetryEvent);
10910618SOmar.Naji@arm.com        DPRINTF(CachePort, "Port descheduled retry\n");
11010561SOmar.Naji@arm.com        mustSendRetry = true;
11110561SOmar.Naji@arm.com    }
11210561SOmar.Naji@arm.com}
11310394Swendy.elsasser@arm.com
11410394Swendy.elsasser@arm.comvoid
11510394Swendy.elsasser@arm.comBaseCache::CacheSlavePort::clearBlocked()
11610394Swendy.elsasser@arm.com{
11710394Swendy.elsasser@arm.com    assert(blocked);
11810394Swendy.elsasser@arm.com    DPRINTF(CachePort, "Port is accepting new requests\n");
11910394Swendy.elsasser@arm.com    blocked = false;
12010394Swendy.elsasser@arm.com    if (mustSendRetry) {
12110618SOmar.Naji@arm.com        // @TODO: need to find a better time (next cycle?)
12210394Swendy.elsasser@arm.com        owner.schedule(sendRetryEvent, curTick() + 1);
12310394Swendy.elsasser@arm.com    }
12410618SOmar.Naji@arm.com}
12510394Swendy.elsasser@arm.com
12610246Sandreas.hansson@arm.comvoid
12710246Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry()
12810246Sandreas.hansson@arm.com{
12910140SN/A    DPRINTF(CachePort, "Port is sending retry\n");
13010140SN/A
13110140SN/A    // reset the flag and call retry
13210140SN/A    mustSendRetry = false;
13310140SN/A    sendRetryReq();
1349243SN/A}
1359243SN/A
1369567SN/Avoid
1379243SN/ABaseCache::init()
13810489SOmar.Naji@arm.com{
13910489SOmar.Naji@arm.com    if (!cpuSidePort->isConnected() || !memSidePort->isConnected())
14010489SOmar.Naji@arm.com        fatal("Cache ports on %s are not connected\n", name());
14110489SOmar.Naji@arm.com    cpuSidePort->sendRangeChange();
14210489SOmar.Naji@arm.com    forwardSnoops = cpuSidePort->isSnooping();
14310489SOmar.Naji@arm.com}
14410489SOmar.Naji@arm.com
14510489SOmar.Naji@arm.comBaseMasterPort &
14610489SOmar.Naji@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx)
14710489SOmar.Naji@arm.com{
1489243SN/A    if (if_name == "mem_side") {
1499243SN/A        return *memSidePort;
1509831SN/A    }  else {
1519831SN/A        return MemObject::getMasterPort(if_name, idx);
1529831SN/A    }
1539831SN/A}
1549831SN/A
1559243SN/ABaseSlavePort &
15610286Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx)
1579566SN/A{
1589566SN/A    if (if_name == "cpu_side") {
15910143SN/A        return *cpuSidePort;
1609566SN/A    } else {
1619566SN/A        return MemObject::getSlavePort(if_name, idx);
16210136SN/A    }
1639831SN/A}
16410286Sandreas.hansson@arm.com
16510136SN/Abool
1669566SN/ABaseCache::inRange(Addr addr) const
16710286Sandreas.hansson@arm.com{
16810286Sandreas.hansson@arm.com    for (const auto& r : addrRanges) {
16910286Sandreas.hansson@arm.com        if (r.contains(addr)) {
17010286Sandreas.hansson@arm.com            return true;
17110286Sandreas.hansson@arm.com       }
17210286Sandreas.hansson@arm.com    }
17310286Sandreas.hansson@arm.com    return false;
17410286Sandreas.hansson@arm.com}
17510286Sandreas.hansson@arm.com
17610286Sandreas.hansson@arm.comvoid
17710286Sandreas.hansson@arm.comBaseCache::regStats()
17810286Sandreas.hansson@arm.com{
17910286Sandreas.hansson@arm.com    using namespace Stats;
18010286Sandreas.hansson@arm.com
18110286Sandreas.hansson@arm.com    // Hit statistics
18210286Sandreas.hansson@arm.com    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
1839669SN/A        MemCmd cmd(access_idx);
18410286Sandreas.hansson@arm.com        const string &cstr = cmd.toString();
18510286Sandreas.hansson@arm.com
18610286Sandreas.hansson@arm.com        hits[access_idx]
18710286Sandreas.hansson@arm.com            .init(system->maxMasters())
18810286Sandreas.hansson@arm.com            .name(name() + "." + cstr + "_hits")
18910286Sandreas.hansson@arm.com            .desc("number of " + cstr + " hits")
19010286Sandreas.hansson@arm.com            .flags(total | nozero | nonan)
19110286Sandreas.hansson@arm.com            ;
1929566SN/A        for (int i = 0; i < system->maxMasters(); i++) {
1939566SN/A            hits[access_idx].subname(i, system->getMasterName(i));
19410207Sandreas.hansson@arm.com        }
19510207Sandreas.hansson@arm.com    }
19610207Sandreas.hansson@arm.com
19710207Sandreas.hansson@arm.com// These macros make it easier to sum the right subset of commands and
19810207Sandreas.hansson@arm.com// to change the subset of commands that are considered "demand" vs
19910207Sandreas.hansson@arm.com// "non-demand"
20010394Swendy.elsasser@arm.com#define SUM_DEMAND(s) \
20110394Swendy.elsasser@arm.com    (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::WriteLineReq] + \
20210394Swendy.elsasser@arm.com     s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq])
20310394Swendy.elsasser@arm.com
20410394Swendy.elsasser@arm.com// should writebacks be included here?  prior code was inconsistent...
20510394Swendy.elsasser@arm.com#define SUM_NON_DEMAND(s) \
20610394Swendy.elsasser@arm.com    (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq])
20710394Swendy.elsasser@arm.com
20810394Swendy.elsasser@arm.com    demandHits
20910394Swendy.elsasser@arm.com        .name(name() + ".demand_hits")
21010394Swendy.elsasser@arm.com        .desc("number of demand (read+write) hits")
21110394Swendy.elsasser@arm.com        .flags(total | nozero | nonan)
21210394Swendy.elsasser@arm.com        ;
21310394Swendy.elsasser@arm.com    demandHits = SUM_DEMAND(hits);
21410394Swendy.elsasser@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
21510394Swendy.elsasser@arm.com        demandHits.subname(i, system->getMasterName(i));
21610394Swendy.elsasser@arm.com    }
21710394Swendy.elsasser@arm.com
21810394Swendy.elsasser@arm.com    overallHits
21910394Swendy.elsasser@arm.com        .name(name() + ".overall_hits")
22010394Swendy.elsasser@arm.com        .desc("number of overall hits")
22110394Swendy.elsasser@arm.com        .flags(total | nozero | nonan)
22210561SOmar.Naji@arm.com        ;
22310561SOmar.Naji@arm.com    overallHits = demandHits + SUM_NON_DEMAND(hits);
22410394Swendy.elsasser@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
22510394Swendy.elsasser@arm.com        overallHits.subname(i, system->getMasterName(i));
22610394Swendy.elsasser@arm.com    }
22710394Swendy.elsasser@arm.com
22810394Swendy.elsasser@arm.com    // Miss statistics
22910394Swendy.elsasser@arm.com    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2309243SN/A        MemCmd cmd(access_idx);
2319243SN/A        const string &cstr = cmd.toString();
2329243SN/A
23310146Sandreas.hansson@arm.com        misses[access_idx]
23410140SN/A            .init(system->maxMasters())
23510466Sandreas.hansson@arm.com            .name(name() + "." + cstr + "_misses")
23610466Sandreas.hansson@arm.com            .desc("number of " + cstr + " misses")
23710466Sandreas.hansson@arm.com            .flags(total | nozero | nonan)
23810146Sandreas.hansson@arm.com            ;
23910140SN/A        for (int i = 0; i < system->maxMasters(); i++) {
24010140SN/A            misses[access_idx].subname(i, system->getMasterName(i));
24110140SN/A        }
24210140SN/A    }
24310140SN/A
24410140SN/A    demandMisses
24510146Sandreas.hansson@arm.com        .name(name() + ".demand_misses")
2469243SN/A        .desc("number of demand (read+write) misses")
24710619Sandreas.hansson@arm.com        .flags(total | nozero | nonan)
24810619Sandreas.hansson@arm.com        ;
24910618SOmar.Naji@arm.com    demandMisses = SUM_DEMAND(misses);
25010619Sandreas.hansson@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
25110619Sandreas.hansson@arm.com        demandMisses.subname(i, system->getMasterName(i));
25210619Sandreas.hansson@arm.com    }
25310619Sandreas.hansson@arm.com
25410619Sandreas.hansson@arm.com    overallMisses
25510619Sandreas.hansson@arm.com        .name(name() + ".overall_misses")
25610619Sandreas.hansson@arm.com        .desc("number of overall misses")
25710619Sandreas.hansson@arm.com        .flags(total | nozero | nonan)
25810619Sandreas.hansson@arm.com        ;
25910619Sandreas.hansson@arm.com    overallMisses = demandMisses + SUM_NON_DEMAND(misses);
26010619Sandreas.hansson@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
26110619Sandreas.hansson@arm.com        overallMisses.subname(i, system->getMasterName(i));
26210619Sandreas.hansson@arm.com    }
26310619Sandreas.hansson@arm.com
26410619Sandreas.hansson@arm.com    // Miss latency statistics
26510618SOmar.Naji@arm.com    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
2669243SN/A        MemCmd cmd(access_idx);
2679243SN/A        const string &cstr = cmd.toString();
2689243SN/A
26910146Sandreas.hansson@arm.com        missLatency[access_idx]
2709243SN/A            .init(system->maxMasters())
2719243SN/A            .name(name() + "." + cstr + "_miss_latency")
2729243SN/A            .desc("number of " + cstr + " miss cycles")
2739243SN/A            .flags(total | nozero | nonan)
2749243SN/A            ;
2759243SN/A        for (int i = 0; i < system->maxMasters(); i++) {
2769243SN/A            missLatency[access_idx].subname(i, system->getMasterName(i));
2779243SN/A        }
2789243SN/A    }
2799243SN/A
2809243SN/A    demandMissLatency
2819243SN/A        .name(name() + ".demand_miss_latency")
2829243SN/A        .desc("number of demand (read+write) miss cycles")
2839243SN/A        .flags(total | nozero | nonan)
2849243SN/A        ;
2859243SN/A    demandMissLatency = SUM_DEMAND(missLatency);
28610146Sandreas.hansson@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
2879243SN/A        demandMissLatency.subname(i, system->getMasterName(i));
2889831SN/A    }
2899831SN/A
2909831SN/A    overallMissLatency
2919243SN/A        .name(name() + ".overall_miss_latency")
2929831SN/A        .desc("number of overall miss cycles")
2939831SN/A        .flags(total | nozero | nonan)
2949243SN/A        ;
2959243SN/A    overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency);
2969243SN/A    for (int i = 0; i < system->maxMasters(); i++) {
29710146Sandreas.hansson@arm.com        overallMissLatency.subname(i, system->getMasterName(i));
2989243SN/A    }
2999831SN/A
3009831SN/A    // access formulas
3019831SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
3029243SN/A        MemCmd cmd(access_idx);
3039243SN/A        const string &cstr = cmd.toString();
30410146Sandreas.hansson@arm.com
30510146Sandreas.hansson@arm.com        accesses[access_idx]
30610143SN/A            .name(name() + "." + cstr + "_accesses")
3079243SN/A            .desc("number of " + cstr + " accesses(hits+misses)")
3089669SN/A            .flags(total | nozero | nonan)
30910136SN/A            ;
31010136SN/A        accesses[access_idx] = hits[access_idx] + misses[access_idx];
3119243SN/A
3129967SN/A        for (int i = 0; i < system->maxMasters(); i++) {
31310245Sandreas.hansson@arm.com            accesses[access_idx].subname(i, system->getMasterName(i));
31410245Sandreas.hansson@arm.com        }
31510245Sandreas.hansson@arm.com    }
3169243SN/A
31710286Sandreas.hansson@arm.com    demandAccesses
31810286Sandreas.hansson@arm.com        .name(name() + ".demand_accesses")
3199831SN/A        .desc("number of demand (read+write) accesses")
3209243SN/A        .flags(total | nozero | nonan)
3219491SN/A        ;
3229831SN/A    demandAccesses = demandHits + demandMisses;
32310136SN/A    for (int i = 0; i < system->maxMasters(); i++) {
3249491SN/A        demandAccesses.subname(i, system->getMasterName(i));
3259491SN/A    }
3269831SN/A
3279243SN/A    overallAccesses
3289669SN/A        .name(name() + ".overall_accesses")
3299566SN/A        .desc("number of overall (read+write) accesses")
3309566SN/A        .flags(total | nozero | nonan)
3319669SN/A        ;
3329669SN/A    overallAccesses = overallHits + overallMisses;
3339669SN/A    for (int i = 0; i < system->maxMasters(); i++) {
3349669SN/A        overallAccesses.subname(i, system->getMasterName(i));
3359669SN/A    }
3369669SN/A
3379669SN/A    // miss rate formulas
3389669SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
3399669SN/A        MemCmd cmd(access_idx);
3409669SN/A        const string &cstr = cmd.toString();
3419669SN/A
3429669SN/A        missRate[access_idx]
3439669SN/A            .name(name() + "." + cstr + "_miss_rate")
34410136SN/A            .desc("miss rate for " + cstr + " accesses")
34510286Sandreas.hansson@arm.com            .flags(total | nozero | nonan)
34610286Sandreas.hansson@arm.com            ;
34710286Sandreas.hansson@arm.com        missRate[access_idx] = misses[access_idx] / accesses[access_idx];
3489669SN/A
3499669SN/A        for (int i = 0; i < system->maxMasters(); i++) {
3509669SN/A            missRate[access_idx].subname(i, system->getMasterName(i));
35110286Sandreas.hansson@arm.com        }
35210286Sandreas.hansson@arm.com    }
3539669SN/A
3549669SN/A    demandMissRate
3559491SN/A        .name(name() + ".demand_miss_rate")
3569243SN/A        .desc("miss rate for demand accesses")
3579243SN/A        .flags(total | nozero | nonan)
3589243SN/A        ;
3599491SN/A    demandMissRate = demandMisses / demandAccesses;
3609491SN/A    for (int i = 0; i < system->maxMasters(); i++) {
3619243SN/A        demandMissRate.subname(i, system->getMasterName(i));
3629243SN/A    }
3639243SN/A
3649491SN/A    overallMissRate
3659243SN/A        .name(name() + ".overall_miss_rate")
3669243SN/A        .desc("miss rate for overall accesses")
36710136SN/A        .flags(total | nozero | nonan)
3689491SN/A        ;
3699491SN/A    overallMissRate = overallMisses / overallAccesses;
3709491SN/A    for (int i = 0; i < system->maxMasters(); i++) {
37110286Sandreas.hansson@arm.com        overallMissRate.subname(i, system->getMasterName(i));
37210286Sandreas.hansson@arm.com    }
37310286Sandreas.hansson@arm.com
3749566SN/A    // miss latency formulas
3759566SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
3769566SN/A        MemCmd cmd(access_idx);
3779566SN/A        const string &cstr = cmd.toString();
3789566SN/A
3799491SN/A        avgMissLatency[access_idx]
3809491SN/A            .name(name() + "." + cstr + "_avg_miss_latency")
3819243SN/A            .desc("average " + cstr + " miss latency")
3829243SN/A            .flags(total | nozero | nonan)
3839243SN/A            ;
3849491SN/A        avgMissLatency[access_idx] =
3859243SN/A            missLatency[access_idx] / misses[access_idx];
3869243SN/A
3879243SN/A        for (int i = 0; i < system->maxMasters(); i++) {
38810286Sandreas.hansson@arm.com            avgMissLatency[access_idx].subname(i, system->getMasterName(i));
38910286Sandreas.hansson@arm.com        }
3909243SN/A    }
3919491SN/A
3929243SN/A    demandAvgMissLatency
3939243SN/A        .name(name() + ".demand_avg_miss_latency")
3949243SN/A        .desc("average overall miss latency")
3959243SN/A        .flags(total | nozero | nonan)
3969243SN/A        ;
3979243SN/A    demandAvgMissLatency = demandMissLatency / demandMisses;
3989243SN/A    for (int i = 0; i < system->maxMasters(); i++) {
3999243SN/A        demandAvgMissLatency.subname(i, system->getMasterName(i));
40010245Sandreas.hansson@arm.com    }
4019243SN/A
4029243SN/A    overallAvgMissLatency
4039831SN/A        .name(name() + ".overall_avg_miss_latency")
4049243SN/A        .desc("average overall miss latency")
4059243SN/A        .flags(total | nozero | nonan)
4069567SN/A        ;
4079567SN/A    overallAvgMissLatency = overallMissLatency / overallMisses;
4089967SN/A    for (int i = 0; i < system->maxMasters(); i++) {
4099967SN/A        overallAvgMissLatency.subname(i, system->getMasterName(i));
41010618SOmar.Naji@arm.com    }
4119243SN/A
4129243SN/A    blocked_cycles.init(NUM_BLOCKED_CAUSES);
4139243SN/A    blocked_cycles
41410146Sandreas.hansson@arm.com        .name(name() + ".blocked_cycles")
4159243SN/A        .desc("number of cycles access was blocked")
4169243SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
4179243SN/A        .subname(Blocked_NoTargets, "no_targets")
4189243SN/A        ;
4199243SN/A
4209831SN/A
4219831SN/A    blocked_causes.init(NUM_BLOCKED_CAUSES);
4229831SN/A    blocked_causes
4239831SN/A        .name(name() + ".blocked")
4249831SN/A        .desc("number of cycles access was blocked")
4259831SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
4269831SN/A        .subname(Blocked_NoTargets, "no_targets")
4279831SN/A        ;
4289243SN/A
4299831SN/A    avg_blocked
4309831SN/A        .name(name() + ".avg_blocked_cycles")
4319831SN/A        .desc("average number of cycles each access was blocked")
4329831SN/A        .subname(Blocked_NoMSHRs, "no_mshrs")
4339831SN/A        .subname(Blocked_NoTargets, "no_targets")
4349831SN/A        ;
4359831SN/A
4369243SN/A    avg_blocked = blocked_cycles / blocked_causes;
4379831SN/A
4389831SN/A    unusedPrefetches
4399831SN/A        .name(name() + ".unused_prefetches")
4409833SN/A        .desc("number of HardPF blocks evicted w/o reference")
4419832SN/A        .flags(nozero)
4429832SN/A        ;
4439832SN/A
4449832SN/A    writebacks
4459831SN/A        .init(system->maxMasters())
4469831SN/A        .name(name() + ".writebacks")
4479831SN/A        .desc("number of writebacks")
4489831SN/A        .flags(total | nozero | nonan)
4499831SN/A        ;
4509975SN/A    for (int i = 0; i < system->maxMasters(); i++) {
4519831SN/A        writebacks.subname(i, system->getMasterName(i));
4529831SN/A    }
4539243SN/A
4549831SN/A    // MSHR statistics
4559831SN/A    // MSHR hit statistics
4569831SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
4579831SN/A        MemCmd cmd(access_idx);
4589831SN/A        const string &cstr = cmd.toString();
4599831SN/A
4609831SN/A        mshr_hits[access_idx]
4619831SN/A            .init(system->maxMasters())
4629831SN/A            .name(name() + "." + cstr + "_mshr_hits")
4639831SN/A            .desc("number of " + cstr + " MSHR hits")
4649831SN/A            .flags(total | nozero | nonan)
4659831SN/A            ;
4669966SN/A        for (int i = 0; i < system->maxMasters(); i++) {
4679831SN/A            mshr_hits[access_idx].subname(i, system->getMasterName(i));
4689831SN/A        }
4699831SN/A    }
4709831SN/A
4719831SN/A    demandMshrHits
4729831SN/A        .name(name() + ".demand_mshr_hits")
4739831SN/A        .desc("number of demand (read+write) MSHR hits")
4749831SN/A        .flags(total | nozero | nonan)
4759831SN/A        ;
4769831SN/A    demandMshrHits = SUM_DEMAND(mshr_hits);
4779831SN/A    for (int i = 0; i < system->maxMasters(); i++) {
4789831SN/A        demandMshrHits.subname(i, system->getMasterName(i));
4799831SN/A    }
4809831SN/A
4819831SN/A    overallMshrHits
4829243SN/A        .name(name() + ".overall_mshr_hits")
4839243SN/A        .desc("number of overall MSHR hits")
4849831SN/A        .flags(total | nozero | nonan)
4859831SN/A        ;
4869831SN/A    overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits);
4879831SN/A    for (int i = 0; i < system->maxMasters(); i++) {
4889831SN/A        overallMshrHits.subname(i, system->getMasterName(i));
4899243SN/A    }
4909831SN/A
4919831SN/A    // MSHR miss statistics
4929831SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
4939243SN/A        MemCmd cmd(access_idx);
49410206Sandreas.hansson@arm.com        const string &cstr = cmd.toString();
49510206Sandreas.hansson@arm.com
49610206Sandreas.hansson@arm.com        mshr_misses[access_idx]
4979567SN/A            .init(system->maxMasters())
4989567SN/A            .name(name() + "." + cstr + "_mshr_misses")
4999243SN/A            .desc("number of " + cstr + " MSHR misses")
5009243SN/A            .flags(total | nozero | nonan)
5019243SN/A            ;
5029243SN/A        for (int i = 0; i < system->maxMasters(); i++) {
50310146Sandreas.hansson@arm.com            mshr_misses[access_idx].subname(i, system->getMasterName(i));
5049243SN/A        }
5059243SN/A    }
5069243SN/A
5079243SN/A    demandMshrMisses
5089243SN/A        .name(name() + ".demand_mshr_misses")
5099831SN/A        .desc("number of demand (read+write) MSHR misses")
5109831SN/A        .flags(total | nozero | nonan)
5119831SN/A        ;
5129831SN/A    demandMshrMisses = SUM_DEMAND(mshr_misses);
5139831SN/A    for (int i = 0; i < system->maxMasters(); i++) {
5149831SN/A        demandMshrMisses.subname(i, system->getMasterName(i));
5159831SN/A    }
5169831SN/A
5179243SN/A    overallMshrMisses
5189832SN/A        .name(name() + ".overall_mshr_misses")
5199838SN/A        .desc("number of overall MSHR misses")
5209838SN/A        .flags(total | nozero | nonan)
5219838SN/A        ;
5229832SN/A    overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses);
5239832SN/A    for (int i = 0; i < system->maxMasters(); i++) {
5249243SN/A        overallMshrMisses.subname(i, system->getMasterName(i));
5259832SN/A    }
5269832SN/A
5279832SN/A    // MSHR miss latency statistics
5289832SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5299838SN/A        MemCmd cmd(access_idx);
5309838SN/A        const string &cstr = cmd.toString();
5319838SN/A
5329832SN/A        mshr_miss_latency[access_idx]
5339832SN/A            .init(system->maxMasters())
5349832SN/A            .name(name() + "." + cstr + "_mshr_miss_latency")
5359832SN/A            .desc("number of " + cstr + " MSHR miss cycles")
5369832SN/A            .flags(total | nozero | nonan)
5379832SN/A            ;
5389832SN/A        for (int i = 0; i < system->maxMasters(); i++) {
5399832SN/A            mshr_miss_latency[access_idx].subname(i, system->getMasterName(i));
5409832SN/A        }
5419832SN/A    }
5429832SN/A
5439832SN/A    demandMshrMissLatency
5449832SN/A        .name(name() + ".demand_mshr_miss_latency")
5459832SN/A        .desc("number of demand (read+write) MSHR miss cycles")
5469832SN/A        .flags(total | nozero | nonan)
5479832SN/A        ;
5489832SN/A    demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency);
54910047SN/A    for (int i = 0; i < system->maxMasters(); i++) {
5509832SN/A        demandMshrMissLatency.subname(i, system->getMasterName(i));
5519832SN/A    }
5529832SN/A
5539838SN/A    overallMshrMissLatency
5549838SN/A        .name(name() + ".overall_mshr_miss_latency")
5559838SN/A        .desc("number of overall MSHR miss cycles")
5569832SN/A        .flags(total | nozero | nonan)
5579832SN/A        ;
5589832SN/A    overallMshrMissLatency =
5599832SN/A        demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency);
5609832SN/A    for (int i = 0; i < system->maxMasters(); i++) {
5619832SN/A        overallMshrMissLatency.subname(i, system->getMasterName(i));
5629832SN/A    }
5639832SN/A
5649832SN/A    // MSHR uncacheable statistics
5659832SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5669832SN/A        MemCmd cmd(access_idx);
5679832SN/A        const string &cstr = cmd.toString();
5689832SN/A
5699832SN/A        mshr_uncacheable[access_idx]
5709832SN/A            .init(system->maxMasters())
5719832SN/A            .name(name() + "." + cstr + "_mshr_uncacheable")
5729832SN/A            .desc("number of " + cstr + " MSHR uncacheable")
5739832SN/A            .flags(total | nozero | nonan)
5749832SN/A            ;
5759832SN/A        for (int i = 0; i < system->maxMasters(); i++) {
5769243SN/A            mshr_uncacheable[access_idx].subname(i, system->getMasterName(i));
5779832SN/A        }
5789832SN/A    }
5799832SN/A
5809966SN/A    overallMshrUncacheable
5819243SN/A        .name(name() + ".overall_mshr_uncacheable_misses")
5829832SN/A        .desc("number of overall MSHR uncacheable misses")
5839832SN/A        .flags(total | nozero | nonan)
5849243SN/A        ;
5859832SN/A    overallMshrUncacheable =
5869831SN/A        SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable);
5879832SN/A    for (int i = 0; i < system->maxMasters(); i++) {
5889831SN/A        overallMshrUncacheable.subname(i, system->getMasterName(i));
5899832SN/A    }
5909832SN/A
5919977SN/A    // MSHR miss latency statistics
5929977SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
5939977SN/A        MemCmd cmd(access_idx);
5949977SN/A        const string &cstr = cmd.toString();
5959832SN/A
5969832SN/A        mshr_uncacheable_lat[access_idx]
5979831SN/A            .init(system->maxMasters())
5989831SN/A            .name(name() + "." + cstr + "_mshr_uncacheable_latency")
5999831SN/A            .desc("number of " + cstr + " MSHR uncacheable cycles")
6009243SN/A            .flags(total | nozero | nonan)
6019243SN/A            ;
6029243SN/A        for (int i = 0; i < system->maxMasters(); i++) {
6039243SN/A            mshr_uncacheable_lat[access_idx].subname(
6049831SN/A                i, system->getMasterName(i));
6059831SN/A        }
6069726SN/A    }
6079243SN/A
60810206Sandreas.hansson@arm.com    overallMshrUncacheableLatency
60910206Sandreas.hansson@arm.com        .name(name() + ".overall_mshr_uncacheable_latency")
61010206Sandreas.hansson@arm.com        .desc("number of overall MSHR uncacheable cycles")
61110206Sandreas.hansson@arm.com        .flags(total | nozero | nonan)
61210206Sandreas.hansson@arm.com        ;
6139243SN/A    overallMshrUncacheableLatency =
6149243SN/A        SUM_DEMAND(mshr_uncacheable_lat) +
6159243SN/A        SUM_NON_DEMAND(mshr_uncacheable_lat);
6169243SN/A    for (int i = 0; i < system->maxMasters(); i++) {
61710146Sandreas.hansson@arm.com        overallMshrUncacheableLatency.subname(i, system->getMasterName(i));
6189243SN/A    }
6199833SN/A
6209243SN/A#if 0
6219243SN/A    // MSHR access formulas
6229243SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6239833SN/A        MemCmd cmd(access_idx);
6249243SN/A        const string &cstr = cmd.toString();
6259243SN/A
6269243SN/A        mshrAccesses[access_idx]
6279833SN/A            .name(name() + "." + cstr + "_mshr_accesses")
6289243SN/A            .desc("number of " + cstr + " mshr accesses(hits+misses)")
6299243SN/A            .flags(total | nozero | nonan)
6309243SN/A            ;
6319243SN/A        mshrAccesses[access_idx] =
6329243SN/A            mshr_hits[access_idx] + mshr_misses[access_idx]
63310146Sandreas.hansson@arm.com            + mshr_uncacheable[access_idx];
6349243SN/A    }
6359349SN/A
6369349SN/A    demandMshrAccesses
6379349SN/A        .name(name() + ".demand_mshr_accesses")
6389349SN/A        .desc("number of demand (read+write) mshr accesses")
6399349SN/A        .flags(total | nozero | nonan)
6409349SN/A        ;
6419243SN/A    demandMshrAccesses = demandMshrHits + demandMshrMisses;
6429567SN/A
6439831SN/A    overallMshrAccesses
6449243SN/A        .name(name() + ".overall_mshr_accesses")
6459567SN/A        .desc("number of overall (read+write) mshr accesses")
6469567SN/A        .flags(total | nozero | nonan)
64710143SN/A        ;
6489567SN/A    overallMshrAccesses = overallMshrHits + overallMshrMisses
6499567SN/A        + overallMshrUncacheable;
6509567SN/A#endif
6519243SN/A
6529243SN/A    // MSHR miss rate formulas
6539243SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6549243SN/A        MemCmd cmd(access_idx);
6559243SN/A        const string &cstr = cmd.toString();
6569243SN/A
6579243SN/A        mshrMissRate[access_idx]
6589831SN/A            .name(name() + "." + cstr + "_mshr_miss_rate")
6599831SN/A            .desc("mshr miss rate for " + cstr + " accesses")
6609831SN/A            .flags(total | nozero | nonan)
6619831SN/A            ;
6629831SN/A        mshrMissRate[access_idx] =
6639243SN/A            mshr_misses[access_idx] / accesses[access_idx];
6649831SN/A
6659831SN/A        for (int i = 0; i < system->maxMasters(); i++) {
6669243SN/A            mshrMissRate[access_idx].subname(i, system->getMasterName(i));
6679243SN/A        }
6689243SN/A    }
6699567SN/A
6709831SN/A    demandMshrMissRate
6719567SN/A        .name(name() + ".demand_mshr_miss_rate")
6729243SN/A        .desc("mshr miss rate for demand accesses")
6739243SN/A        .flags(total | nozero | nonan)
6749243SN/A        ;
6759243SN/A    demandMshrMissRate = demandMshrMisses / demandAccesses;
6769243SN/A    for (int i = 0; i < system->maxMasters(); i++) {
6779831SN/A        demandMshrMissRate.subname(i, system->getMasterName(i));
6789243SN/A    }
6799977SN/A
6809243SN/A    overallMshrMissRate
6819243SN/A        .name(name() + ".overall_mshr_miss_rate")
6829567SN/A        .desc("mshr miss rate for overall accesses")
6839831SN/A        .flags(total | nozero | nonan)
6849567SN/A        ;
6859243SN/A    overallMshrMissRate = overallMshrMisses / overallAccesses;
6869243SN/A    for (int i = 0; i < system->maxMasters(); i++) {
6879243SN/A        overallMshrMissRate.subname(i, system->getMasterName(i));
6889243SN/A    }
6899243SN/A
6909831SN/A    // mshrMiss latency formulas
6919243SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
6929977SN/A        MemCmd cmd(access_idx);
6939243SN/A        const string &cstr = cmd.toString();
6949243SN/A
6959243SN/A        avgMshrMissLatency[access_idx]
6969243SN/A            .name(name() + "." + cstr + "_avg_mshr_miss_latency")
6979726SN/A            .desc("average " + cstr + " mshr miss latency")
6989243SN/A            .flags(total | nozero | nonan)
6999243SN/A            ;
7009243SN/A        avgMshrMissLatency[access_idx] =
7019243SN/A            mshr_miss_latency[access_idx] / mshr_misses[access_idx];
7029243SN/A
7039243SN/A        for (int i = 0; i < system->maxMasters(); i++) {
70410146Sandreas.hansson@arm.com            avgMshrMissLatency[access_idx].subname(
7059243SN/A                i, system->getMasterName(i));
7069243SN/A        }
7079243SN/A    }
7089243SN/A
7099831SN/A    demandAvgMshrMissLatency
7109243SN/A        .name(name() + ".demand_avg_mshr_miss_latency")
7119831SN/A        .desc("average overall mshr miss latency")
7129831SN/A        .flags(total | nozero | nonan)
7139831SN/A        ;
7149831SN/A    demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses;
71510143SN/A    for (int i = 0; i < system->maxMasters(); i++) {
7169831SN/A        demandAvgMshrMissLatency.subname(i, system->getMasterName(i));
7179831SN/A    }
7189831SN/A
7199831SN/A    overallAvgMshrMissLatency
7209831SN/A        .name(name() + ".overall_avg_mshr_miss_latency")
7219831SN/A        .desc("average overall mshr miss latency")
7229831SN/A        .flags(total | nozero | nonan)
7239831SN/A        ;
7249831SN/A    overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses;
7259831SN/A    for (int i = 0; i < system->maxMasters(); i++) {
7269831SN/A        overallAvgMshrMissLatency.subname(i, system->getMasterName(i));
7279831SN/A    }
7289243SN/A
7299831SN/A    // mshrUncacheable latency formulas
7309831SN/A    for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) {
7319243SN/A        MemCmd cmd(access_idx);
7329831SN/A        const string &cstr = cmd.toString();
7339831SN/A
7349831SN/A        avgMshrUncacheableLatency[access_idx]
7359831SN/A            .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency")
7369831SN/A            .desc("average " + cstr + " mshr uncacheable latency")
7379831SN/A            .flags(total | nozero | nonan)
7389831SN/A            ;
7399831SN/A        avgMshrUncacheableLatency[access_idx] =
74010509SAli.Saidi@ARM.com            mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx];
7419831SN/A
7429831SN/A        for (int i = 0; i < system->maxMasters(); i++) {
7439831SN/A            avgMshrUncacheableLatency[access_idx].subname(
7449831SN/A                i, system->getMasterName(i));
7459567SN/A        }
7469831SN/A    }
7479831SN/A
7489831SN/A    overallAvgMshrUncacheableLatency
7499831SN/A        .name(name() + ".overall_avg_mshr_uncacheable_latency")
7509831SN/A        .desc("average overall mshr uncacheable latency")
7519831SN/A        .flags(total | nozero | nonan)
7529243SN/A        ;
7539243SN/A    overallAvgMshrUncacheableLatency =
75410618SOmar.Naji@arm.com        overallMshrUncacheableLatency / overallMshrUncacheable;
75510393Swendy.elsasser@arm.com    for (int i = 0; i < system->maxMasters(); i++) {
7569243SN/A        overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i));
75710206Sandreas.hansson@arm.com    }
75810206Sandreas.hansson@arm.com
75910206Sandreas.hansson@arm.com}
76010206Sandreas.hansson@arm.com