base.cc revision 11377
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 6811053Sandreas.hansson@arm.comBaseCache::BaseCache(const BaseCacheParams *p, unsigned blk_size) 695034SN/A : MemObject(p), 7010360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7111377Sandreas.hansson@arm.com mshrQueue("MSHRs", p->mshrs, 0, p->demand_mshr_reserve), // see below 7211377Sandreas.hansson@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs), // see below 7311053Sandreas.hansson@arm.com blkSize(blk_size), 7410693SMarco.Balboni@ARM.com lookupLatency(p->hit_latency), 7510693SMarco.Balboni@ARM.com forwardLatency(p->hit_latency), 7610693SMarco.Balboni@ARM.com fillLatency(p->response_latency), 779263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 785034SN/A numTarget(p->tgts_per_mshr), 7911331Sandreas.hansson@arm.com forwardSnoops(true), 8010884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 814626SN/A blocked(0), 8210360Sandreas.hansson@arm.com order(0), 834626SN/A noTargetMSHR(NULL), 845034SN/A missCount(p->max_miss_count), 858883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 868833Sdam.sunwoo@arm.com system(p->system) 874458SN/A{ 8811377Sandreas.hansson@arm.com // the MSHR queue has no reserve entries as we check the MSHR 8911377Sandreas.hansson@arm.com // queue on every single allocation, whereas the write queue has 9011377Sandreas.hansson@arm.com // as many reserve entries as we have MSHRs, since every MSHR may 9111377Sandreas.hansson@arm.com // eventually require a writeback, and we do not check the write 9211377Sandreas.hansson@arm.com // buffer before committing to an MSHR 9311377Sandreas.hansson@arm.com 9411331Sandreas.hansson@arm.com // forward snoops is overridden in init() once we can query 9511331Sandreas.hansson@arm.com // whether the connected master is actually snooping or not 962810SN/A} 972810SN/A 983013SN/Avoid 998856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 1002810SN/A{ 1013013SN/A assert(!blocked); 10210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 1032810SN/A blocked = true; 1049614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 1059614Srene.dejong@arm.com // happened, cancel it 1069614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 10710345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 10810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 10910345SCurtis.Dunham@arm.com mustSendRetry = true; 1109614Srene.dejong@arm.com } 1112810SN/A} 1122810SN/A 1132810SN/Avoid 1148856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1152810SN/A{ 1163013SN/A assert(blocked); 11710714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1183013SN/A blocked = false; 1198856Sandreas.hansson@arm.com if (mustSendRetry) { 12010714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1218922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1222897SN/A } 1232810SN/A} 1242810SN/A 12510344Sandreas.hansson@arm.comvoid 12610344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 12710344Sandreas.hansson@arm.com{ 12810714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 12910344Sandreas.hansson@arm.com 13010344Sandreas.hansson@arm.com // reset the flag and call retry 13110344Sandreas.hansson@arm.com mustSendRetry = false; 13210713Sandreas.hansson@arm.com sendRetryReq(); 13310344Sandreas.hansson@arm.com} 1342844SN/A 1352810SN/Avoid 1362858SN/ABaseCache::init() 1372858SN/A{ 1388856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1398922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1408711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 14111331Sandreas.hansson@arm.com forwardSnoops = cpuSidePort->isSnooping(); 1422858SN/A} 1432858SN/A 1449294Sandreas.hansson@arm.comBaseMasterPort & 1459294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1468922Swilliam.wang@arm.com{ 1478922Swilliam.wang@arm.com if (if_name == "mem_side") { 1488922Swilliam.wang@arm.com return *memSidePort; 1498922Swilliam.wang@arm.com } else { 1508922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1518922Swilliam.wang@arm.com } 1528922Swilliam.wang@arm.com} 1538922Swilliam.wang@arm.com 1549294Sandreas.hansson@arm.comBaseSlavePort & 1559294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1568922Swilliam.wang@arm.com{ 1578922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1588922Swilliam.wang@arm.com return *cpuSidePort; 1598922Swilliam.wang@arm.com } else { 1608922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1618922Swilliam.wang@arm.com } 1628922Swilliam.wang@arm.com} 1634628SN/A 16410821Sandreas.hansson@arm.combool 16510821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 16610821Sandreas.hansson@arm.com{ 16710821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 16810821Sandreas.hansson@arm.com if (r.contains(addr)) { 16910821Sandreas.hansson@arm.com return true; 17010821Sandreas.hansson@arm.com } 17110821Sandreas.hansson@arm.com } 17210821Sandreas.hansson@arm.com return false; 17310821Sandreas.hansson@arm.com} 17410821Sandreas.hansson@arm.com 1752858SN/Avoid 1762810SN/ABaseCache::regStats() 1772810SN/A{ 1782810SN/A using namespace Stats; 1792810SN/A 1802810SN/A // Hit statistics 1814022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1824022SN/A MemCmd cmd(access_idx); 1834022SN/A const string &cstr = cmd.toString(); 1842810SN/A 1852810SN/A hits[access_idx] 1868833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1872810SN/A .name(name() + "." + cstr + "_hits") 1882810SN/A .desc("number of " + cstr + " hits") 1892810SN/A .flags(total | nozero | nonan) 1902810SN/A ; 1918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1928833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1938833Sdam.sunwoo@arm.com } 1942810SN/A } 1952810SN/A 1964871SN/A// These macros make it easier to sum the right subset of commands and 1974871SN/A// to change the subset of commands that are considered "demand" vs 1984871SN/A// "non-demand" 1994871SN/A#define SUM_DEMAND(s) \ 20010885Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + \ 20110885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 2024871SN/A 2034871SN/A// should writebacks be included here? prior code was inconsistent... 2044871SN/A#define SUM_NON_DEMAND(s) \ 2054871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 2064871SN/A 2072810SN/A demandHits 2082810SN/A .name(name() + ".demand_hits") 2092810SN/A .desc("number of demand (read+write) hits") 2108833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2112810SN/A ; 2124871SN/A demandHits = SUM_DEMAND(hits); 2138833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2148833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 2158833Sdam.sunwoo@arm.com } 2162810SN/A 2172810SN/A overallHits 2182810SN/A .name(name() + ".overall_hits") 2192810SN/A .desc("number of overall hits") 2208833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2212810SN/A ; 2224871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2248833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2258833Sdam.sunwoo@arm.com } 2262810SN/A 2272810SN/A // Miss statistics 2284022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2294022SN/A MemCmd cmd(access_idx); 2304022SN/A const string &cstr = cmd.toString(); 2312810SN/A 2322810SN/A misses[access_idx] 2338833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2342810SN/A .name(name() + "." + cstr + "_misses") 2352810SN/A .desc("number of " + cstr + " misses") 2362810SN/A .flags(total | nozero | nonan) 2372810SN/A ; 2388833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2398833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2408833Sdam.sunwoo@arm.com } 2412810SN/A } 2422810SN/A 2432810SN/A demandMisses 2442810SN/A .name(name() + ".demand_misses") 2452810SN/A .desc("number of demand (read+write) misses") 2468833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2472810SN/A ; 2484871SN/A demandMisses = SUM_DEMAND(misses); 2498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2508833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2518833Sdam.sunwoo@arm.com } 2522810SN/A 2532810SN/A overallMisses 2542810SN/A .name(name() + ".overall_misses") 2552810SN/A .desc("number of overall misses") 2568833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2572810SN/A ; 2584871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2598833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2608833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2618833Sdam.sunwoo@arm.com } 2622810SN/A 2632810SN/A // Miss latency statistics 2644022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2654022SN/A MemCmd cmd(access_idx); 2664022SN/A const string &cstr = cmd.toString(); 2672810SN/A 2682810SN/A missLatency[access_idx] 2698833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2702810SN/A .name(name() + "." + cstr + "_miss_latency") 2712810SN/A .desc("number of " + cstr + " miss cycles") 2722810SN/A .flags(total | nozero | nonan) 2732810SN/A ; 2748833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2758833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2768833Sdam.sunwoo@arm.com } 2772810SN/A } 2782810SN/A 2792810SN/A demandMissLatency 2802810SN/A .name(name() + ".demand_miss_latency") 2812810SN/A .desc("number of demand (read+write) miss cycles") 2828833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2832810SN/A ; 2844871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2868833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2878833Sdam.sunwoo@arm.com } 2882810SN/A 2892810SN/A overallMissLatency 2902810SN/A .name(name() + ".overall_miss_latency") 2912810SN/A .desc("number of overall miss cycles") 2928833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2932810SN/A ; 2944871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2958833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2968833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2978833Sdam.sunwoo@arm.com } 2982810SN/A 2992810SN/A // access formulas 3004022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3014022SN/A MemCmd cmd(access_idx); 3024022SN/A const string &cstr = cmd.toString(); 3032810SN/A 3042810SN/A accesses[access_idx] 3052810SN/A .name(name() + "." + cstr + "_accesses") 3062810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 3072810SN/A .flags(total | nozero | nonan) 3082810SN/A ; 3098833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3102810SN/A 3118833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3128833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 3138833Sdam.sunwoo@arm.com } 3142810SN/A } 3152810SN/A 3162810SN/A demandAccesses 3172810SN/A .name(name() + ".demand_accesses") 3182810SN/A .desc("number of demand (read+write) accesses") 3198833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3202810SN/A ; 3212810SN/A demandAccesses = demandHits + demandMisses; 3228833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3238833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3248833Sdam.sunwoo@arm.com } 3252810SN/A 3262810SN/A overallAccesses 3272810SN/A .name(name() + ".overall_accesses") 3282810SN/A .desc("number of overall (read+write) accesses") 3298833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3302810SN/A ; 3312810SN/A overallAccesses = overallHits + overallMisses; 3328833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3338833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3348833Sdam.sunwoo@arm.com } 3352810SN/A 3362810SN/A // miss rate formulas 3374022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3384022SN/A MemCmd cmd(access_idx); 3394022SN/A const string &cstr = cmd.toString(); 3402810SN/A 3412810SN/A missRate[access_idx] 3422810SN/A .name(name() + "." + cstr + "_miss_rate") 3432810SN/A .desc("miss rate for " + cstr + " accesses") 3442810SN/A .flags(total | nozero | nonan) 3452810SN/A ; 3468833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3472810SN/A 3488833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3498833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3508833Sdam.sunwoo@arm.com } 3512810SN/A } 3522810SN/A 3532810SN/A demandMissRate 3542810SN/A .name(name() + ".demand_miss_rate") 3552810SN/A .desc("miss rate for demand accesses") 3568833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3572810SN/A ; 3582810SN/A demandMissRate = demandMisses / demandAccesses; 3598833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3608833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3618833Sdam.sunwoo@arm.com } 3622810SN/A 3632810SN/A overallMissRate 3642810SN/A .name(name() + ".overall_miss_rate") 3652810SN/A .desc("miss rate for overall accesses") 3668833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3672810SN/A ; 3682810SN/A overallMissRate = overallMisses / overallAccesses; 3698833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3708833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3718833Sdam.sunwoo@arm.com } 3722810SN/A 3732810SN/A // miss latency formulas 3744022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3754022SN/A MemCmd cmd(access_idx); 3764022SN/A const string &cstr = cmd.toString(); 3772810SN/A 3782810SN/A avgMissLatency[access_idx] 3792810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3802810SN/A .desc("average " + cstr + " miss latency") 3812810SN/A .flags(total | nozero | nonan) 3822810SN/A ; 3832810SN/A avgMissLatency[access_idx] = 3842810SN/A missLatency[access_idx] / misses[access_idx]; 3858833Sdam.sunwoo@arm.com 3868833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3878833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3888833Sdam.sunwoo@arm.com } 3892810SN/A } 3902810SN/A 3912810SN/A demandAvgMissLatency 3922810SN/A .name(name() + ".demand_avg_miss_latency") 3932810SN/A .desc("average overall miss latency") 3948833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3952810SN/A ; 3962810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3978833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3988833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3998833Sdam.sunwoo@arm.com } 4002810SN/A 4012810SN/A overallAvgMissLatency 4022810SN/A .name(name() + ".overall_avg_miss_latency") 4032810SN/A .desc("average overall miss latency") 4048833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4052810SN/A ; 4062810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 4078833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4088833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 4098833Sdam.sunwoo@arm.com } 4102810SN/A 4112810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 4122810SN/A blocked_cycles 4132810SN/A .name(name() + ".blocked_cycles") 4142810SN/A .desc("number of cycles access was blocked") 4152810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4162810SN/A .subname(Blocked_NoTargets, "no_targets") 4172810SN/A ; 4182810SN/A 4192810SN/A 4202810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 4212810SN/A blocked_causes 4222810SN/A .name(name() + ".blocked") 4232810SN/A .desc("number of cycles access was blocked") 4242810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4252810SN/A .subname(Blocked_NoTargets, "no_targets") 4262810SN/A ; 4272810SN/A 4282810SN/A avg_blocked 4292810SN/A .name(name() + ".avg_blocked_cycles") 4302810SN/A .desc("average number of cycles each access was blocked") 4312810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4322810SN/A .subname(Blocked_NoTargets, "no_targets") 4332810SN/A ; 4342810SN/A 4352810SN/A avg_blocked = blocked_cycles / blocked_causes; 4362810SN/A 4372810SN/A fastWrites 4382810SN/A .name(name() + ".fast_writes") 4392810SN/A .desc("number of fast writes performed") 4402810SN/A ; 4412810SN/A 4422810SN/A cacheCopies 4432810SN/A .name(name() + ".cache_copies") 4442810SN/A .desc("number of cache copies performed") 4452810SN/A ; 4462826SN/A 4474626SN/A writebacks 4488833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4494626SN/A .name(name() + ".writebacks") 4504626SN/A .desc("number of writebacks") 4518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4524626SN/A ; 4538833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4548833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4558833Sdam.sunwoo@arm.com } 4564626SN/A 4574626SN/A // MSHR statistics 4584626SN/A // MSHR hit statistics 4594626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4604626SN/A MemCmd cmd(access_idx); 4614626SN/A const string &cstr = cmd.toString(); 4624626SN/A 4634626SN/A mshr_hits[access_idx] 4648833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4654626SN/A .name(name() + "." + cstr + "_mshr_hits") 4664626SN/A .desc("number of " + cstr + " MSHR hits") 4674626SN/A .flags(total | nozero | nonan) 4684626SN/A ; 4698833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4708833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4718833Sdam.sunwoo@arm.com } 4724626SN/A } 4734626SN/A 4744626SN/A demandMshrHits 4754626SN/A .name(name() + ".demand_mshr_hits") 4764626SN/A .desc("number of demand (read+write) MSHR hits") 4778833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4784626SN/A ; 4794871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4808833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4818833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4828833Sdam.sunwoo@arm.com } 4834626SN/A 4844626SN/A overallMshrHits 4854626SN/A .name(name() + ".overall_mshr_hits") 4864626SN/A .desc("number of overall MSHR hits") 4878833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4884626SN/A ; 4894871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4908833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4918833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4928833Sdam.sunwoo@arm.com } 4934626SN/A 4944626SN/A // MSHR miss statistics 4954626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4964626SN/A MemCmd cmd(access_idx); 4974626SN/A const string &cstr = cmd.toString(); 4984626SN/A 4994626SN/A mshr_misses[access_idx] 5008833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5014626SN/A .name(name() + "." + cstr + "_mshr_misses") 5024626SN/A .desc("number of " + cstr + " MSHR misses") 5034626SN/A .flags(total | nozero | nonan) 5044626SN/A ; 5058833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5068833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 5078833Sdam.sunwoo@arm.com } 5084626SN/A } 5094626SN/A 5104626SN/A demandMshrMisses 5114626SN/A .name(name() + ".demand_mshr_misses") 5124626SN/A .desc("number of demand (read+write) MSHR misses") 5138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5144626SN/A ; 5154871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 5168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5178833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 5188833Sdam.sunwoo@arm.com } 5194626SN/A 5204626SN/A overallMshrMisses 5214626SN/A .name(name() + ".overall_mshr_misses") 5224626SN/A .desc("number of overall MSHR misses") 5238833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5244626SN/A ; 5254871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5278833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5288833Sdam.sunwoo@arm.com } 5294626SN/A 5304626SN/A // MSHR miss latency statistics 5314626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5324626SN/A MemCmd cmd(access_idx); 5334626SN/A const string &cstr = cmd.toString(); 5344626SN/A 5354626SN/A mshr_miss_latency[access_idx] 5368833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5374626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5384626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5394626SN/A .flags(total | nozero | nonan) 5404626SN/A ; 5418833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5428833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5438833Sdam.sunwoo@arm.com } 5444626SN/A } 5454626SN/A 5464626SN/A demandMshrMissLatency 5474626SN/A .name(name() + ".demand_mshr_miss_latency") 5484626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5504626SN/A ; 5514871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5538833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5548833Sdam.sunwoo@arm.com } 5554626SN/A 5564626SN/A overallMshrMissLatency 5574626SN/A .name(name() + ".overall_mshr_miss_latency") 5584626SN/A .desc("number of overall MSHR miss cycles") 5598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5604626SN/A ; 5614871SN/A overallMshrMissLatency = 5624871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5638833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5648833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5658833Sdam.sunwoo@arm.com } 5664626SN/A 5674626SN/A // MSHR uncacheable statistics 5684626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5694626SN/A MemCmd cmd(access_idx); 5704626SN/A const string &cstr = cmd.toString(); 5714626SN/A 5724626SN/A mshr_uncacheable[access_idx] 5738833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5744626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5754626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5764626SN/A .flags(total | nozero | nonan) 5774626SN/A ; 5788833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5798833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5808833Sdam.sunwoo@arm.com } 5814626SN/A } 5824626SN/A 5834626SN/A overallMshrUncacheable 5844626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5854626SN/A .desc("number of overall MSHR uncacheable misses") 5868833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5874626SN/A ; 5884871SN/A overallMshrUncacheable = 5894871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5908833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5918833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5928833Sdam.sunwoo@arm.com } 5934626SN/A 5944626SN/A // MSHR miss latency statistics 5954626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5964626SN/A MemCmd cmd(access_idx); 5974626SN/A const string &cstr = cmd.toString(); 5984626SN/A 5994626SN/A mshr_uncacheable_lat[access_idx] 6008833Sdam.sunwoo@arm.com .init(system->maxMasters()) 6014626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 6024626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 6034626SN/A .flags(total | nozero | nonan) 6044626SN/A ; 6058833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6068833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 6078833Sdam.sunwoo@arm.com } 6084626SN/A } 6094626SN/A 6104626SN/A overallMshrUncacheableLatency 6114626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 6124626SN/A .desc("number of overall MSHR uncacheable cycles") 6138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6144626SN/A ; 6154871SN/A overallMshrUncacheableLatency = 6164871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 6174871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 6188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6198833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 6208833Sdam.sunwoo@arm.com } 6214626SN/A 6224626SN/A#if 0 6234626SN/A // MSHR access formulas 6244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6254626SN/A MemCmd cmd(access_idx); 6264626SN/A const string &cstr = cmd.toString(); 6274626SN/A 6284626SN/A mshrAccesses[access_idx] 6294626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6304626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6314626SN/A .flags(total | nozero | nonan) 6324626SN/A ; 6334626SN/A mshrAccesses[access_idx] = 6344626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6354626SN/A + mshr_uncacheable[access_idx]; 6364626SN/A } 6374626SN/A 6384626SN/A demandMshrAccesses 6394626SN/A .name(name() + ".demand_mshr_accesses") 6404626SN/A .desc("number of demand (read+write) mshr accesses") 6414626SN/A .flags(total | nozero | nonan) 6424626SN/A ; 6434626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6444626SN/A 6454626SN/A overallMshrAccesses 6464626SN/A .name(name() + ".overall_mshr_accesses") 6474626SN/A .desc("number of overall (read+write) mshr accesses") 6484626SN/A .flags(total | nozero | nonan) 6494626SN/A ; 6504626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6514626SN/A + overallMshrUncacheable; 6524626SN/A#endif 6534626SN/A 6544626SN/A // MSHR miss rate formulas 6554626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6564626SN/A MemCmd cmd(access_idx); 6574626SN/A const string &cstr = cmd.toString(); 6584626SN/A 6594626SN/A mshrMissRate[access_idx] 6604626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6614626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6624626SN/A .flags(total | nozero | nonan) 6634626SN/A ; 6644626SN/A mshrMissRate[access_idx] = 6654626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6668833Sdam.sunwoo@arm.com 6678833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6688833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6698833Sdam.sunwoo@arm.com } 6704626SN/A } 6714626SN/A 6724626SN/A demandMshrMissRate 6734626SN/A .name(name() + ".demand_mshr_miss_rate") 6744626SN/A .desc("mshr miss rate for demand accesses") 6758833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6764626SN/A ; 6774626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6788833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6798833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6808833Sdam.sunwoo@arm.com } 6814626SN/A 6824626SN/A overallMshrMissRate 6834626SN/A .name(name() + ".overall_mshr_miss_rate") 6844626SN/A .desc("mshr miss rate for overall accesses") 6858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6864626SN/A ; 6874626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6898833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6908833Sdam.sunwoo@arm.com } 6914626SN/A 6924626SN/A // mshrMiss latency formulas 6934626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6944626SN/A MemCmd cmd(access_idx); 6954626SN/A const string &cstr = cmd.toString(); 6964626SN/A 6974626SN/A avgMshrMissLatency[access_idx] 6984626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6994626SN/A .desc("average " + cstr + " mshr miss latency") 7004626SN/A .flags(total | nozero | nonan) 7014626SN/A ; 7024626SN/A avgMshrMissLatency[access_idx] = 7034626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 7048833Sdam.sunwoo@arm.com 7058833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7068833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 7078833Sdam.sunwoo@arm.com } 7084626SN/A } 7094626SN/A 7104626SN/A demandAvgMshrMissLatency 7114626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 7124626SN/A .desc("average overall mshr miss latency") 7138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7144626SN/A ; 7154626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 7168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7178833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7188833Sdam.sunwoo@arm.com } 7194626SN/A 7204626SN/A overallAvgMshrMissLatency 7214626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7224626SN/A .desc("average overall mshr miss latency") 7238833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7244626SN/A ; 7254626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7268833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7278833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7288833Sdam.sunwoo@arm.com } 7294626SN/A 7304626SN/A // mshrUncacheable latency formulas 7314626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7324626SN/A MemCmd cmd(access_idx); 7334626SN/A const string &cstr = cmd.toString(); 7344626SN/A 7354626SN/A avgMshrUncacheableLatency[access_idx] 7364626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7374626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7384626SN/A .flags(total | nozero | nonan) 7394626SN/A ; 7404626SN/A avgMshrUncacheableLatency[access_idx] = 7414626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7428833Sdam.sunwoo@arm.com 7438833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7448833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7458833Sdam.sunwoo@arm.com } 7464626SN/A } 7474626SN/A 7484626SN/A overallAvgMshrUncacheableLatency 7494626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7504626SN/A .desc("average overall mshr uncacheable latency") 7518833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7524626SN/A ; 7534626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7558833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7568833Sdam.sunwoo@arm.com } 7574626SN/A 7584626SN/A mshr_cap_events 7598833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7604626SN/A .name(name() + ".mshr_cap_events") 7614626SN/A .desc("number of times MSHR cap was activated") 7628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7634626SN/A ; 7648833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7658833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7668833Sdam.sunwoo@arm.com } 7674626SN/A 7684626SN/A //software prefetching stats 7694626SN/A soft_prefetch_mshr_full 7708833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7714626SN/A .name(name() + ".soft_prefetch_mshr_full") 7724626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7738833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7744626SN/A ; 7758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7768833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7778833Sdam.sunwoo@arm.com } 7784626SN/A 7794626SN/A mshr_no_allocate_misses 7804626SN/A .name(name() +".no_allocate_misses") 7814626SN/A .desc("Number of misses that were no-allocate") 7824626SN/A ; 7834626SN/A 7842810SN/A} 785