base.cc revision 10885
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 685034SN/ABaseCache::BaseCache(const Params *p) 695034SN/A : MemObject(p), 7010360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7110622Smitch.hayenga@arm.com mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs), 7210622Smitch.hayenga@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0, 734628SN/A MSHRQueue_WriteBuffer), 749814Sandreas.hansson@arm.com blkSize(p->system->cacheLineSize()), 7510693SMarco.Balboni@ARM.com lookupLatency(p->hit_latency), 7610693SMarco.Balboni@ARM.com forwardLatency(p->hit_latency), 7710693SMarco.Balboni@ARM.com fillLatency(p->response_latency), 789263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 795034SN/A numTarget(p->tgts_per_mshr), 806122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 818134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 8210884Sandreas.hansson@arm.com isReadOnly(p->is_read_only), 834626SN/A blocked(0), 8410360Sandreas.hansson@arm.com order(0), 854626SN/A noTargetMSHR(NULL), 865034SN/A missCount(p->max_miss_count), 878883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 888833Sdam.sunwoo@arm.com system(p->system) 894458SN/A{ 902810SN/A} 912810SN/A 923013SN/Avoid 938856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 942810SN/A{ 953013SN/A assert(!blocked); 9610714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 972810SN/A blocked = true; 989614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 999614Srene.dejong@arm.com // happened, cancel it 1009614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 10110345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 10210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 10310345SCurtis.Dunham@arm.com mustSendRetry = true; 1049614Srene.dejong@arm.com } 1052810SN/A} 1062810SN/A 1072810SN/Avoid 1088856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1092810SN/A{ 1103013SN/A assert(blocked); 11110714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1123013SN/A blocked = false; 1138856Sandreas.hansson@arm.com if (mustSendRetry) { 11410714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1158922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1162897SN/A } 1172810SN/A} 1182810SN/A 11910344Sandreas.hansson@arm.comvoid 12010344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 12110344Sandreas.hansson@arm.com{ 12210714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 12310344Sandreas.hansson@arm.com 12410344Sandreas.hansson@arm.com // reset the flag and call retry 12510344Sandreas.hansson@arm.com mustSendRetry = false; 12610713Sandreas.hansson@arm.com sendRetryReq(); 12710344Sandreas.hansson@arm.com} 1282844SN/A 1292810SN/Avoid 1302858SN/ABaseCache::init() 1312858SN/A{ 1328856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1338922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1348711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1352858SN/A} 1362858SN/A 1379294Sandreas.hansson@arm.comBaseMasterPort & 1389294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1398922Swilliam.wang@arm.com{ 1408922Swilliam.wang@arm.com if (if_name == "mem_side") { 1418922Swilliam.wang@arm.com return *memSidePort; 1428922Swilliam.wang@arm.com } else { 1438922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1448922Swilliam.wang@arm.com } 1458922Swilliam.wang@arm.com} 1468922Swilliam.wang@arm.com 1479294Sandreas.hansson@arm.comBaseSlavePort & 1489294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1498922Swilliam.wang@arm.com{ 1508922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1518922Swilliam.wang@arm.com return *cpuSidePort; 1528922Swilliam.wang@arm.com } else { 1538922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1548922Swilliam.wang@arm.com } 1558922Swilliam.wang@arm.com} 1564628SN/A 15710821Sandreas.hansson@arm.combool 15810821Sandreas.hansson@arm.comBaseCache::inRange(Addr addr) const 15910821Sandreas.hansson@arm.com{ 16010821Sandreas.hansson@arm.com for (const auto& r : addrRanges) { 16110821Sandreas.hansson@arm.com if (r.contains(addr)) { 16210821Sandreas.hansson@arm.com return true; 16310821Sandreas.hansson@arm.com } 16410821Sandreas.hansson@arm.com } 16510821Sandreas.hansson@arm.com return false; 16610821Sandreas.hansson@arm.com} 16710821Sandreas.hansson@arm.com 1682858SN/Avoid 1692810SN/ABaseCache::regStats() 1702810SN/A{ 1712810SN/A using namespace Stats; 1722810SN/A 1732810SN/A // Hit statistics 1744022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1754022SN/A MemCmd cmd(access_idx); 1764022SN/A const string &cstr = cmd.toString(); 1772810SN/A 1782810SN/A hits[access_idx] 1798833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1802810SN/A .name(name() + "." + cstr + "_hits") 1812810SN/A .desc("number of " + cstr + " hits") 1822810SN/A .flags(total | nozero | nonan) 1832810SN/A ; 1848833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1858833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1868833Sdam.sunwoo@arm.com } 1872810SN/A } 1882810SN/A 1894871SN/A// These macros make it easier to sum the right subset of commands and 1904871SN/A// to change the subset of commands that are considered "demand" vs 1914871SN/A// "non-demand" 1924871SN/A#define SUM_DEMAND(s) \ 19310885Sandreas.hansson@arm.com (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + \ 19410885Sandreas.hansson@arm.com s[MemCmd::ReadExReq] + s[MemCmd::ReadCleanReq] + s[MemCmd::ReadSharedReq]) 1954871SN/A 1964871SN/A// should writebacks be included here? prior code was inconsistent... 1974871SN/A#define SUM_NON_DEMAND(s) \ 1984871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1994871SN/A 2002810SN/A demandHits 2012810SN/A .name(name() + ".demand_hits") 2022810SN/A .desc("number of demand (read+write) hits") 2038833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2042810SN/A ; 2054871SN/A demandHits = SUM_DEMAND(hits); 2068833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2078833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 2088833Sdam.sunwoo@arm.com } 2092810SN/A 2102810SN/A overallHits 2112810SN/A .name(name() + ".overall_hits") 2122810SN/A .desc("number of overall hits") 2138833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2142810SN/A ; 2154871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2168833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2178833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2188833Sdam.sunwoo@arm.com } 2192810SN/A 2202810SN/A // Miss statistics 2214022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2224022SN/A MemCmd cmd(access_idx); 2234022SN/A const string &cstr = cmd.toString(); 2242810SN/A 2252810SN/A misses[access_idx] 2268833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2272810SN/A .name(name() + "." + cstr + "_misses") 2282810SN/A .desc("number of " + cstr + " misses") 2292810SN/A .flags(total | nozero | nonan) 2302810SN/A ; 2318833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2328833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2338833Sdam.sunwoo@arm.com } 2342810SN/A } 2352810SN/A 2362810SN/A demandMisses 2372810SN/A .name(name() + ".demand_misses") 2382810SN/A .desc("number of demand (read+write) misses") 2398833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2402810SN/A ; 2414871SN/A demandMisses = SUM_DEMAND(misses); 2428833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2438833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2448833Sdam.sunwoo@arm.com } 2452810SN/A 2462810SN/A overallMisses 2472810SN/A .name(name() + ".overall_misses") 2482810SN/A .desc("number of overall misses") 2498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2502810SN/A ; 2514871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2538833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2548833Sdam.sunwoo@arm.com } 2552810SN/A 2562810SN/A // Miss latency statistics 2574022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2584022SN/A MemCmd cmd(access_idx); 2594022SN/A const string &cstr = cmd.toString(); 2602810SN/A 2612810SN/A missLatency[access_idx] 2628833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2632810SN/A .name(name() + "." + cstr + "_miss_latency") 2642810SN/A .desc("number of " + cstr + " miss cycles") 2652810SN/A .flags(total | nozero | nonan) 2662810SN/A ; 2678833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2688833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2698833Sdam.sunwoo@arm.com } 2702810SN/A } 2712810SN/A 2722810SN/A demandMissLatency 2732810SN/A .name(name() + ".demand_miss_latency") 2742810SN/A .desc("number of demand (read+write) miss cycles") 2758833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2762810SN/A ; 2774871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2788833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2798833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2808833Sdam.sunwoo@arm.com } 2812810SN/A 2822810SN/A overallMissLatency 2832810SN/A .name(name() + ".overall_miss_latency") 2842810SN/A .desc("number of overall miss cycles") 2858833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2862810SN/A ; 2874871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2888833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2898833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2908833Sdam.sunwoo@arm.com } 2912810SN/A 2922810SN/A // access formulas 2934022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2944022SN/A MemCmd cmd(access_idx); 2954022SN/A const string &cstr = cmd.toString(); 2962810SN/A 2972810SN/A accesses[access_idx] 2982810SN/A .name(name() + "." + cstr + "_accesses") 2992810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 3002810SN/A .flags(total | nozero | nonan) 3012810SN/A ; 3028833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 3032810SN/A 3048833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3058833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 3068833Sdam.sunwoo@arm.com } 3072810SN/A } 3082810SN/A 3092810SN/A demandAccesses 3102810SN/A .name(name() + ".demand_accesses") 3112810SN/A .desc("number of demand (read+write) accesses") 3128833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3132810SN/A ; 3142810SN/A demandAccesses = demandHits + demandMisses; 3158833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3168833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3178833Sdam.sunwoo@arm.com } 3182810SN/A 3192810SN/A overallAccesses 3202810SN/A .name(name() + ".overall_accesses") 3212810SN/A .desc("number of overall (read+write) accesses") 3228833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3232810SN/A ; 3242810SN/A overallAccesses = overallHits + overallMisses; 3258833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3268833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3278833Sdam.sunwoo@arm.com } 3282810SN/A 3292810SN/A // miss rate formulas 3304022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3314022SN/A MemCmd cmd(access_idx); 3324022SN/A const string &cstr = cmd.toString(); 3332810SN/A 3342810SN/A missRate[access_idx] 3352810SN/A .name(name() + "." + cstr + "_miss_rate") 3362810SN/A .desc("miss rate for " + cstr + " accesses") 3372810SN/A .flags(total | nozero | nonan) 3382810SN/A ; 3398833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3402810SN/A 3418833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3428833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3438833Sdam.sunwoo@arm.com } 3442810SN/A } 3452810SN/A 3462810SN/A demandMissRate 3472810SN/A .name(name() + ".demand_miss_rate") 3482810SN/A .desc("miss rate for demand accesses") 3498833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3502810SN/A ; 3512810SN/A demandMissRate = demandMisses / demandAccesses; 3528833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3538833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3548833Sdam.sunwoo@arm.com } 3552810SN/A 3562810SN/A overallMissRate 3572810SN/A .name(name() + ".overall_miss_rate") 3582810SN/A .desc("miss rate for overall accesses") 3598833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3602810SN/A ; 3612810SN/A overallMissRate = overallMisses / overallAccesses; 3628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3638833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3648833Sdam.sunwoo@arm.com } 3652810SN/A 3662810SN/A // miss latency formulas 3674022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3684022SN/A MemCmd cmd(access_idx); 3694022SN/A const string &cstr = cmd.toString(); 3702810SN/A 3712810SN/A avgMissLatency[access_idx] 3722810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3732810SN/A .desc("average " + cstr + " miss latency") 3742810SN/A .flags(total | nozero | nonan) 3752810SN/A ; 3762810SN/A avgMissLatency[access_idx] = 3772810SN/A missLatency[access_idx] / misses[access_idx]; 3788833Sdam.sunwoo@arm.com 3798833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3808833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3818833Sdam.sunwoo@arm.com } 3822810SN/A } 3832810SN/A 3842810SN/A demandAvgMissLatency 3852810SN/A .name(name() + ".demand_avg_miss_latency") 3862810SN/A .desc("average overall miss latency") 3878833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3882810SN/A ; 3892810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3908833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3918833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3928833Sdam.sunwoo@arm.com } 3932810SN/A 3942810SN/A overallAvgMissLatency 3952810SN/A .name(name() + ".overall_avg_miss_latency") 3962810SN/A .desc("average overall miss latency") 3978833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3982810SN/A ; 3992810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 4008833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4018833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 4028833Sdam.sunwoo@arm.com } 4032810SN/A 4042810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 4052810SN/A blocked_cycles 4062810SN/A .name(name() + ".blocked_cycles") 4072810SN/A .desc("number of cycles access was blocked") 4082810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4092810SN/A .subname(Blocked_NoTargets, "no_targets") 4102810SN/A ; 4112810SN/A 4122810SN/A 4132810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 4142810SN/A blocked_causes 4152810SN/A .name(name() + ".blocked") 4162810SN/A .desc("number of cycles access was blocked") 4172810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4182810SN/A .subname(Blocked_NoTargets, "no_targets") 4192810SN/A ; 4202810SN/A 4212810SN/A avg_blocked 4222810SN/A .name(name() + ".avg_blocked_cycles") 4232810SN/A .desc("average number of cycles each access was blocked") 4242810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4252810SN/A .subname(Blocked_NoTargets, "no_targets") 4262810SN/A ; 4272810SN/A 4282810SN/A avg_blocked = blocked_cycles / blocked_causes; 4292810SN/A 4302810SN/A fastWrites 4312810SN/A .name(name() + ".fast_writes") 4322810SN/A .desc("number of fast writes performed") 4332810SN/A ; 4342810SN/A 4352810SN/A cacheCopies 4362810SN/A .name(name() + ".cache_copies") 4372810SN/A .desc("number of cache copies performed") 4382810SN/A ; 4392826SN/A 4404626SN/A writebacks 4418833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4424626SN/A .name(name() + ".writebacks") 4434626SN/A .desc("number of writebacks") 4448833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4454626SN/A ; 4468833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4478833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4488833Sdam.sunwoo@arm.com } 4494626SN/A 4504626SN/A // MSHR statistics 4514626SN/A // MSHR hit statistics 4524626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4534626SN/A MemCmd cmd(access_idx); 4544626SN/A const string &cstr = cmd.toString(); 4554626SN/A 4564626SN/A mshr_hits[access_idx] 4578833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4584626SN/A .name(name() + "." + cstr + "_mshr_hits") 4594626SN/A .desc("number of " + cstr + " MSHR hits") 4604626SN/A .flags(total | nozero | nonan) 4614626SN/A ; 4628833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4638833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4648833Sdam.sunwoo@arm.com } 4654626SN/A } 4664626SN/A 4674626SN/A demandMshrHits 4684626SN/A .name(name() + ".demand_mshr_hits") 4694626SN/A .desc("number of demand (read+write) MSHR hits") 4708833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4714626SN/A ; 4724871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4738833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4748833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4758833Sdam.sunwoo@arm.com } 4764626SN/A 4774626SN/A overallMshrHits 4784626SN/A .name(name() + ".overall_mshr_hits") 4794626SN/A .desc("number of overall MSHR hits") 4808833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4814626SN/A ; 4824871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4848833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4858833Sdam.sunwoo@arm.com } 4864626SN/A 4874626SN/A // MSHR miss statistics 4884626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4894626SN/A MemCmd cmd(access_idx); 4904626SN/A const string &cstr = cmd.toString(); 4914626SN/A 4924626SN/A mshr_misses[access_idx] 4938833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4944626SN/A .name(name() + "." + cstr + "_mshr_misses") 4954626SN/A .desc("number of " + cstr + " MSHR misses") 4964626SN/A .flags(total | nozero | nonan) 4974626SN/A ; 4988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4998833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 5008833Sdam.sunwoo@arm.com } 5014626SN/A } 5024626SN/A 5034626SN/A demandMshrMisses 5044626SN/A .name(name() + ".demand_mshr_misses") 5054626SN/A .desc("number of demand (read+write) MSHR misses") 5068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5074626SN/A ; 5084871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 5098833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5108833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 5118833Sdam.sunwoo@arm.com } 5124626SN/A 5134626SN/A overallMshrMisses 5144626SN/A .name(name() + ".overall_mshr_misses") 5154626SN/A .desc("number of overall MSHR misses") 5168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5174626SN/A ; 5184871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5208833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5218833Sdam.sunwoo@arm.com } 5224626SN/A 5234626SN/A // MSHR miss latency statistics 5244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5254626SN/A MemCmd cmd(access_idx); 5264626SN/A const string &cstr = cmd.toString(); 5274626SN/A 5284626SN/A mshr_miss_latency[access_idx] 5298833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5304626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5314626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5324626SN/A .flags(total | nozero | nonan) 5334626SN/A ; 5348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5358833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5368833Sdam.sunwoo@arm.com } 5374626SN/A } 5384626SN/A 5394626SN/A demandMshrMissLatency 5404626SN/A .name(name() + ".demand_mshr_miss_latency") 5414626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5434626SN/A ; 5444871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5458833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5468833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5478833Sdam.sunwoo@arm.com } 5484626SN/A 5494626SN/A overallMshrMissLatency 5504626SN/A .name(name() + ".overall_mshr_miss_latency") 5514626SN/A .desc("number of overall MSHR miss cycles") 5528833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5534626SN/A ; 5544871SN/A overallMshrMissLatency = 5554871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5568833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5578833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5588833Sdam.sunwoo@arm.com } 5594626SN/A 5604626SN/A // MSHR uncacheable statistics 5614626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5624626SN/A MemCmd cmd(access_idx); 5634626SN/A const string &cstr = cmd.toString(); 5644626SN/A 5654626SN/A mshr_uncacheable[access_idx] 5668833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5674626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5684626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5694626SN/A .flags(total | nozero | nonan) 5704626SN/A ; 5718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5728833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5738833Sdam.sunwoo@arm.com } 5744626SN/A } 5754626SN/A 5764626SN/A overallMshrUncacheable 5774626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5784626SN/A .desc("number of overall MSHR uncacheable misses") 5798833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5804626SN/A ; 5814871SN/A overallMshrUncacheable = 5824871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5838833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5848833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5858833Sdam.sunwoo@arm.com } 5864626SN/A 5874626SN/A // MSHR miss latency statistics 5884626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5894626SN/A MemCmd cmd(access_idx); 5904626SN/A const string &cstr = cmd.toString(); 5914626SN/A 5924626SN/A mshr_uncacheable_lat[access_idx] 5938833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5944626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5954626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5964626SN/A .flags(total | nozero | nonan) 5974626SN/A ; 5988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5998833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 6008833Sdam.sunwoo@arm.com } 6014626SN/A } 6024626SN/A 6034626SN/A overallMshrUncacheableLatency 6044626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 6054626SN/A .desc("number of overall MSHR uncacheable cycles") 6068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6074626SN/A ; 6084871SN/A overallMshrUncacheableLatency = 6094871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 6104871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 6118833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6128833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 6138833Sdam.sunwoo@arm.com } 6144626SN/A 6154626SN/A#if 0 6164626SN/A // MSHR access formulas 6174626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6184626SN/A MemCmd cmd(access_idx); 6194626SN/A const string &cstr = cmd.toString(); 6204626SN/A 6214626SN/A mshrAccesses[access_idx] 6224626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6234626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6244626SN/A .flags(total | nozero | nonan) 6254626SN/A ; 6264626SN/A mshrAccesses[access_idx] = 6274626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6284626SN/A + mshr_uncacheable[access_idx]; 6294626SN/A } 6304626SN/A 6314626SN/A demandMshrAccesses 6324626SN/A .name(name() + ".demand_mshr_accesses") 6334626SN/A .desc("number of demand (read+write) mshr accesses") 6344626SN/A .flags(total | nozero | nonan) 6354626SN/A ; 6364626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6374626SN/A 6384626SN/A overallMshrAccesses 6394626SN/A .name(name() + ".overall_mshr_accesses") 6404626SN/A .desc("number of overall (read+write) mshr accesses") 6414626SN/A .flags(total | nozero | nonan) 6424626SN/A ; 6434626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6444626SN/A + overallMshrUncacheable; 6454626SN/A#endif 6464626SN/A 6474626SN/A // MSHR miss rate formulas 6484626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6494626SN/A MemCmd cmd(access_idx); 6504626SN/A const string &cstr = cmd.toString(); 6514626SN/A 6524626SN/A mshrMissRate[access_idx] 6534626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6544626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6554626SN/A .flags(total | nozero | nonan) 6564626SN/A ; 6574626SN/A mshrMissRate[access_idx] = 6584626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6598833Sdam.sunwoo@arm.com 6608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6618833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6628833Sdam.sunwoo@arm.com } 6634626SN/A } 6644626SN/A 6654626SN/A demandMshrMissRate 6664626SN/A .name(name() + ".demand_mshr_miss_rate") 6674626SN/A .desc("mshr miss rate for demand accesses") 6688833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6694626SN/A ; 6704626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6718833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6728833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6738833Sdam.sunwoo@arm.com } 6744626SN/A 6754626SN/A overallMshrMissRate 6764626SN/A .name(name() + ".overall_mshr_miss_rate") 6774626SN/A .desc("mshr miss rate for overall accesses") 6788833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6794626SN/A ; 6804626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6818833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6828833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6838833Sdam.sunwoo@arm.com } 6844626SN/A 6854626SN/A // mshrMiss latency formulas 6864626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6874626SN/A MemCmd cmd(access_idx); 6884626SN/A const string &cstr = cmd.toString(); 6894626SN/A 6904626SN/A avgMshrMissLatency[access_idx] 6914626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6924626SN/A .desc("average " + cstr + " mshr miss latency") 6934626SN/A .flags(total | nozero | nonan) 6944626SN/A ; 6954626SN/A avgMshrMissLatency[access_idx] = 6964626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6978833Sdam.sunwoo@arm.com 6988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6998833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 7008833Sdam.sunwoo@arm.com } 7014626SN/A } 7024626SN/A 7034626SN/A demandAvgMshrMissLatency 7044626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 7054626SN/A .desc("average overall mshr miss latency") 7068833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7074626SN/A ; 7084626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 7098833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7108833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7118833Sdam.sunwoo@arm.com } 7124626SN/A 7134626SN/A overallAvgMshrMissLatency 7144626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7154626SN/A .desc("average overall mshr miss latency") 7168833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7174626SN/A ; 7184626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7198833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7208833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7218833Sdam.sunwoo@arm.com } 7224626SN/A 7234626SN/A // mshrUncacheable latency formulas 7244626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7254626SN/A MemCmd cmd(access_idx); 7264626SN/A const string &cstr = cmd.toString(); 7274626SN/A 7284626SN/A avgMshrUncacheableLatency[access_idx] 7294626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7304626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7314626SN/A .flags(total | nozero | nonan) 7324626SN/A ; 7334626SN/A avgMshrUncacheableLatency[access_idx] = 7344626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7358833Sdam.sunwoo@arm.com 7368833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7378833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7388833Sdam.sunwoo@arm.com } 7394626SN/A } 7404626SN/A 7414626SN/A overallAvgMshrUncacheableLatency 7424626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7434626SN/A .desc("average overall mshr uncacheable latency") 7448833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7454626SN/A ; 7464626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7488833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7498833Sdam.sunwoo@arm.com } 7504626SN/A 7514626SN/A mshr_cap_events 7528833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7534626SN/A .name(name() + ".mshr_cap_events") 7544626SN/A .desc("number of times MSHR cap was activated") 7558833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7564626SN/A ; 7578833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7588833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7598833Sdam.sunwoo@arm.com } 7604626SN/A 7614626SN/A //software prefetching stats 7624626SN/A soft_prefetch_mshr_full 7638833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7644626SN/A .name(name() + ".soft_prefetch_mshr_full") 7654626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7668833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7674626SN/A ; 7688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7698833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7708833Sdam.sunwoo@arm.com } 7714626SN/A 7724626SN/A mshr_no_allocate_misses 7734626SN/A .name(name() +".no_allocate_misses") 7744626SN/A .desc("Number of misses that were no-allocate") 7754626SN/A ; 7764626SN/A 7772810SN/A} 7783503SN/A 7793503SN/Aunsigned int 7809342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm) 7813503SN/A{ 7829347SAndreas.Sandberg@arm.com int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 7839347SAndreas.Sandberg@arm.com mshrQueue.drain(dm) + writeBuffer.drain(dm); 7844626SN/A 7853503SN/A // Set status 7864626SN/A if (count != 0) { 7879342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 7889152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7894626SN/A return count; 7903503SN/A } 7913503SN/A 7929342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 7933503SN/A return 0; 7943503SN/A} 7959795Sandreas.hansson@arm.com 7969795Sandreas.hansson@arm.comBaseCache * 7979795Sandreas.hansson@arm.comBaseCacheParams::create() 7989795Sandreas.hansson@arm.com{ 7999796Sprakash.ramrakhyani@arm.com assert(tags); 8009796Sprakash.ramrakhyani@arm.com 80110815Sdavid.guillen@arm.com return new Cache(this); 8029795Sandreas.hansson@arm.com} 803