base.cc revision 10815
12810SN/A/* 29614Srene.dejong@arm.com * Copyright (c) 2012-2013 ARM Limited 38856Sandreas.hansson@arm.com * All rights reserved. 48856Sandreas.hansson@arm.com * 58856Sandreas.hansson@arm.com * The license below extends only to copyright in the software and shall 68856Sandreas.hansson@arm.com * not be construed as granting a license to any other intellectual 78856Sandreas.hansson@arm.com * property including but not limited to intellectual property relating 88856Sandreas.hansson@arm.com * to a hardware implementation of the functionality of the software 98856Sandreas.hansson@arm.com * licensed hereunder. You may use the software subject to the license 108856Sandreas.hansson@arm.com * terms below provided that you ensure that this notice is replicated 118856Sandreas.hansson@arm.com * unmodified and in its entirety in all distributions of the software, 128856Sandreas.hansson@arm.com * modified or unmodified, in source code or in binary form. 138856Sandreas.hansson@arm.com * 142810SN/A * Copyright (c) 2003-2005 The Regents of The University of Michigan 152810SN/A * All rights reserved. 162810SN/A * 172810SN/A * Redistribution and use in source and binary forms, with or without 182810SN/A * modification, are permitted provided that the following conditions are 192810SN/A * met: redistributions of source code must retain the above copyright 202810SN/A * notice, this list of conditions and the following disclaimer; 212810SN/A * redistributions in binary form must reproduce the above copyright 222810SN/A * notice, this list of conditions and the following disclaimer in the 232810SN/A * documentation and/or other materials provided with the distribution; 242810SN/A * neither the name of the copyright holders nor the names of its 252810SN/A * contributors may be used to endorse or promote products derived from 262810SN/A * this software without specific prior written permission. 272810SN/A * 282810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392810SN/A * 402810SN/A * Authors: Erik Hallnor 412810SN/A */ 422810SN/A 432810SN/A/** 442810SN/A * @file 452810SN/A * Definition of BaseCache functions. 462810SN/A */ 472810SN/A 488232Snate@binkert.org#include "debug/Cache.hh" 499152Satgutier@umich.edu#include "debug/Drain.hh" 509795Sandreas.hansson@arm.com#include "mem/cache/tags/fa_lru.hh" 519795Sandreas.hansson@arm.com#include "mem/cache/tags/lru.hh" 5210263Satgutier@umich.edu#include "mem/cache/tags/random_repl.hh" 535338Sstever@gmail.com#include "mem/cache/base.hh" 549795Sandreas.hansson@arm.com#include "mem/cache/cache.hh" 555338Sstever@gmail.com#include "mem/cache/mshr.hh" 568786Sgblack@eecs.umich.edu#include "sim/full_system.hh" 572810SN/A 582810SN/Ausing namespace std; 592810SN/A 608856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::CacheSlavePort(const std::string &_name, 618856Sandreas.hansson@arm.com BaseCache *_cache, 628856Sandreas.hansson@arm.com const std::string &_label) 638922Swilliam.wang@arm.com : QueuedSlavePort(_name, _cache, queue), queue(*_cache, *this, _label), 648914Sandreas.hansson@arm.com blocked(false), mustSendRetry(false), sendRetryEvent(this) 658856Sandreas.hansson@arm.com{ 668856Sandreas.hansson@arm.com} 674475SN/A 685034SN/ABaseCache::BaseCache(const Params *p) 695034SN/A : MemObject(p), 7010360Sandreas.hansson@arm.com cpuSidePort(nullptr), memSidePort(nullptr), 7110622Smitch.hayenga@arm.com mshrQueue("MSHRs", p->mshrs, 4, p->demand_mshr_reserve, MSHRQueue_MSHRs), 7210622Smitch.hayenga@arm.com writeBuffer("write buffer", p->write_buffers, p->mshrs+1000, 0, 734628SN/A MSHRQueue_WriteBuffer), 749814Sandreas.hansson@arm.com blkSize(p->system->cacheLineSize()), 7510693SMarco.Balboni@ARM.com lookupLatency(p->hit_latency), 7610693SMarco.Balboni@ARM.com forwardLatency(p->hit_latency), 7710693SMarco.Balboni@ARM.com fillLatency(p->response_latency), 789263Smrinmoy.ghosh@arm.com responseLatency(p->response_latency), 795034SN/A numTarget(p->tgts_per_mshr), 806122SSteve.Reinhardt@amd.com forwardSnoops(p->forward_snoops), 818134SAli.Saidi@ARM.com isTopLevel(p->is_top_level), 824626SN/A blocked(0), 8310360Sandreas.hansson@arm.com order(0), 844626SN/A noTargetMSHR(NULL), 855034SN/A missCount(p->max_miss_count), 868883SAli.Saidi@ARM.com addrRanges(p->addr_ranges.begin(), p->addr_ranges.end()), 878833Sdam.sunwoo@arm.com system(p->system) 884458SN/A{ 892810SN/A} 902810SN/A 913013SN/Avoid 928856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::setBlocked() 932810SN/A{ 943013SN/A assert(!blocked); 9510714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is blocking new requests\n"); 962810SN/A blocked = true; 979614Srene.dejong@arm.com // if we already scheduled a retry in this cycle, but it has not yet 989614Srene.dejong@arm.com // happened, cancel it 999614Srene.dejong@arm.com if (sendRetryEvent.scheduled()) { 10010345SCurtis.Dunham@arm.com owner.deschedule(sendRetryEvent); 10110714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port descheduled retry\n"); 10210345SCurtis.Dunham@arm.com mustSendRetry = true; 1039614Srene.dejong@arm.com } 1042810SN/A} 1052810SN/A 1062810SN/Avoid 1078856Sandreas.hansson@arm.comBaseCache::CacheSlavePort::clearBlocked() 1082810SN/A{ 1093013SN/A assert(blocked); 11010714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is accepting new requests\n"); 1113013SN/A blocked = false; 1128856Sandreas.hansson@arm.com if (mustSendRetry) { 11310714Sandreas.hansson@arm.com // @TODO: need to find a better time (next cycle?) 1148922Swilliam.wang@arm.com owner.schedule(sendRetryEvent, curTick() + 1); 1152897SN/A } 1162810SN/A} 1172810SN/A 11810344Sandreas.hansson@arm.comvoid 11910344Sandreas.hansson@arm.comBaseCache::CacheSlavePort::processSendRetry() 12010344Sandreas.hansson@arm.com{ 12110714Sandreas.hansson@arm.com DPRINTF(CachePort, "Port is sending retry\n"); 12210344Sandreas.hansson@arm.com 12310344Sandreas.hansson@arm.com // reset the flag and call retry 12410344Sandreas.hansson@arm.com mustSendRetry = false; 12510713Sandreas.hansson@arm.com sendRetryReq(); 12610344Sandreas.hansson@arm.com} 1272844SN/A 1282810SN/Avoid 1292858SN/ABaseCache::init() 1302858SN/A{ 1318856Sandreas.hansson@arm.com if (!cpuSidePort->isConnected() || !memSidePort->isConnected()) 1328922Swilliam.wang@arm.com fatal("Cache ports on %s are not connected\n", name()); 1338711Sandreas.hansson@arm.com cpuSidePort->sendRangeChange(); 1342858SN/A} 1352858SN/A 1369294Sandreas.hansson@arm.comBaseMasterPort & 1379294Sandreas.hansson@arm.comBaseCache::getMasterPort(const std::string &if_name, PortID idx) 1388922Swilliam.wang@arm.com{ 1398922Swilliam.wang@arm.com if (if_name == "mem_side") { 1408922Swilliam.wang@arm.com return *memSidePort; 1418922Swilliam.wang@arm.com } else { 1428922Swilliam.wang@arm.com return MemObject::getMasterPort(if_name, idx); 1438922Swilliam.wang@arm.com } 1448922Swilliam.wang@arm.com} 1458922Swilliam.wang@arm.com 1469294Sandreas.hansson@arm.comBaseSlavePort & 1479294Sandreas.hansson@arm.comBaseCache::getSlavePort(const std::string &if_name, PortID idx) 1488922Swilliam.wang@arm.com{ 1498922Swilliam.wang@arm.com if (if_name == "cpu_side") { 1508922Swilliam.wang@arm.com return *cpuSidePort; 1518922Swilliam.wang@arm.com } else { 1528922Swilliam.wang@arm.com return MemObject::getSlavePort(if_name, idx); 1538922Swilliam.wang@arm.com } 1548922Swilliam.wang@arm.com} 1554628SN/A 1562858SN/Avoid 1572810SN/ABaseCache::regStats() 1582810SN/A{ 1592810SN/A using namespace Stats; 1602810SN/A 1612810SN/A // Hit statistics 1624022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 1634022SN/A MemCmd cmd(access_idx); 1644022SN/A const string &cstr = cmd.toString(); 1652810SN/A 1662810SN/A hits[access_idx] 1678833Sdam.sunwoo@arm.com .init(system->maxMasters()) 1682810SN/A .name(name() + "." + cstr + "_hits") 1692810SN/A .desc("number of " + cstr + " hits") 1702810SN/A .flags(total | nozero | nonan) 1712810SN/A ; 1728833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1738833Sdam.sunwoo@arm.com hits[access_idx].subname(i, system->getMasterName(i)); 1748833Sdam.sunwoo@arm.com } 1752810SN/A } 1762810SN/A 1774871SN/A// These macros make it easier to sum the right subset of commands and 1784871SN/A// to change the subset of commands that are considered "demand" vs 1794871SN/A// "non-demand" 1804871SN/A#define SUM_DEMAND(s) \ 1814871SN/A (s[MemCmd::ReadReq] + s[MemCmd::WriteReq] + s[MemCmd::ReadExReq]) 1824871SN/A 1834871SN/A// should writebacks be included here? prior code was inconsistent... 1844871SN/A#define SUM_NON_DEMAND(s) \ 1854871SN/A (s[MemCmd::SoftPFReq] + s[MemCmd::HardPFReq]) 1864871SN/A 1872810SN/A demandHits 1882810SN/A .name(name() + ".demand_hits") 1892810SN/A .desc("number of demand (read+write) hits") 1908833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1912810SN/A ; 1924871SN/A demandHits = SUM_DEMAND(hits); 1938833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 1948833Sdam.sunwoo@arm.com demandHits.subname(i, system->getMasterName(i)); 1958833Sdam.sunwoo@arm.com } 1962810SN/A 1972810SN/A overallHits 1982810SN/A .name(name() + ".overall_hits") 1992810SN/A .desc("number of overall hits") 2008833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2012810SN/A ; 2024871SN/A overallHits = demandHits + SUM_NON_DEMAND(hits); 2038833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2048833Sdam.sunwoo@arm.com overallHits.subname(i, system->getMasterName(i)); 2058833Sdam.sunwoo@arm.com } 2062810SN/A 2072810SN/A // Miss statistics 2084022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2094022SN/A MemCmd cmd(access_idx); 2104022SN/A const string &cstr = cmd.toString(); 2112810SN/A 2122810SN/A misses[access_idx] 2138833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2142810SN/A .name(name() + "." + cstr + "_misses") 2152810SN/A .desc("number of " + cstr + " misses") 2162810SN/A .flags(total | nozero | nonan) 2172810SN/A ; 2188833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2198833Sdam.sunwoo@arm.com misses[access_idx].subname(i, system->getMasterName(i)); 2208833Sdam.sunwoo@arm.com } 2212810SN/A } 2222810SN/A 2232810SN/A demandMisses 2242810SN/A .name(name() + ".demand_misses") 2252810SN/A .desc("number of demand (read+write) misses") 2268833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2272810SN/A ; 2284871SN/A demandMisses = SUM_DEMAND(misses); 2298833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2308833Sdam.sunwoo@arm.com demandMisses.subname(i, system->getMasterName(i)); 2318833Sdam.sunwoo@arm.com } 2322810SN/A 2332810SN/A overallMisses 2342810SN/A .name(name() + ".overall_misses") 2352810SN/A .desc("number of overall misses") 2368833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2372810SN/A ; 2384871SN/A overallMisses = demandMisses + SUM_NON_DEMAND(misses); 2398833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2408833Sdam.sunwoo@arm.com overallMisses.subname(i, system->getMasterName(i)); 2418833Sdam.sunwoo@arm.com } 2422810SN/A 2432810SN/A // Miss latency statistics 2444022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2454022SN/A MemCmd cmd(access_idx); 2464022SN/A const string &cstr = cmd.toString(); 2472810SN/A 2482810SN/A missLatency[access_idx] 2498833Sdam.sunwoo@arm.com .init(system->maxMasters()) 2502810SN/A .name(name() + "." + cstr + "_miss_latency") 2512810SN/A .desc("number of " + cstr + " miss cycles") 2522810SN/A .flags(total | nozero | nonan) 2532810SN/A ; 2548833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2558833Sdam.sunwoo@arm.com missLatency[access_idx].subname(i, system->getMasterName(i)); 2568833Sdam.sunwoo@arm.com } 2572810SN/A } 2582810SN/A 2592810SN/A demandMissLatency 2602810SN/A .name(name() + ".demand_miss_latency") 2612810SN/A .desc("number of demand (read+write) miss cycles") 2628833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2632810SN/A ; 2644871SN/A demandMissLatency = SUM_DEMAND(missLatency); 2658833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2668833Sdam.sunwoo@arm.com demandMissLatency.subname(i, system->getMasterName(i)); 2678833Sdam.sunwoo@arm.com } 2682810SN/A 2692810SN/A overallMissLatency 2702810SN/A .name(name() + ".overall_miss_latency") 2712810SN/A .desc("number of overall miss cycles") 2728833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 2732810SN/A ; 2744871SN/A overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); 2758833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2768833Sdam.sunwoo@arm.com overallMissLatency.subname(i, system->getMasterName(i)); 2778833Sdam.sunwoo@arm.com } 2782810SN/A 2792810SN/A // access formulas 2804022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 2814022SN/A MemCmd cmd(access_idx); 2824022SN/A const string &cstr = cmd.toString(); 2832810SN/A 2842810SN/A accesses[access_idx] 2852810SN/A .name(name() + "." + cstr + "_accesses") 2862810SN/A .desc("number of " + cstr + " accesses(hits+misses)") 2872810SN/A .flags(total | nozero | nonan) 2882810SN/A ; 2898833Sdam.sunwoo@arm.com accesses[access_idx] = hits[access_idx] + misses[access_idx]; 2902810SN/A 2918833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 2928833Sdam.sunwoo@arm.com accesses[access_idx].subname(i, system->getMasterName(i)); 2938833Sdam.sunwoo@arm.com } 2942810SN/A } 2952810SN/A 2962810SN/A demandAccesses 2972810SN/A .name(name() + ".demand_accesses") 2982810SN/A .desc("number of demand (read+write) accesses") 2998833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3002810SN/A ; 3012810SN/A demandAccesses = demandHits + demandMisses; 3028833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3038833Sdam.sunwoo@arm.com demandAccesses.subname(i, system->getMasterName(i)); 3048833Sdam.sunwoo@arm.com } 3052810SN/A 3062810SN/A overallAccesses 3072810SN/A .name(name() + ".overall_accesses") 3082810SN/A .desc("number of overall (read+write) accesses") 3098833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3102810SN/A ; 3112810SN/A overallAccesses = overallHits + overallMisses; 3128833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3138833Sdam.sunwoo@arm.com overallAccesses.subname(i, system->getMasterName(i)); 3148833Sdam.sunwoo@arm.com } 3152810SN/A 3162810SN/A // miss rate formulas 3174022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3184022SN/A MemCmd cmd(access_idx); 3194022SN/A const string &cstr = cmd.toString(); 3202810SN/A 3212810SN/A missRate[access_idx] 3222810SN/A .name(name() + "." + cstr + "_miss_rate") 3232810SN/A .desc("miss rate for " + cstr + " accesses") 3242810SN/A .flags(total | nozero | nonan) 3252810SN/A ; 3268833Sdam.sunwoo@arm.com missRate[access_idx] = misses[access_idx] / accesses[access_idx]; 3272810SN/A 3288833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3298833Sdam.sunwoo@arm.com missRate[access_idx].subname(i, system->getMasterName(i)); 3308833Sdam.sunwoo@arm.com } 3312810SN/A } 3322810SN/A 3332810SN/A demandMissRate 3342810SN/A .name(name() + ".demand_miss_rate") 3352810SN/A .desc("miss rate for demand accesses") 3368833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3372810SN/A ; 3382810SN/A demandMissRate = demandMisses / demandAccesses; 3398833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3408833Sdam.sunwoo@arm.com demandMissRate.subname(i, system->getMasterName(i)); 3418833Sdam.sunwoo@arm.com } 3422810SN/A 3432810SN/A overallMissRate 3442810SN/A .name(name() + ".overall_miss_rate") 3452810SN/A .desc("miss rate for overall accesses") 3468833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3472810SN/A ; 3482810SN/A overallMissRate = overallMisses / overallAccesses; 3498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3508833Sdam.sunwoo@arm.com overallMissRate.subname(i, system->getMasterName(i)); 3518833Sdam.sunwoo@arm.com } 3522810SN/A 3532810SN/A // miss latency formulas 3544022SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 3554022SN/A MemCmd cmd(access_idx); 3564022SN/A const string &cstr = cmd.toString(); 3572810SN/A 3582810SN/A avgMissLatency[access_idx] 3592810SN/A .name(name() + "." + cstr + "_avg_miss_latency") 3602810SN/A .desc("average " + cstr + " miss latency") 3612810SN/A .flags(total | nozero | nonan) 3622810SN/A ; 3632810SN/A avgMissLatency[access_idx] = 3642810SN/A missLatency[access_idx] / misses[access_idx]; 3658833Sdam.sunwoo@arm.com 3668833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3678833Sdam.sunwoo@arm.com avgMissLatency[access_idx].subname(i, system->getMasterName(i)); 3688833Sdam.sunwoo@arm.com } 3692810SN/A } 3702810SN/A 3712810SN/A demandAvgMissLatency 3722810SN/A .name(name() + ".demand_avg_miss_latency") 3732810SN/A .desc("average overall miss latency") 3748833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3752810SN/A ; 3762810SN/A demandAvgMissLatency = demandMissLatency / demandMisses; 3778833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3788833Sdam.sunwoo@arm.com demandAvgMissLatency.subname(i, system->getMasterName(i)); 3798833Sdam.sunwoo@arm.com } 3802810SN/A 3812810SN/A overallAvgMissLatency 3822810SN/A .name(name() + ".overall_avg_miss_latency") 3832810SN/A .desc("average overall miss latency") 3848833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 3852810SN/A ; 3862810SN/A overallAvgMissLatency = overallMissLatency / overallMisses; 3878833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 3888833Sdam.sunwoo@arm.com overallAvgMissLatency.subname(i, system->getMasterName(i)); 3898833Sdam.sunwoo@arm.com } 3902810SN/A 3912810SN/A blocked_cycles.init(NUM_BLOCKED_CAUSES); 3922810SN/A blocked_cycles 3932810SN/A .name(name() + ".blocked_cycles") 3942810SN/A .desc("number of cycles access was blocked") 3952810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 3962810SN/A .subname(Blocked_NoTargets, "no_targets") 3972810SN/A ; 3982810SN/A 3992810SN/A 4002810SN/A blocked_causes.init(NUM_BLOCKED_CAUSES); 4012810SN/A blocked_causes 4022810SN/A .name(name() + ".blocked") 4032810SN/A .desc("number of cycles access was blocked") 4042810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4052810SN/A .subname(Blocked_NoTargets, "no_targets") 4062810SN/A ; 4072810SN/A 4082810SN/A avg_blocked 4092810SN/A .name(name() + ".avg_blocked_cycles") 4102810SN/A .desc("average number of cycles each access was blocked") 4112810SN/A .subname(Blocked_NoMSHRs, "no_mshrs") 4122810SN/A .subname(Blocked_NoTargets, "no_targets") 4132810SN/A ; 4142810SN/A 4152810SN/A avg_blocked = blocked_cycles / blocked_causes; 4162810SN/A 4172810SN/A fastWrites 4182810SN/A .name(name() + ".fast_writes") 4192810SN/A .desc("number of fast writes performed") 4202810SN/A ; 4212810SN/A 4222810SN/A cacheCopies 4232810SN/A .name(name() + ".cache_copies") 4242810SN/A .desc("number of cache copies performed") 4252810SN/A ; 4262826SN/A 4274626SN/A writebacks 4288833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4294626SN/A .name(name() + ".writebacks") 4304626SN/A .desc("number of writebacks") 4318833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4324626SN/A ; 4338833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4348833Sdam.sunwoo@arm.com writebacks.subname(i, system->getMasterName(i)); 4358833Sdam.sunwoo@arm.com } 4364626SN/A 4374626SN/A // MSHR statistics 4384626SN/A // MSHR hit statistics 4394626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4404626SN/A MemCmd cmd(access_idx); 4414626SN/A const string &cstr = cmd.toString(); 4424626SN/A 4434626SN/A mshr_hits[access_idx] 4448833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4454626SN/A .name(name() + "." + cstr + "_mshr_hits") 4464626SN/A .desc("number of " + cstr + " MSHR hits") 4474626SN/A .flags(total | nozero | nonan) 4484626SN/A ; 4498833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4508833Sdam.sunwoo@arm.com mshr_hits[access_idx].subname(i, system->getMasterName(i)); 4518833Sdam.sunwoo@arm.com } 4524626SN/A } 4534626SN/A 4544626SN/A demandMshrHits 4554626SN/A .name(name() + ".demand_mshr_hits") 4564626SN/A .desc("number of demand (read+write) MSHR hits") 4578833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4584626SN/A ; 4594871SN/A demandMshrHits = SUM_DEMAND(mshr_hits); 4608833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4618833Sdam.sunwoo@arm.com demandMshrHits.subname(i, system->getMasterName(i)); 4628833Sdam.sunwoo@arm.com } 4634626SN/A 4644626SN/A overallMshrHits 4654626SN/A .name(name() + ".overall_mshr_hits") 4664626SN/A .desc("number of overall MSHR hits") 4678833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4684626SN/A ; 4694871SN/A overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); 4708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4718833Sdam.sunwoo@arm.com overallMshrHits.subname(i, system->getMasterName(i)); 4728833Sdam.sunwoo@arm.com } 4734626SN/A 4744626SN/A // MSHR miss statistics 4754626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 4764626SN/A MemCmd cmd(access_idx); 4774626SN/A const string &cstr = cmd.toString(); 4784626SN/A 4794626SN/A mshr_misses[access_idx] 4808833Sdam.sunwoo@arm.com .init(system->maxMasters()) 4814626SN/A .name(name() + "." + cstr + "_mshr_misses") 4824626SN/A .desc("number of " + cstr + " MSHR misses") 4834626SN/A .flags(total | nozero | nonan) 4844626SN/A ; 4858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4868833Sdam.sunwoo@arm.com mshr_misses[access_idx].subname(i, system->getMasterName(i)); 4878833Sdam.sunwoo@arm.com } 4884626SN/A } 4894626SN/A 4904626SN/A demandMshrMisses 4914626SN/A .name(name() + ".demand_mshr_misses") 4924626SN/A .desc("number of demand (read+write) MSHR misses") 4938833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 4944626SN/A ; 4954871SN/A demandMshrMisses = SUM_DEMAND(mshr_misses); 4968833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 4978833Sdam.sunwoo@arm.com demandMshrMisses.subname(i, system->getMasterName(i)); 4988833Sdam.sunwoo@arm.com } 4994626SN/A 5004626SN/A overallMshrMisses 5014626SN/A .name(name() + ".overall_mshr_misses") 5024626SN/A .desc("number of overall MSHR misses") 5038833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5044626SN/A ; 5054871SN/A overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); 5068833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5078833Sdam.sunwoo@arm.com overallMshrMisses.subname(i, system->getMasterName(i)); 5088833Sdam.sunwoo@arm.com } 5094626SN/A 5104626SN/A // MSHR miss latency statistics 5114626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5124626SN/A MemCmd cmd(access_idx); 5134626SN/A const string &cstr = cmd.toString(); 5144626SN/A 5154626SN/A mshr_miss_latency[access_idx] 5168833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5174626SN/A .name(name() + "." + cstr + "_mshr_miss_latency") 5184626SN/A .desc("number of " + cstr + " MSHR miss cycles") 5194626SN/A .flags(total | nozero | nonan) 5204626SN/A ; 5218833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5228833Sdam.sunwoo@arm.com mshr_miss_latency[access_idx].subname(i, system->getMasterName(i)); 5238833Sdam.sunwoo@arm.com } 5244626SN/A } 5254626SN/A 5264626SN/A demandMshrMissLatency 5274626SN/A .name(name() + ".demand_mshr_miss_latency") 5284626SN/A .desc("number of demand (read+write) MSHR miss cycles") 5298833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5304626SN/A ; 5314871SN/A demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); 5328833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5338833Sdam.sunwoo@arm.com demandMshrMissLatency.subname(i, system->getMasterName(i)); 5348833Sdam.sunwoo@arm.com } 5354626SN/A 5364626SN/A overallMshrMissLatency 5374626SN/A .name(name() + ".overall_mshr_miss_latency") 5384626SN/A .desc("number of overall MSHR miss cycles") 5398833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5404626SN/A ; 5414871SN/A overallMshrMissLatency = 5424871SN/A demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); 5438833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5448833Sdam.sunwoo@arm.com overallMshrMissLatency.subname(i, system->getMasterName(i)); 5458833Sdam.sunwoo@arm.com } 5464626SN/A 5474626SN/A // MSHR uncacheable statistics 5484626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5494626SN/A MemCmd cmd(access_idx); 5504626SN/A const string &cstr = cmd.toString(); 5514626SN/A 5524626SN/A mshr_uncacheable[access_idx] 5538833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5544626SN/A .name(name() + "." + cstr + "_mshr_uncacheable") 5554626SN/A .desc("number of " + cstr + " MSHR uncacheable") 5564626SN/A .flags(total | nozero | nonan) 5574626SN/A ; 5588833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5598833Sdam.sunwoo@arm.com mshr_uncacheable[access_idx].subname(i, system->getMasterName(i)); 5608833Sdam.sunwoo@arm.com } 5614626SN/A } 5624626SN/A 5634626SN/A overallMshrUncacheable 5644626SN/A .name(name() + ".overall_mshr_uncacheable_misses") 5654626SN/A .desc("number of overall MSHR uncacheable misses") 5668833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5674626SN/A ; 5684871SN/A overallMshrUncacheable = 5694871SN/A SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); 5708833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5718833Sdam.sunwoo@arm.com overallMshrUncacheable.subname(i, system->getMasterName(i)); 5728833Sdam.sunwoo@arm.com } 5734626SN/A 5744626SN/A // MSHR miss latency statistics 5754626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 5764626SN/A MemCmd cmd(access_idx); 5774626SN/A const string &cstr = cmd.toString(); 5784626SN/A 5794626SN/A mshr_uncacheable_lat[access_idx] 5808833Sdam.sunwoo@arm.com .init(system->maxMasters()) 5814626SN/A .name(name() + "." + cstr + "_mshr_uncacheable_latency") 5824626SN/A .desc("number of " + cstr + " MSHR uncacheable cycles") 5834626SN/A .flags(total | nozero | nonan) 5844626SN/A ; 5858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5868833Sdam.sunwoo@arm.com mshr_uncacheable_lat[access_idx].subname(i, system->getMasterName(i)); 5878833Sdam.sunwoo@arm.com } 5884626SN/A } 5894626SN/A 5904626SN/A overallMshrUncacheableLatency 5914626SN/A .name(name() + ".overall_mshr_uncacheable_latency") 5924626SN/A .desc("number of overall MSHR uncacheable cycles") 5938833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 5944626SN/A ; 5954871SN/A overallMshrUncacheableLatency = 5964871SN/A SUM_DEMAND(mshr_uncacheable_lat) + 5974871SN/A SUM_NON_DEMAND(mshr_uncacheable_lat); 5988833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 5998833Sdam.sunwoo@arm.com overallMshrUncacheableLatency.subname(i, system->getMasterName(i)); 6008833Sdam.sunwoo@arm.com } 6014626SN/A 6024626SN/A#if 0 6034626SN/A // MSHR access formulas 6044626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6054626SN/A MemCmd cmd(access_idx); 6064626SN/A const string &cstr = cmd.toString(); 6074626SN/A 6084626SN/A mshrAccesses[access_idx] 6094626SN/A .name(name() + "." + cstr + "_mshr_accesses") 6104626SN/A .desc("number of " + cstr + " mshr accesses(hits+misses)") 6114626SN/A .flags(total | nozero | nonan) 6124626SN/A ; 6134626SN/A mshrAccesses[access_idx] = 6144626SN/A mshr_hits[access_idx] + mshr_misses[access_idx] 6154626SN/A + mshr_uncacheable[access_idx]; 6164626SN/A } 6174626SN/A 6184626SN/A demandMshrAccesses 6194626SN/A .name(name() + ".demand_mshr_accesses") 6204626SN/A .desc("number of demand (read+write) mshr accesses") 6214626SN/A .flags(total | nozero | nonan) 6224626SN/A ; 6234626SN/A demandMshrAccesses = demandMshrHits + demandMshrMisses; 6244626SN/A 6254626SN/A overallMshrAccesses 6264626SN/A .name(name() + ".overall_mshr_accesses") 6274626SN/A .desc("number of overall (read+write) mshr accesses") 6284626SN/A .flags(total | nozero | nonan) 6294626SN/A ; 6304626SN/A overallMshrAccesses = overallMshrHits + overallMshrMisses 6314626SN/A + overallMshrUncacheable; 6324626SN/A#endif 6334626SN/A 6344626SN/A // MSHR miss rate formulas 6354626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6364626SN/A MemCmd cmd(access_idx); 6374626SN/A const string &cstr = cmd.toString(); 6384626SN/A 6394626SN/A mshrMissRate[access_idx] 6404626SN/A .name(name() + "." + cstr + "_mshr_miss_rate") 6414626SN/A .desc("mshr miss rate for " + cstr + " accesses") 6424626SN/A .flags(total | nozero | nonan) 6434626SN/A ; 6444626SN/A mshrMissRate[access_idx] = 6454626SN/A mshr_misses[access_idx] / accesses[access_idx]; 6468833Sdam.sunwoo@arm.com 6478833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6488833Sdam.sunwoo@arm.com mshrMissRate[access_idx].subname(i, system->getMasterName(i)); 6498833Sdam.sunwoo@arm.com } 6504626SN/A } 6514626SN/A 6524626SN/A demandMshrMissRate 6534626SN/A .name(name() + ".demand_mshr_miss_rate") 6544626SN/A .desc("mshr miss rate for demand accesses") 6558833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6564626SN/A ; 6574626SN/A demandMshrMissRate = demandMshrMisses / demandAccesses; 6588833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6598833Sdam.sunwoo@arm.com demandMshrMissRate.subname(i, system->getMasterName(i)); 6608833Sdam.sunwoo@arm.com } 6614626SN/A 6624626SN/A overallMshrMissRate 6634626SN/A .name(name() + ".overall_mshr_miss_rate") 6644626SN/A .desc("mshr miss rate for overall accesses") 6658833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6664626SN/A ; 6674626SN/A overallMshrMissRate = overallMshrMisses / overallAccesses; 6688833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6698833Sdam.sunwoo@arm.com overallMshrMissRate.subname(i, system->getMasterName(i)); 6708833Sdam.sunwoo@arm.com } 6714626SN/A 6724626SN/A // mshrMiss latency formulas 6734626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 6744626SN/A MemCmd cmd(access_idx); 6754626SN/A const string &cstr = cmd.toString(); 6764626SN/A 6774626SN/A avgMshrMissLatency[access_idx] 6784626SN/A .name(name() + "." + cstr + "_avg_mshr_miss_latency") 6794626SN/A .desc("average " + cstr + " mshr miss latency") 6804626SN/A .flags(total | nozero | nonan) 6814626SN/A ; 6824626SN/A avgMshrMissLatency[access_idx] = 6834626SN/A mshr_miss_latency[access_idx] / mshr_misses[access_idx]; 6848833Sdam.sunwoo@arm.com 6858833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6868833Sdam.sunwoo@arm.com avgMshrMissLatency[access_idx].subname(i, system->getMasterName(i)); 6878833Sdam.sunwoo@arm.com } 6884626SN/A } 6894626SN/A 6904626SN/A demandAvgMshrMissLatency 6914626SN/A .name(name() + ".demand_avg_mshr_miss_latency") 6924626SN/A .desc("average overall mshr miss latency") 6938833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 6944626SN/A ; 6954626SN/A demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; 6968833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 6978833Sdam.sunwoo@arm.com demandAvgMshrMissLatency.subname(i, system->getMasterName(i)); 6988833Sdam.sunwoo@arm.com } 6994626SN/A 7004626SN/A overallAvgMshrMissLatency 7014626SN/A .name(name() + ".overall_avg_mshr_miss_latency") 7024626SN/A .desc("average overall mshr miss latency") 7038833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7044626SN/A ; 7054626SN/A overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; 7068833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7078833Sdam.sunwoo@arm.com overallAvgMshrMissLatency.subname(i, system->getMasterName(i)); 7088833Sdam.sunwoo@arm.com } 7094626SN/A 7104626SN/A // mshrUncacheable latency formulas 7114626SN/A for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { 7124626SN/A MemCmd cmd(access_idx); 7134626SN/A const string &cstr = cmd.toString(); 7144626SN/A 7154626SN/A avgMshrUncacheableLatency[access_idx] 7164626SN/A .name(name() + "." + cstr + "_avg_mshr_uncacheable_latency") 7174626SN/A .desc("average " + cstr + " mshr uncacheable latency") 7184626SN/A .flags(total | nozero | nonan) 7194626SN/A ; 7204626SN/A avgMshrUncacheableLatency[access_idx] = 7214626SN/A mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; 7228833Sdam.sunwoo@arm.com 7238833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7248833Sdam.sunwoo@arm.com avgMshrUncacheableLatency[access_idx].subname(i, system->getMasterName(i)); 7258833Sdam.sunwoo@arm.com } 7264626SN/A } 7274626SN/A 7284626SN/A overallAvgMshrUncacheableLatency 7294626SN/A .name(name() + ".overall_avg_mshr_uncacheable_latency") 7304626SN/A .desc("average overall mshr uncacheable latency") 7318833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7324626SN/A ; 7334626SN/A overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; 7348833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7358833Sdam.sunwoo@arm.com overallAvgMshrUncacheableLatency.subname(i, system->getMasterName(i)); 7368833Sdam.sunwoo@arm.com } 7374626SN/A 7384626SN/A mshr_cap_events 7398833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7404626SN/A .name(name() + ".mshr_cap_events") 7414626SN/A .desc("number of times MSHR cap was activated") 7428833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7434626SN/A ; 7448833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7458833Sdam.sunwoo@arm.com mshr_cap_events.subname(i, system->getMasterName(i)); 7468833Sdam.sunwoo@arm.com } 7474626SN/A 7484626SN/A //software prefetching stats 7494626SN/A soft_prefetch_mshr_full 7508833Sdam.sunwoo@arm.com .init(system->maxMasters()) 7514626SN/A .name(name() + ".soft_prefetch_mshr_full") 7524626SN/A .desc("number of mshr full events for SW prefetching instrutions") 7538833Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 7544626SN/A ; 7558833Sdam.sunwoo@arm.com for (int i = 0; i < system->maxMasters(); i++) { 7568833Sdam.sunwoo@arm.com soft_prefetch_mshr_full.subname(i, system->getMasterName(i)); 7578833Sdam.sunwoo@arm.com } 7584626SN/A 7594626SN/A mshr_no_allocate_misses 7604626SN/A .name(name() +".no_allocate_misses") 7614626SN/A .desc("Number of misses that were no-allocate") 7624626SN/A ; 7634626SN/A 7642810SN/A} 7653503SN/A 7663503SN/Aunsigned int 7679342SAndreas.Sandberg@arm.comBaseCache::drain(DrainManager *dm) 7683503SN/A{ 7699347SAndreas.Sandberg@arm.com int count = memSidePort->drain(dm) + cpuSidePort->drain(dm) + 7709347SAndreas.Sandberg@arm.com mshrQueue.drain(dm) + writeBuffer.drain(dm); 7714626SN/A 7723503SN/A // Set status 7734626SN/A if (count != 0) { 7749342SAndreas.Sandberg@arm.com setDrainState(Drainable::Draining); 7759152Satgutier@umich.edu DPRINTF(Drain, "Cache not drained\n"); 7764626SN/A return count; 7773503SN/A } 7783503SN/A 7799342SAndreas.Sandberg@arm.com setDrainState(Drainable::Drained); 7803503SN/A return 0; 7813503SN/A} 7829795Sandreas.hansson@arm.com 7839795Sandreas.hansson@arm.comBaseCache * 7849795Sandreas.hansson@arm.comBaseCacheParams::create() 7859795Sandreas.hansson@arm.com{ 7869796Sprakash.ramrakhyani@arm.com assert(tags); 7879796Sprakash.ramrakhyani@arm.com 78810815Sdavid.guillen@arm.com return new Cache(this); 7899795Sandreas.hansson@arm.com} 790