Cache.py revision 9288
1# Copyright (c) 2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2005-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Nathan Binkert 40 41from m5.params import * 42from m5.proxy import * 43from MemObject import MemObject 44from Prefetcher import BasePrefetcher 45 46 47class BaseCache(MemObject): 48 type = 'BaseCache' 49 assoc = Param.Int("associativity") 50 block_size = Param.Int("block size in bytes") 51 hit_latency = Param.Cycles("The hit latency for this cache") 52 response_latency = Param.Cycles( 53 "Additional cache latency for the return path to core on a miss"); 54 hash_delay = Param.Cycles(1, "time in cycles of hash access") 55 max_miss_count = Param.Counter(0, 56 "number of misses to handle before calling exit") 57 mshrs = Param.Int("number of MSHRs (max outstanding requests)") 58 prioritizeRequests = Param.Bool(False, 59 "always service demand misses first") 60 repl = Param.Repl(NULL, "replacement policy") 61 size = Param.MemorySize("capacity in bytes") 62 forward_snoops = Param.Bool(True, 63 "forward snoops from mem side to cpu side") 64 is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") 65 subblock_size = Param.Int(0, 66 "Size of subblock in IIC used for compression") 67 tgts_per_mshr = Param.Int("max number of accesses per MSHR") 68 trace_addr = Param.Addr(0, "address to trace") 69 two_queue = Param.Bool(False, 70 "whether the lifo should have two queue replacement") 71 write_buffers = Param.Int(8, "number of write buffers") 72 prefetch_on_access = Param.Bool(False, 73 "notify the hardware prefetcher on every access (not just misses)") 74 prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 75 cpu_side = SlavePort("Port on side closer to CPU") 76 mem_side = MasterPort("Port on side closer to MEM") 77 addr_ranges = VectorParam.AddrRange([AllMemory], "The address range for the CPU-side port") 78 system = Param.System(Parent.any, "System we belong to") 79