Cache.py revision 11722:f15f02d8c79e 
1# Copyright (c) 2012-2013, 2015 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder.  You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2005-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Nathan Binkert
40#          Andreas Hansson
41
42from m5.params import *
43from m5.proxy import *
44from MemObject import MemObject
45from Prefetcher import BasePrefetcher
46from Tags import *
47
48class BaseCache(MemObject):
49    type = 'BaseCache'
50    abstract = True
51    cxx_header = "mem/cache/base.hh"
52
53    size = Param.MemorySize("Capacity")
54    assoc = Param.Unsigned("Associativity")
55
56    tag_latency = Param.Cycles("Tag lookup latency")
57    data_latency = Param.Cycles("Data access latency")
58    response_latency = Param.Cycles("Latency for the return path on a miss");
59
60    max_miss_count = Param.Counter(0,
61        "Number of misses to handle before calling exit")
62
63    mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
64    demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
65    tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
66    write_buffers = Param.Unsigned(8, "Number of write buffers")
67
68    is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")
69
70    prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache")
71    prefetch_on_access = Param.Bool(False,
72         "Notify the hardware prefetcher on every access (not just misses)")
73
74    tags = Param.BaseTags(LRU(), "Tag store (replacement policy)")
75    sequential_access = Param.Bool(False,
76        "Whether to access tags and data sequentially")
77
78    cpu_side = SlavePort("Upstream port closer to the CPU and/or device")
79    mem_side = MasterPort("Downstream port closer to memory")
80
81    addr_ranges = VectorParam.AddrRange([AllMemory],
82         "Address range for the CPU-side port (to allow striping)")
83
84    system = Param.System(Parent.any, "System we belong to")
85
86# Enum for cache clusivity, currently mostly inclusive or mostly
87# exclusive.
88class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl']
89
90class Cache(BaseCache):
91    type = 'Cache'
92    cxx_header = 'mem/cache/cache.hh'
93
94    # Control whether this cache should be mostly inclusive or mostly
95    # exclusive with respect to upstream caches. The behaviour on a
96    # fill is determined accordingly. For a mostly inclusive cache,
97    # blocks are allocated on all fill operations. Thus, L1 caches
98    # should be set as mostly inclusive even if they have no upstream
99    # caches. In the case of a mostly exclusive cache, fills are not
100    # allocating unless they came directly from a non-caching source,
101    # e.g. a table walker. Additionally, on a hit from an upstream
102    # cache a line is dropped for a mostly exclusive cache.
103    clusivity = Param.Clusivity('mostly_incl',
104                                "Clusivity with upstream cache")
105
106    # Determine if this cache sends out writebacks for clean lines, or
107    # simply clean evicts. In cases where a downstream cache is mostly
108    # exclusive with respect to this cache (acting as a victim cache),
109    # the clean writebacks are essential for performance. In general
110    # this should be set to True for anything but the last-level
111    # cache.
112    writeback_clean = Param.Bool(False, "Writeback clean lines")
113