Cache.py revision 10816
12381SN/A# Copyright (c) 2012-2013, 2015 ARM Limited 22381SN/A# All rights reserved. 32381SN/A# 42381SN/A# The license below extends only to copyright in the software and shall 52381SN/A# not be construed as granting a license to any other intellectual 62381SN/A# property including but not limited to intellectual property relating 72381SN/A# to a hardware implementation of the functionality of the software 82381SN/A# licensed hereunder. You may use the software subject to the license 92381SN/A# terms below provided that you ensure that this notice is replicated 102381SN/A# unmodified and in its entirety in all distributions of the software, 112381SN/A# modified or unmodified, in source code or in binary form. 122381SN/A# 132381SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 142381SN/A# All rights reserved. 152381SN/A# 162381SN/A# Redistribution and use in source and binary forms, with or without 172381SN/A# modification, are permitted provided that the following conditions are 182381SN/A# met: redistributions of source code must retain the above copyright 192381SN/A# notice, this list of conditions and the following disclaimer; 202381SN/A# redistributions in binary form must reproduce the above copyright 212381SN/A# notice, this list of conditions and the following disclaimer in the 222381SN/A# documentation and/or other materials provided with the distribution; 232381SN/A# neither the name of the copyright holders nor the names of its 242381SN/A# contributors may be used to endorse or promote products derived from 252381SN/A# this software without specific prior written permission. 262381SN/A# 272381SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 282381SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 292381SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 302381SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 312381SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 322381SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 332381SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 342381SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 352381SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 362381SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 372423SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 382394SN/A# 392394SN/A# Authors: Nathan Binkert 402394SN/A 412394SN/Afrom m5.params import * 422394SN/Afrom m5.proxy import * 432395SN/Afrom MemObject import MemObject 442395SN/Afrom Prefetcher import BasePrefetcher 452395SN/Afrom Tags import * 462395SN/A 472395SN/Aclass BaseCache(MemObject): 482395SN/A type = 'BaseCache' 492395SN/A cxx_header = "mem/cache/base.hh" 502395SN/A 512395SN/A size = Param.MemorySize("Capacity") 522395SN/A assoc = Param.Unsigned("Associativity") 532395SN/A 542395SN/A hit_latency = Param.Cycles("Hit latency") 552397SN/A response_latency = Param.Cycles("Latency for the return path on a miss"); 562397SN/A 572397SN/A max_miss_count = Param.Counter(0, 582397SN/A "Number of misses to handle before calling exit") 592495SN/A 602495SN/A mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 612395SN/A demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 622381SN/A tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 632381SN/A write_buffers = Param.Unsigned(8, "Number of write buffers") 642394SN/A 652394SN/A forward_snoops = Param.Bool(True, 662548SN/A "Forward snoops from mem side to cpu side") 672532SN/A is_top_level = Param.Bool(False, "Is this cache at the top level (e.g. L1)") 682532SN/A 692559SN/A prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 702559SN/A prefetch_on_access = Param.Bool(False, 712559SN/A "Notify the hardware prefetcher on every access (not just misses)") 722559SN/A 732559SN/A tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") 742559SN/A sequential_access = Param.Bool(False, 752548SN/A "Whether to access tags and data sequentially") 762532SN/A 772532SN/A cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 782381SN/A mem_side = MasterPort("Downstream port closer to memory") 792381SN/A 802532SN/A addr_ranges = VectorParam.AddrRange([AllMemory], 812532SN/A "Address range for the CPU-side port (to allow striping)") 822381SN/A 832381SN/A system = Param.System(Parent.any, "System we belong to") 842381SN/A