Cache.py revision 13892
112726Snikos.nikoleris@arm.com# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 29288SN/A# All rights reserved. 39288SN/A# 49288SN/A# The license below extends only to copyright in the software and shall 59288SN/A# not be construed as granting a license to any other intellectual 69288SN/A# property including but not limited to intellectual property relating 79288SN/A# to a hardware implementation of the functionality of the software 89288SN/A# licensed hereunder. You may use the software subject to the license 99288SN/A# terms below provided that you ensure that this notice is replicated 109288SN/A# unmodified and in its entirety in all distributions of the software, 119288SN/A# modified or unmodified, in source code or in binary form. 129288SN/A# 134486SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 394486SN/A# Authors: Nathan Binkert 4011053Sandreas.hansson@arm.com# Andreas Hansson 414486SN/A 423102SN/Afrom m5.params import * 438833SN/Afrom m5.proxy import * 4413352Snikos.nikoleris@arm.comfrom m5.SimObject import SimObject 4513665Sandreas.sandberg@arm.com 4613892Sgabeblack@google.comfrom m5.objects.ClockedObject import ClockedObject 4713665Sandreas.sandberg@arm.comfrom m5.objects.Prefetcher import BasePrefetcher 4813665Sandreas.sandberg@arm.comfrom m5.objects.ReplacementPolicies import * 4913665Sandreas.sandberg@arm.comfrom m5.objects.Tags import * 501615SN/A 5112724Snikos.nikoleris@arm.com 5212724Snikos.nikoleris@arm.com# Enum for cache clusivity, currently mostly inclusive or mostly 5312724Snikos.nikoleris@arm.com# exclusive. 5412724Snikos.nikoleris@arm.comclass Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 5512724Snikos.nikoleris@arm.com 5613352Snikos.nikoleris@arm.comclass WriteAllocator(SimObject): 5713352Snikos.nikoleris@arm.com type = 'WriteAllocator' 5813352Snikos.nikoleris@arm.com cxx_header = "mem/cache/cache.hh" 5913352Snikos.nikoleris@arm.com 6013352Snikos.nikoleris@arm.com # Control the limits for when the cache introduces extra delays to 6113352Snikos.nikoleris@arm.com # allow whole-line write coalescing, and eventually switches to a 6213352Snikos.nikoleris@arm.com # write-no-allocate policy. 6313352Snikos.nikoleris@arm.com coalesce_limit = Param.Unsigned(2, "Consecutive lines written before " 6413352Snikos.nikoleris@arm.com "delaying for coalescing") 6513352Snikos.nikoleris@arm.com no_allocate_limit = Param.Unsigned(12, "Consecutive lines written before" 6613352Snikos.nikoleris@arm.com " skipping allocation") 6713352Snikos.nikoleris@arm.com 6813352Snikos.nikoleris@arm.com delay_threshold = Param.Unsigned(8, "Number of delay quanta imposed on an " 6913352Snikos.nikoleris@arm.com "MSHR with write requests to allow for " 7013352Snikos.nikoleris@arm.com "write coalescing") 7113352Snikos.nikoleris@arm.com 7213352Snikos.nikoleris@arm.com block_size = Param.Int(Parent.cache_line_size, "block size in bytes") 7313352Snikos.nikoleris@arm.com 7412724Snikos.nikoleris@arm.com 7513892Sgabeblack@google.comclass BaseCache(ClockedObject): 761366SN/A type = 'BaseCache' 7711053Sandreas.hansson@arm.com abstract = True 789338SN/A cxx_header = "mem/cache/base.hh" 7910816SN/A 8010816SN/A size = Param.MemorySize("Capacity") 8110816SN/A assoc = Param.Unsigned("Associativity") 8210816SN/A 8311722Ssophiane.senni@gmail.com tag_latency = Param.Cycles("Tag lookup latency") 8411722Ssophiane.senni@gmail.com data_latency = Param.Cycles("Data access latency") 8510816SN/A response_latency = Param.Cycles("Latency for the return path on a miss"); 8610816SN/A 8712513Sodanrc@yahoo.com.br warmup_percentage = Param.Percent(0, 8812513Sodanrc@yahoo.com.br "Percentage of tags to be touched to warm up the cache") 8912513Sodanrc@yahoo.com.br 901310SN/A max_miss_count = Param.Counter(0, 9110816SN/A "Number of misses to handle before calling exit") 9210816SN/A 9310816SN/A mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 9410816SN/A demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 9510816SN/A tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 9610816SN/A write_buffers = Param.Unsigned(8, "Number of write buffers") 9710816SN/A 9810884SN/A is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 9910816SN/A 10010816SN/A prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 1015875SN/A prefetch_on_access = Param.Bool(False, 10210816SN/A "Notify the hardware prefetcher on every access (not just misses)") 10310816SN/A 10412600Sodanrc@yahoo.com.br tags = Param.BaseTags(BaseSetAssoc(), "Tag store") 10512600Sodanrc@yahoo.com.br replacement_policy = Param.BaseReplacementPolicy(LRURP(), 10612600Sodanrc@yahoo.com.br "Replacement policy") 10712600Sodanrc@yahoo.com.br 10810025SN/A sequential_access = Param.Bool(False, 10910025SN/A "Whether to access tags and data sequentially") 11010816SN/A 11110816SN/A cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 11210816SN/A mem_side = MasterPort("Downstream port closer to memory") 11310816SN/A 11410816SN/A addr_ranges = VectorParam.AddrRange([AllMemory], 11510816SN/A "Address range for the CPU-side port (to allow striping)") 11610816SN/A 11710816SN/A system = Param.System(Parent.any, "System we belong to") 11811053Sandreas.hansson@arm.com 11912724Snikos.nikoleris@arm.com # Determine if this cache sends out writebacks for clean lines, or 12012724Snikos.nikoleris@arm.com # simply clean evicts. In cases where a downstream cache is mostly 12112724Snikos.nikoleris@arm.com # exclusive with respect to this cache (acting as a victim cache), 12212724Snikos.nikoleris@arm.com # the clean writebacks are essential for performance. In general 12312724Snikos.nikoleris@arm.com # this should be set to True for anything but the last-level 12412724Snikos.nikoleris@arm.com # cache. 12512724Snikos.nikoleris@arm.com writeback_clean = Param.Bool(False, "Writeback clean lines") 12611197Sandreas.hansson@arm.com 12711197Sandreas.hansson@arm.com # Control whether this cache should be mostly inclusive or mostly 12811197Sandreas.hansson@arm.com # exclusive with respect to upstream caches. The behaviour on a 12911197Sandreas.hansson@arm.com # fill is determined accordingly. For a mostly inclusive cache, 13011197Sandreas.hansson@arm.com # blocks are allocated on all fill operations. Thus, L1 caches 13111197Sandreas.hansson@arm.com # should be set as mostly inclusive even if they have no upstream 13211197Sandreas.hansson@arm.com # caches. In the case of a mostly exclusive cache, fills are not 13311197Sandreas.hansson@arm.com # allocating unless they came directly from a non-caching source, 13411197Sandreas.hansson@arm.com # e.g. a table walker. Additionally, on a hit from an upstream 13511197Sandreas.hansson@arm.com # cache a line is dropped for a mostly exclusive cache. 13611197Sandreas.hansson@arm.com clusivity = Param.Clusivity('mostly_incl', 13711197Sandreas.hansson@arm.com "Clusivity with upstream cache") 13811199Sandreas.hansson@arm.com 13913352Snikos.nikoleris@arm.com # The write allocator enables optimizations for streaming write 14013352Snikos.nikoleris@arm.com # accesses by first coalescing writes and then avoiding allocation 14113352Snikos.nikoleris@arm.com # in the current cache. Typically, this would be enabled in the 14213352Snikos.nikoleris@arm.com # data cache. 14313352Snikos.nikoleris@arm.com write_allocator = Param.WriteAllocator(NULL, "Write allocator") 14412724Snikos.nikoleris@arm.com 14512724Snikos.nikoleris@arm.comclass Cache(BaseCache): 14612724Snikos.nikoleris@arm.com type = 'Cache' 14712724Snikos.nikoleris@arm.com cxx_header = 'mem/cache/cache.hh' 14812726Snikos.nikoleris@arm.com 14912726Snikos.nikoleris@arm.com 15012726Snikos.nikoleris@arm.comclass NoncoherentCache(BaseCache): 15112726Snikos.nikoleris@arm.com type = 'NoncoherentCache' 15212726Snikos.nikoleris@arm.com cxx_header = 'mem/cache/noncoherent_cache.hh' 15312726Snikos.nikoleris@arm.com 15412726Snikos.nikoleris@arm.com # This is typically a last level cache and any clean 15512726Snikos.nikoleris@arm.com # writebacks would be unnecessary traffic to the main memory. 15612726Snikos.nikoleris@arm.com writeback_clean = False 15712726Snikos.nikoleris@arm.com 158