Cache.py revision 12726
112726Snikos.nikoleris@arm.com# Copyright (c) 2012-2013, 2015, 2018 ARM Limited 29288SN/A# All rights reserved. 39288SN/A# 49288SN/A# The license below extends only to copyright in the software and shall 59288SN/A# not be construed as granting a license to any other intellectual 69288SN/A# property including but not limited to intellectual property relating 79288SN/A# to a hardware implementation of the functionality of the software 89288SN/A# licensed hereunder. You may use the software subject to the license 99288SN/A# terms below provided that you ensure that this notice is replicated 109288SN/A# unmodified and in its entirety in all distributions of the software, 119288SN/A# modified or unmodified, in source code or in binary form. 129288SN/A# 134486SN/A# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486SN/A# All rights reserved. 154486SN/A# 164486SN/A# Redistribution and use in source and binary forms, with or without 174486SN/A# modification, are permitted provided that the following conditions are 184486SN/A# met: redistributions of source code must retain the above copyright 194486SN/A# notice, this list of conditions and the following disclaimer; 204486SN/A# redistributions in binary form must reproduce the above copyright 214486SN/A# notice, this list of conditions and the following disclaimer in the 224486SN/A# documentation and/or other materials provided with the distribution; 234486SN/A# neither the name of the copyright holders nor the names of its 244486SN/A# contributors may be used to endorse or promote products derived from 254486SN/A# this software without specific prior written permission. 264486SN/A# 274486SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486SN/A# 394486SN/A# Authors: Nathan Binkert 4011053Sandreas.hansson@arm.com# Andreas Hansson 414486SN/A 423102SN/Afrom m5.params import * 438833SN/Afrom m5.proxy import * 442826SN/Afrom MemObject import MemObject 458831SN/Afrom Prefetcher import BasePrefetcher 4612600Sodanrc@yahoo.com.brfrom ReplacementPolicies import * 479796SN/Afrom Tags import * 481615SN/A 4912724Snikos.nikoleris@arm.com 5012724Snikos.nikoleris@arm.com# Enum for cache clusivity, currently mostly inclusive or mostly 5112724Snikos.nikoleris@arm.com# exclusive. 5212724Snikos.nikoleris@arm.comclass Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 5312724Snikos.nikoleris@arm.com 5412724Snikos.nikoleris@arm.com 552826SN/Aclass BaseCache(MemObject): 561366SN/A type = 'BaseCache' 5711053Sandreas.hansson@arm.com abstract = True 589338SN/A cxx_header = "mem/cache/base.hh" 5910816SN/A 6010816SN/A size = Param.MemorySize("Capacity") 6110816SN/A assoc = Param.Unsigned("Associativity") 6210816SN/A 6311722Ssophiane.senni@gmail.com tag_latency = Param.Cycles("Tag lookup latency") 6411722Ssophiane.senni@gmail.com data_latency = Param.Cycles("Data access latency") 6510816SN/A response_latency = Param.Cycles("Latency for the return path on a miss"); 6610816SN/A 6712513Sodanrc@yahoo.com.br warmup_percentage = Param.Percent(0, 6812513Sodanrc@yahoo.com.br "Percentage of tags to be touched to warm up the cache") 6912513Sodanrc@yahoo.com.br 701310SN/A max_miss_count = Param.Counter(0, 7110816SN/A "Number of misses to handle before calling exit") 7210816SN/A 7310816SN/A mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 7410816SN/A demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 7510816SN/A tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 7610816SN/A write_buffers = Param.Unsigned(8, "Number of write buffers") 7710816SN/A 7810884SN/A is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 7910816SN/A 8010816SN/A prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 815875SN/A prefetch_on_access = Param.Bool(False, 8210816SN/A "Notify the hardware prefetcher on every access (not just misses)") 8310816SN/A 8412600Sodanrc@yahoo.com.br tags = Param.BaseTags(BaseSetAssoc(), "Tag store") 8512600Sodanrc@yahoo.com.br replacement_policy = Param.BaseReplacementPolicy(LRURP(), 8612600Sodanrc@yahoo.com.br "Replacement policy") 8712600Sodanrc@yahoo.com.br 8810025SN/A sequential_access = Param.Bool(False, 8910025SN/A "Whether to access tags and data sequentially") 9010816SN/A 9110816SN/A cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 9210816SN/A mem_side = MasterPort("Downstream port closer to memory") 9310816SN/A 9410816SN/A addr_ranges = VectorParam.AddrRange([AllMemory], 9510816SN/A "Address range for the CPU-side port (to allow striping)") 9610816SN/A 9710816SN/A system = Param.System(Parent.any, "System we belong to") 9811053Sandreas.hansson@arm.com 9912724Snikos.nikoleris@arm.com # Determine if this cache sends out writebacks for clean lines, or 10012724Snikos.nikoleris@arm.com # simply clean evicts. In cases where a downstream cache is mostly 10112724Snikos.nikoleris@arm.com # exclusive with respect to this cache (acting as a victim cache), 10212724Snikos.nikoleris@arm.com # the clean writebacks are essential for performance. In general 10312724Snikos.nikoleris@arm.com # this should be set to True for anything but the last-level 10412724Snikos.nikoleris@arm.com # cache. 10512724Snikos.nikoleris@arm.com writeback_clean = Param.Bool(False, "Writeback clean lines") 10611197Sandreas.hansson@arm.com 10711197Sandreas.hansson@arm.com # Control whether this cache should be mostly inclusive or mostly 10811197Sandreas.hansson@arm.com # exclusive with respect to upstream caches. The behaviour on a 10911197Sandreas.hansson@arm.com # fill is determined accordingly. For a mostly inclusive cache, 11011197Sandreas.hansson@arm.com # blocks are allocated on all fill operations. Thus, L1 caches 11111197Sandreas.hansson@arm.com # should be set as mostly inclusive even if they have no upstream 11211197Sandreas.hansson@arm.com # caches. In the case of a mostly exclusive cache, fills are not 11311197Sandreas.hansson@arm.com # allocating unless they came directly from a non-caching source, 11411197Sandreas.hansson@arm.com # e.g. a table walker. Additionally, on a hit from an upstream 11511197Sandreas.hansson@arm.com # cache a line is dropped for a mostly exclusive cache. 11611197Sandreas.hansson@arm.com clusivity = Param.Clusivity('mostly_incl', 11711197Sandreas.hansson@arm.com "Clusivity with upstream cache") 11811199Sandreas.hansson@arm.com 11912724Snikos.nikoleris@arm.com 12012724Snikos.nikoleris@arm.comclass Cache(BaseCache): 12112724Snikos.nikoleris@arm.com type = 'Cache' 12212724Snikos.nikoleris@arm.com cxx_header = 'mem/cache/cache.hh' 12312726Snikos.nikoleris@arm.com 12412726Snikos.nikoleris@arm.com 12512726Snikos.nikoleris@arm.comclass NoncoherentCache(BaseCache): 12612726Snikos.nikoleris@arm.com type = 'NoncoherentCache' 12712726Snikos.nikoleris@arm.com cxx_header = 'mem/cache/noncoherent_cache.hh' 12812726Snikos.nikoleris@arm.com 12912726Snikos.nikoleris@arm.com # This is typically a last level cache and any clean 13012726Snikos.nikoleris@arm.com # writebacks would be unnecessary traffic to the main memory. 13112726Snikos.nikoleris@arm.com writeback_clean = False 13212726Snikos.nikoleris@arm.com 133