Cache.py revision 11722
113759Sgiacomo.gabrielli@arm.com# Copyright (c) 2012-2013, 2015 ARM Limited 27760SGiacomo.Gabrielli@arm.com# All rights reserved. 37760SGiacomo.Gabrielli@arm.com# 47760SGiacomo.Gabrielli@arm.com# The license below extends only to copyright in the software and shall 57760SGiacomo.Gabrielli@arm.com# not be construed as granting a license to any other intellectual 67760SGiacomo.Gabrielli@arm.com# property including but not limited to intellectual property relating 77760SGiacomo.Gabrielli@arm.com# to a hardware implementation of the functionality of the software 87760SGiacomo.Gabrielli@arm.com# licensed hereunder. You may use the software subject to the license 97760SGiacomo.Gabrielli@arm.com# terms below provided that you ensure that this notice is replicated 107760SGiacomo.Gabrielli@arm.com# unmodified and in its entirety in all distributions of the software, 117760SGiacomo.Gabrielli@arm.com# modified or unmodified, in source code or in binary form. 127760SGiacomo.Gabrielli@arm.com# 134486Sbinkertn@umich.edu# Copyright (c) 2005-2007 The Regents of The University of Michigan 144486Sbinkertn@umich.edu# All rights reserved. 154486Sbinkertn@umich.edu# 164486Sbinkertn@umich.edu# Redistribution and use in source and binary forms, with or without 174486Sbinkertn@umich.edu# modification, are permitted provided that the following conditions are 184486Sbinkertn@umich.edu# met: redistributions of source code must retain the above copyright 194486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer; 204486Sbinkertn@umich.edu# redistributions in binary form must reproduce the above copyright 214486Sbinkertn@umich.edu# notice, this list of conditions and the following disclaimer in the 224486Sbinkertn@umich.edu# documentation and/or other materials provided with the distribution; 234486Sbinkertn@umich.edu# neither the name of the copyright holders nor the names of its 244486Sbinkertn@umich.edu# contributors may be used to endorse or promote products derived from 254486Sbinkertn@umich.edu# this software without specific prior written permission. 264486Sbinkertn@umich.edu# 274486Sbinkertn@umich.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 284486Sbinkertn@umich.edu# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 294486Sbinkertn@umich.edu# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 304486Sbinkertn@umich.edu# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 314486Sbinkertn@umich.edu# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 324486Sbinkertn@umich.edu# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 334486Sbinkertn@umich.edu# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 344486Sbinkertn@umich.edu# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 354486Sbinkertn@umich.edu# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 364486Sbinkertn@umich.edu# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 374486Sbinkertn@umich.edu# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 384486Sbinkertn@umich.edu# 394486Sbinkertn@umich.edu# Authors: Nathan Binkert 404486Sbinkertn@umich.edu# Andreas Hansson 413102SN/A 423102SN/Afrom m5.params import * 432736SN/Afrom m5.proxy import * 444556Sbinkertn@umich.edufrom MemObject import MemObject 454556Sbinkertn@umich.edufrom Prefetcher import BasePrefetcher 4611683Sfernando.endo2@gmail.comfrom Tags import * 4711683Sfernando.endo2@gmail.com 487760SGiacomo.Gabrielli@arm.comclass BaseCache(MemObject): 497760SGiacomo.Gabrielli@arm.com type = 'BaseCache' 5013759Sgiacomo.gabrielli@arm.com abstract = True 5113759Sgiacomo.gabrielli@arm.com cxx_header = "mem/cache/base.hh" 5213759Sgiacomo.gabrielli@arm.com 5313759Sgiacomo.gabrielli@arm.com size = Param.MemorySize("Capacity") 5413759Sgiacomo.gabrielli@arm.com assoc = Param.Unsigned("Associativity") 5513169Smatt.horsnell@arm.com 5613169Smatt.horsnell@arm.com tag_latency = Param.Cycles("Tag lookup latency") 5713759Sgiacomo.gabrielli@arm.com data_latency = Param.Cycles("Data access latency") 5813759Sgiacomo.gabrielli@arm.com response_latency = Param.Cycles("Latency for the return path on a miss"); 5913759Sgiacomo.gabrielli@arm.com 6011683Sfernando.endo2@gmail.com max_miss_count = Param.Counter(0, 612736SN/A "Number of misses to handle before calling exit") 622736SN/A 632736SN/A mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)") 649338SAndreas.Sandberg@arm.com demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access") 654556Sbinkertn@umich.edu tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR") 669184Sandreas.hansson@arm.com write_buffers = Param.Unsigned(8, "Number of write buffers") 6710807Snilay@cs.wisc.edu 6810807Snilay@cs.wisc.edu is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)") 692736SN/A 702736SN/A prefetcher = Param.BasePrefetcher(NULL,"Prefetcher attached to cache") 712736SN/A prefetch_on_access = Param.Bool(False, 729338SAndreas.Sandberg@arm.com "Notify the hardware prefetcher on every access (not just misses)") 732736SN/A 742736SN/A tags = Param.BaseTags(LRU(), "Tag store (replacement policy)") 75 sequential_access = Param.Bool(False, 76 "Whether to access tags and data sequentially") 77 78 cpu_side = SlavePort("Upstream port closer to the CPU and/or device") 79 mem_side = MasterPort("Downstream port closer to memory") 80 81 addr_ranges = VectorParam.AddrRange([AllMemory], 82 "Address range for the CPU-side port (to allow striping)") 83 84 system = Param.System(Parent.any, "System we belong to") 85 86# Enum for cache clusivity, currently mostly inclusive or mostly 87# exclusive. 88class Clusivity(Enum): vals = ['mostly_incl', 'mostly_excl'] 89 90class Cache(BaseCache): 91 type = 'Cache' 92 cxx_header = 'mem/cache/cache.hh' 93 94 # Control whether this cache should be mostly inclusive or mostly 95 # exclusive with respect to upstream caches. The behaviour on a 96 # fill is determined accordingly. For a mostly inclusive cache, 97 # blocks are allocated on all fill operations. Thus, L1 caches 98 # should be set as mostly inclusive even if they have no upstream 99 # caches. In the case of a mostly exclusive cache, fills are not 100 # allocating unless they came directly from a non-caching source, 101 # e.g. a table walker. Additionally, on a hit from an upstream 102 # cache a line is dropped for a mostly exclusive cache. 103 clusivity = Param.Clusivity('mostly_incl', 104 "Clusivity with upstream cache") 105 106 # Determine if this cache sends out writebacks for clean lines, or 107 # simply clean evicts. In cases where a downstream cache is mostly 108 # exclusive with respect to this cache (acting as a victim cache), 109 # the clean writebacks are essential for performance. In general 110 # this should be set to True for anything but the last-level 111 # cache. 112 writeback_clean = Param.Bool(False, "Writeback clean lines") 113