bridge.hh revision 9786:03a075377221
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2006 The Regents of The University of Michigan 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Ali Saidi 41 * Steve Reinhardt 42 * Andreas Hansson 43 */ 44 45/** 46 * @file 47 * Declaration of a memory-mapped bus bridge that connects a master 48 * and a slave through a request and response queue. 49 */ 50 51#ifndef __MEM_BRIDGE_HH__ 52#define __MEM_BRIDGE_HH__ 53 54#include <deque> 55 56#include "base/types.hh" 57#include "mem/mem_object.hh" 58#include "params/Bridge.hh" 59 60/** 61 * A bridge is used to interface two different busses (or in general a 62 * memory-mapped master and slave), with buffering for requests and 63 * responses. The bridge has a fixed delay for packets passing through 64 * it and responds to a fixed set of address ranges. 65 * 66 * The bridge comprises a slave port and a master port, that buffer 67 * outgoing responses and requests respectively. Buffer space is 68 * reserved when a request arrives, also reserving response space 69 * before forwarding the request. If there is no space present, then 70 * the bridge will delay accepting the packet until space becomes 71 * available. 72 */ 73class Bridge : public MemObject 74{ 75 protected: 76 77 /** 78 * A bridge request state stores packets along with their sender 79 * state and original source. It has enough information to also 80 * restore the response once it comes back to the bridge. 81 */ 82 class RequestState : public Packet::SenderState 83 { 84 85 public: 86 87 const PortID origSrc; 88 89 RequestState(PortID orig_src) : origSrc(orig_src) 90 { } 91 92 }; 93 94 /** 95 * A deferred packet stores a packet along with its scheduled 96 * transmission time 97 */ 98 class DeferredPacket 99 { 100 101 public: 102 103 const Tick tick; 104 const PacketPtr pkt; 105 106 DeferredPacket(PacketPtr _pkt, Tick _tick) : tick(_tick), pkt(_pkt) 107 { } 108 }; 109 110 // Forward declaration to allow the slave port to have a pointer 111 class BridgeMasterPort; 112 113 /** 114 * The port on the side that receives requests and sends 115 * responses. The slave port has a set of address ranges that it 116 * is responsible for. The slave port also has a buffer for the 117 * responses not yet sent. 118 */ 119 class BridgeSlavePort : public SlavePort 120 { 121 122 private: 123 124 /** The bridge to which this port belongs. */ 125 Bridge& bridge; 126 127 /** 128 * Master port on the other side of the bridge (connected to 129 * the other bus). 130 */ 131 BridgeMasterPort& masterPort; 132 133 /** Minimum request delay though this bridge. */ 134 const Cycles delay; 135 136 /** Address ranges to pass through the bridge */ 137 const AddrRangeList ranges; 138 139 /** 140 * Response packet queue. Response packets are held in this 141 * queue for a specified delay to model the processing delay 142 * of the bridge. We use a deque as we need to iterate over 143 * the items for functional accesses. 144 */ 145 std::deque<DeferredPacket> transmitList; 146 147 /** Counter to track the outstanding responses. */ 148 unsigned int outstandingResponses; 149 150 /** If we should send a retry when space becomes available. */ 151 bool retryReq; 152 153 /** Max queue size for reserved responses. */ 154 unsigned int respQueueLimit; 155 156 /** 157 * Is this side blocked from accepting new response packets. 158 * 159 * @return true if the reserved space has reached the set limit 160 */ 161 bool respQueueFull() const; 162 163 /** 164 * Handle send event, scheduled when the packet at the head of 165 * the response queue is ready to transmit (for timing 166 * accesses only). 167 */ 168 void trySendTiming(); 169 170 /** Send event for the response queue. */ 171 EventWrapper<BridgeSlavePort, 172 &BridgeSlavePort::trySendTiming> sendEvent; 173 174 public: 175 176 /** 177 * Constructor for the BridgeSlavePort. 178 * 179 * @param _name the port name including the owner 180 * @param _bridge the structural owner 181 * @param _masterPort the master port on the other side of the bridge 182 * @param _delay the delay in cycles from receiving to sending 183 * @param _resp_limit the size of the response queue 184 * @param _ranges a number of address ranges to forward 185 */ 186 BridgeSlavePort(const std::string& _name, Bridge& _bridge, 187 BridgeMasterPort& _masterPort, Cycles _delay, 188 int _resp_limit, std::vector<AddrRange> _ranges); 189 190 /** 191 * Queue a response packet to be sent out later and also schedule 192 * a send if necessary. 193 * 194 * @param pkt a response to send out after a delay 195 * @param when tick when response packet should be sent 196 */ 197 void schedTimingResp(PacketPtr pkt, Tick when); 198 199 /** 200 * Retry any stalled request that we have failed to accept at 201 * an earlier point in time. This call will do nothing if no 202 * request is waiting. 203 */ 204 void retryStalledReq(); 205 206 protected: 207 208 /** When receiving a timing request from the peer port, 209 pass it to the bridge. */ 210 bool recvTimingReq(PacketPtr pkt); 211 212 /** When receiving a retry request from the peer port, 213 pass it to the bridge. */ 214 void recvRetry(); 215 216 /** When receiving a Atomic requestfrom the peer port, 217 pass it to the bridge. */ 218 Tick recvAtomic(PacketPtr pkt); 219 220 /** When receiving a Functional request from the peer port, 221 pass it to the bridge. */ 222 void recvFunctional(PacketPtr pkt); 223 224 /** When receiving a address range request the peer port, 225 pass it to the bridge. */ 226 AddrRangeList getAddrRanges() const; 227 }; 228 229 230 /** 231 * Port on the side that forwards requests and receives 232 * responses. The master port has a buffer for the requests not 233 * yet sent. 234 */ 235 class BridgeMasterPort : public MasterPort 236 { 237 238 private: 239 240 /** The bridge to which this port belongs. */ 241 Bridge& bridge; 242 243 /** 244 * The slave port on the other side of the bridge (connected 245 * to the other bus). 246 */ 247 BridgeSlavePort& slavePort; 248 249 /** Minimum delay though this bridge. */ 250 const Cycles delay; 251 252 /** 253 * Request packet queue. Request packets are held in this 254 * queue for a specified delay to model the processing delay 255 * of the bridge. We use a deque as we need to iterate over 256 * the items for functional accesses. 257 */ 258 std::deque<DeferredPacket> transmitList; 259 260 /** Max queue size for request packets */ 261 const unsigned int reqQueueLimit; 262 263 /** 264 * Handle send event, scheduled when the packet at the head of 265 * the outbound queue is ready to transmit (for timing 266 * accesses only). 267 */ 268 void trySendTiming(); 269 270 /** Send event for the request queue. */ 271 EventWrapper<BridgeMasterPort, 272 &BridgeMasterPort::trySendTiming> sendEvent; 273 274 public: 275 276 /** 277 * Constructor for the BridgeMasterPort. 278 * 279 * @param _name the port name including the owner 280 * @param _bridge the structural owner 281 * @param _slavePort the slave port on the other side of the bridge 282 * @param _delay the delay in cycles from receiving to sending 283 * @param _req_limit the size of the request queue 284 */ 285 BridgeMasterPort(const std::string& _name, Bridge& _bridge, 286 BridgeSlavePort& _slavePort, Cycles _delay, 287 int _req_limit); 288 289 /** 290 * Is this side blocked from accepting new request packets. 291 * 292 * @return true if the occupied space has reached the set limit 293 */ 294 bool reqQueueFull() const; 295 296 /** 297 * Queue a request packet to be sent out later and also schedule 298 * a send if necessary. 299 * 300 * @param pkt a request to send out after a delay 301 * @param when tick when response packet should be sent 302 */ 303 void schedTimingReq(PacketPtr pkt, Tick when); 304 305 /** 306 * Check a functional request against the packets in our 307 * request queue. 308 * 309 * @param pkt packet to check against 310 * 311 * @return true if we find a match 312 */ 313 bool checkFunctional(PacketPtr pkt); 314 315 protected: 316 317 /** When receiving a timing request from the peer port, 318 pass it to the bridge. */ 319 bool recvTimingResp(PacketPtr pkt); 320 321 /** When receiving a retry request from the peer port, 322 pass it to the bridge. */ 323 void recvRetry(); 324 }; 325 326 /** Slave port of the bridge. */ 327 BridgeSlavePort slavePort; 328 329 /** Master port of the bridge. */ 330 BridgeMasterPort masterPort; 331 332 public: 333 334 virtual BaseMasterPort& getMasterPort(const std::string& if_name, 335 PortID idx = InvalidPortID); 336 virtual BaseSlavePort& getSlavePort(const std::string& if_name, 337 PortID idx = InvalidPortID); 338 339 virtual void init(); 340 341 typedef BridgeParams Params; 342 343 Bridge(Params *p); 344}; 345 346#endif //__MEM_BUS_HH__ 347