abstract_mem.hh revision 8931 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Andreas Hansson
42 */
43
44/**
45 * @file
46 * AbstractMemory declaration
47 */
48
49#ifndef __ABSTRACT_MEMORY_HH__
50#define __ABSTRACT_MEMORY_HH__
51
52#include "mem/mem_object.hh"
53#include "params/AbstractMemory.hh"
54#include "sim/stats.hh"
55
56/**
57 * An abstract memory represents a contiguous block of physical
58 * memory, with an associated address range, and also provides basic
59 * functionality for reading and writing this memory without any
60 * timing information. It is a MemObject since any subclass must have
61 * at least one slave port.
62 */
63class AbstractMemory : public MemObject
64{
65  protected:
66
67    // Address range of this memory
68    Range<Addr> range;
69
70    // Pointer to host memory used to implement this memory
71    uint8_t* pmemAddr;
72
73    // Enable specific memories to be reported to the configuration table
74    bool confTableReported;
75
76    // Should the memory appear in the global address map
77    bool inAddrMap;
78
79    class LockedAddr {
80
81      public:
82        // on alpha, minimum LL/SC granularity is 16 bytes, so lower
83        // bits need to masked off.
84        static const Addr Addr_Mask = 0xf;
85
86        static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); }
87
88        Addr addr;      // locked address
89        int contextId;     // locking hw context
90
91        // check for matching execution context
92        bool matchesContext(Request *req)
93        {
94            return (contextId == req->contextId());
95        }
96
97        LockedAddr(Request *req) : addr(mask(req->getPaddr())),
98                                   contextId(req->contextId())
99        {
100        }
101        // constructor for unserialization use
102        LockedAddr(Addr _addr, int _cid) : addr(_addr), contextId(_cid)
103        {
104        }
105    };
106
107    std::list<LockedAddr> lockedAddrList;
108
109    // helper function for checkLockedAddrs(): we really want to
110    // inline a quick check for an empty locked addr list (hopefully
111    // the common case), and do the full list search (if necessary) in
112    // this out-of-line function
113    bool checkLockedAddrList(PacketPtr pkt);
114
115    // Record the address of a load-locked operation so that we can
116    // clear the execution context's lock flag if a matching store is
117    // performed
118    void trackLoadLocked(PacketPtr pkt);
119
120    // Compare a store address with any locked addresses so we can
121    // clear the lock flag appropriately.  Return value set to 'false'
122    // if store operation should be suppressed (because it was a
123    // conditional store and the address was no longer locked by the
124    // requesting execution context), 'true' otherwise.  Note that
125    // this method must be called on *all* stores since even
126    // non-conditional stores must clear any matching lock addresses.
127    bool writeOK(PacketPtr pkt) {
128        Request *req = pkt->req;
129        if (lockedAddrList.empty()) {
130            // no locked addrs: nothing to check, store_conditional fails
131            bool isLLSC = pkt->isLLSC();
132            if (isLLSC) {
133                req->setExtraData(0);
134            }
135            return !isLLSC; // only do write if not an sc
136        } else {
137            // iterate over list...
138            return checkLockedAddrList(pkt);
139        }
140    }
141
142    /** Number of total bytes read from this memory */
143    Stats::Scalar bytesRead;
144    /** Number of instruction bytes read from this memory */
145    Stats::Scalar bytesInstRead;
146    /** Number of bytes written to this memory */
147    Stats::Scalar bytesWritten;
148    /** Number of read requests */
149    Stats::Scalar numReads;
150    /** Number of write requests */
151    Stats::Scalar numWrites;
152    /** Number of other requests */
153    Stats::Scalar numOther;
154    /** Read bandwidth from this memory */
155    Stats::Formula bwRead;
156    /** Read bandwidth from this memory */
157    Stats::Formula bwInstRead;
158    /** Write bandwidth from this memory */
159    Stats::Formula bwWrite;
160    /** Total bandwidth from this memory */
161    Stats::Formula bwTotal;
162
163  private:
164
165    // Prevent copying
166    AbstractMemory(const AbstractMemory&);
167
168    // Prevent assignment
169    AbstractMemory& operator=(const AbstractMemory&);
170
171  public:
172
173    typedef AbstractMemoryParams Params;
174
175    AbstractMemory(const Params* p);
176    virtual ~AbstractMemory();
177
178    const Params *
179    params() const
180    {
181        return dynamic_cast<const Params *>(_params);
182    }
183
184    /**
185     * Get the address range
186     *
187     * @return a single contigous address range
188     */
189    Range<Addr> getAddrRange();
190
191    /**
192     * Get the memory size.
193     *
194     * @return the size of the memory
195     */
196    uint64_t size() { return range.size(); }
197
198    /**
199     * Get the start address.
200     *
201     * @return the start address of the memory
202     */
203    Addr start() { return range.start; }
204
205    /**
206     *  Should this memory be passed to the kernel and part of the OS
207     *  physical memory layout.
208     *
209     * @return if this memory is reported
210     */
211    bool isConfReported() const { return confTableReported; }
212
213    /**
214     * Some memories are used as shadow memories or should for other
215     * reasons not be part of the global address map.
216     *
217     * @return if this memory is part of the address map
218     */
219    bool isInAddrMap() const { return inAddrMap; }
220
221    /**
222     * Perform an untimed memory access and update all the state
223     * (e.g. locked addresses) and statistics accordingly. The packet
224     * is turned into a response if required.
225     *
226     * @param pkt Packet performing the access
227     */
228    void access(PacketPtr pkt);
229
230    /**
231     * Perform an untimed memory read or write without changing
232     * anything but the memory itself. No stats are affected by this
233     * access. In addition to normal accesses this also facilitates
234     * print requests.
235     *
236     * @param pkt Packet performing the access
237     */
238    void functionalAccess(PacketPtr pkt);
239
240    /**
241     * Register Statistics
242     */
243    virtual void regStats();
244
245    virtual void serialize(std::ostream &os);
246    virtual void unserialize(Checkpoint *cp, const std::string &section);
247
248};
249
250#endif //__ABSTRACT_MEMORY_HH__
251