abstract_mem.hh revision 8923
13985Sgblack@eecs.umich.edu/* 22632Sstever@eecs.umich.edu * Copyright (c) 2001-2005 The Regents of The University of Michigan 32632Sstever@eecs.umich.edu * All rights reserved. 42632Sstever@eecs.umich.edu * 52632Sstever@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 62632Sstever@eecs.umich.edu * modification, are permitted provided that the following conditions are 72632Sstever@eecs.umich.edu * met: redistributions of source code must retain the above copyright 82632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 92632Sstever@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 102632Sstever@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 112632Sstever@eecs.umich.edu * documentation and/or other materials provided with the distribution; 122632Sstever@eecs.umich.edu * neither the name of the copyright holders nor the names of its 132632Sstever@eecs.umich.edu * contributors may be used to endorse or promote products derived from 142632Sstever@eecs.umich.edu * this software without specific prior written permission. 152632Sstever@eecs.umich.edu * 162632Sstever@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172632Sstever@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182632Sstever@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192632Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202632Sstever@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212632Sstever@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222632Sstever@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232632Sstever@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242632Sstever@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252632Sstever@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262632Sstever@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272632Sstever@eecs.umich.edu * 282632Sstever@eecs.umich.edu * Authors: Ron Dreslinski 292632Sstever@eecs.umich.edu */ 302022SN/A 312022SN/A/* @file 322022SN/A */ 332022SN/A 342022SN/A#ifndef __PHYSICAL_MEMORY_HH__ 352022SN/A#define __PHYSICAL_MEMORY_HH__ 362022SN/A 372516SN/A#include <map> 382022SN/A#include <string> 392022SN/A 402022SN/A#include "base/range.hh" 412224SN/A#include "base/statistics.hh" 422224SN/A#include "mem/mem_object.hh" 434253Sgblack@eecs.umich.edu#include "mem/packet.hh" 442224SN/A#include "mem/tport.hh" 452224SN/A#include "params/PhysicalMemory.hh" 462224SN/A#include "sim/eventq.hh" 472022SN/A#include "sim/stats.hh" 482224SN/A 492224SN/A// 502022SN/A// Functional model for a contiguous block of physical memory. (i.e. RAM) 512516SN/A// 522516SN/Aclass PhysicalMemory : public MemObject 532516SN/A{ 542516SN/A protected: 552516SN/A 562516SN/A class MemoryPort : public SimpleTimingPort 572516SN/A { 582516SN/A PhysicalMemory *memory; 594253Sgblack@eecs.umich.edu 602516SN/A public: 612516SN/A 622516SN/A MemoryPort(const std::string &_name, PhysicalMemory *_memory); 632516SN/A 642516SN/A protected: 652516SN/A 662516SN/A virtual Tick recvAtomic(PacketPtr pkt); 672516SN/A 682516SN/A virtual void recvFunctional(PacketPtr pkt); 692516SN/A 702516SN/A virtual AddrRangeList getAddrRanges(); 712516SN/A 722944Sgblack@eecs.umich.edu virtual unsigned deviceBlockSize() const; 732516SN/A }; 742944Sgblack@eecs.umich.edu 752944Sgblack@eecs.umich.edu int numPorts; 762516SN/A 772516SN/A 782516SN/A private: 794253Sgblack@eecs.umich.edu // prevent copying of a MainMemory object 802516SN/A PhysicalMemory(const PhysicalMemory &specmem); 812516SN/A const PhysicalMemory &operator=(const PhysicalMemory &specmem); 822516SN/A 833273Sgblack@eecs.umich.edu protected: 842516SN/A 852516SN/A class LockedAddr { 862516SN/A public: 872516SN/A // on alpha, minimum LL/SC granularity is 16 bytes, so lower 882516SN/A // bits need to masked off. 892516SN/A static const Addr Addr_Mask = 0xf; 902516SN/A 912516SN/A static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } 922516SN/A 932516SN/A Addr addr; // locked address 944253Sgblack@eecs.umich.edu int contextId; // locking hw context 952516SN/A 962516SN/A // check for matching execution context 972516SN/A bool matchesContext(Request *req) 983273Sgblack@eecs.umich.edu { 992516SN/A return (contextId == req->contextId()); 1002516SN/A } 1012516SN/A 1022516SN/A LockedAddr(Request *req) 1032516SN/A : addr(mask(req->getPaddr())), 1042516SN/A contextId(req->contextId()) 1052516SN/A { 1062516SN/A } 1072516SN/A // constructor for unserialization use 1082516SN/A LockedAddr(Addr _addr, int _cid) 1092516SN/A : addr(_addr), contextId(_cid) 1104253Sgblack@eecs.umich.edu { 1113273Sgblack@eecs.umich.edu } 1122516SN/A }; 1132516SN/A 1142516SN/A std::list<LockedAddr> lockedAddrList; 1152516SN/A 1162516SN/A // helper function for checkLockedAddrs(): we really want to 1172516SN/A // inline a quick check for an empty locked addr list (hopefully 1182516SN/A // the common case), and do the full list search (if necessary) in 1192516SN/A // this out-of-line function 1202022SN/A bool checkLockedAddrList(PacketPtr pkt); 1212022SN/A 1222022SN/A // Record the address of a load-locked operation so that we can 1232944Sgblack@eecs.umich.edu // clear the execution context's lock flag if a matching store is 1242944Sgblack@eecs.umich.edu // performed 1252944Sgblack@eecs.umich.edu void trackLoadLocked(PacketPtr pkt); 1262944Sgblack@eecs.umich.edu 1272944Sgblack@eecs.umich.edu // Compare a store address with any locked addresses so we can 1282944Sgblack@eecs.umich.edu // clear the lock flag appropriately. Return value set to 'false' 1292944Sgblack@eecs.umich.edu // if store operation should be suppressed (because it was a 1307741Sgblack@eecs.umich.edu // conditional store and the address was no longer locked by the 1317741Sgblack@eecs.umich.edu // requesting execution context), 'true' otherwise. Note that 1327741Sgblack@eecs.umich.edu // this method must be called on *all* stores since even 1337741Sgblack@eecs.umich.edu // non-conditional stores must clear any matching lock addresses. 1347741Sgblack@eecs.umich.edu bool writeOK(PacketPtr pkt) { 1357741Sgblack@eecs.umich.edu Request *req = pkt->req; 1367741Sgblack@eecs.umich.edu if (lockedAddrList.empty()) { 1377741Sgblack@eecs.umich.edu // no locked addrs: nothing to check, store_conditional fails 1387741Sgblack@eecs.umich.edu bool isLLSC = pkt->isLLSC(); 1397741Sgblack@eecs.umich.edu if (isLLSC) { 1407741Sgblack@eecs.umich.edu req->setExtraData(0); 1417741Sgblack@eecs.umich.edu } 1427741Sgblack@eecs.umich.edu return !isLLSC; // only do write if not an sc 1437741Sgblack@eecs.umich.edu } else { 1447741Sgblack@eecs.umich.edu // iterate over list... 1457741Sgblack@eecs.umich.edu return checkLockedAddrList(pkt); 1462516SN/A } 1472022SN/A } 1482516SN/A 1492516SN/A uint8_t *pmemAddr; 1502516SN/A Tick lat; 1512944Sgblack@eecs.umich.edu Tick lat_var; 1527741Sgblack@eecs.umich.edu std::vector<MemoryPort*> ports; 1532516SN/A typedef std::vector<MemoryPort*>::iterator PortIterator; 1542516SN/A 1552516SN/A uint64_t _size; 1562516SN/A uint64_t _start; 1572944Sgblack@eecs.umich.edu 1582516SN/A /** Number of total bytes read from this memory */ 1592516SN/A Stats::Scalar bytesRead; 1602516SN/A /** Number of instruction bytes read from this memory */ 1612516SN/A Stats::Scalar bytesInstRead; 1627741Sgblack@eecs.umich.edu /** Number of bytes written to this memory */ 1637741Sgblack@eecs.umich.edu Stats::Scalar bytesWritten; 1642516SN/A /** Number of read requests */ 1652516SN/A Stats::Scalar numReads; 1662516SN/A /** Number of write requests */ 1672516SN/A Stats::Scalar numWrites; 1682516SN/A /** Number of other requests */ 1692516SN/A Stats::Scalar numOther; 1702516SN/A /** Read bandwidth from this memory */ 1712516SN/A Stats::Formula bwRead; 1722516SN/A /** Read bandwidth from this memory */ 1732516SN/A Stats::Formula bwInstRead; 1742516SN/A /** Write bandwidth from this memory */ 1757741Sgblack@eecs.umich.edu Stats::Formula bwWrite; 1767741Sgblack@eecs.umich.edu /** Total bandwidth from this memory */ 1772516SN/A Stats::Formula bwTotal; 1787741Sgblack@eecs.umich.edu 1792580SN/A public: 1802516SN/A uint64_t size() { return _size; } 1812516SN/A uint64_t start() { return _start; } 1822516SN/A 1832516SN/A public: 1842516SN/A typedef PhysicalMemoryParams Params; 1852022SN/A PhysicalMemory(const Params *p); 1862022SN/A virtual ~PhysicalMemory(); 1872022SN/A 1885091Sgblack@eecs.umich.edu const Params * 1892224SN/A params() const 1902224SN/A { 1912022SN/A return dynamic_cast<const Params *>(_params); 1927741Sgblack@eecs.umich.edu } 1932224SN/A 1942022SN/A public: 1952224SN/A unsigned deviceBlockSize() const; 1962224SN/A AddrRangeList getAddrRanges(); 1972516SN/A virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1); 1982224SN/A void virtual init(); 1992022SN/A unsigned int drain(Event *de); 2007741Sgblack@eecs.umich.edu 2017741Sgblack@eecs.umich.edu Tick doAtomicAccess(PacketPtr pkt); 2022022SN/A void doFunctionalAccess(PacketPtr pkt); 2032224SN/A 2042022SN/A 2052224SN/A protected: 2062022SN/A virtual Tick calculateLatency(PacketPtr pkt); 2072022SN/A 2082022SN/A public: 2095091Sgblack@eecs.umich.edu /** 2107741Sgblack@eecs.umich.edu * Register Statistics 2117741Sgblack@eecs.umich.edu */ 2125091Sgblack@eecs.umich.edu void regStats(); 2132580SN/A 2147741Sgblack@eecs.umich.edu virtual void serialize(std::ostream &os); 2155091Sgblack@eecs.umich.edu virtual void unserialize(Checkpoint *cp, const std::string §ion); 2165091Sgblack@eecs.umich.edu 2175091Sgblack@eecs.umich.edu}; 2185091Sgblack@eecs.umich.edu 2195091Sgblack@eecs.umich.edu#endif //__PHYSICAL_MEMORY_HH__ 2205091Sgblack@eecs.umich.edu