abstract_mem.hh revision 2413
17405SAli.Saidi@ARM.com/* 211573SDylan.Johnson@ARM.com * Copyright (c) 2001-2005 The Regents of The University of Michigan 37405SAli.Saidi@ARM.com * All rights reserved. 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 67405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 77405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 87405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 97405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 107405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 117405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 127405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 137405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 147405SAli.Saidi@ARM.com * this software without specific prior written permission. 157405SAli.Saidi@ARM.com * 167405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 177405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 187405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 197405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 207405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 217405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 227405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 237405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 247405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 257405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 267405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 277405SAli.Saidi@ARM.com */ 287405SAli.Saidi@ARM.com 297405SAli.Saidi@ARM.com/* @file 307405SAli.Saidi@ARM.com */ 317405SAli.Saidi@ARM.com 327405SAli.Saidi@ARM.com#ifndef __PHYSICAL_MEMORY_HH__ 337405SAli.Saidi@ARM.com#define __PHYSICAL_MEMORY_HH__ 347405SAli.Saidi@ARM.com 357405SAli.Saidi@ARM.com#include "base/range.hh" 367405SAli.Saidi@ARM.com#include "mem/memory.hh" 377405SAli.Saidi@ARM.com 387405SAli.Saidi@ARM.com// 397405SAli.Saidi@ARM.com// Functional model for a contiguous block of physical memory. (i.e. RAM) 407405SAli.Saidi@ARM.com// 417405SAli.Saidi@ARM.comclass PhysicalMemory : public Memory 4211793Sbrandon.potter@amd.com{ 4310461SAndreas.Sandberg@ARM.com class MemoryPort : public Port 449050Schander.sudanthi@arm.com { 4511793Sbrandon.potter@amd.com PhysicalMemory *memory; 468887Sgeoffrey.blake@arm.com 478232Snate@binkert.org public: 488232Snate@binkert.org 4910844Sandreas.sandberg@arm.com MemoryPort(PhysicalMemory *_memory); 509384SAndreas.Sandberg@arm.com 517678Sgblack@eecs.umich.edu protected: 528059SAli.Saidi@ARM.com 538284SAli.Saidi@ARM.com virtual bool recvTiming(Packet &pkt); 547405SAli.Saidi@ARM.com 557405SAli.Saidi@ARM.com virtual Tick recvAtomic(Packet &pkt); 567405SAli.Saidi@ARM.com 577405SAli.Saidi@ARM.com virtual void recvFunctional(Packet &pkt); 5810037SARM gem5 Developers 5910037SARM gem5 Developers virtual void recvStatusChange(Status status); 6011768SCurtis.Dunham@arm.com 6110037SARM gem5 Developers virtual void getDeviceAddressRanges(AddrRangeList &range_list, 6210037SARM gem5 Developers bool &owner); 6310037SARM gem5 Developers 6410037SARM gem5 Developers virtual int deviceBlockSize(); 6511768SCurtis.Dunham@arm.com 6610037SARM gem5 Developers }; 6710037SARM gem5 Developers 6811768SCurtis.Dunham@arm.com MemoryPort memoryPort; 6911768SCurtis.Dunham@arm.com 7011768SCurtis.Dunham@arm.com Port * PhysicalMemory::getPort(const char *if_name); 7111768SCurtis.Dunham@arm.com 7211768SCurtis.Dunham@arm.com int lat; 7311768SCurtis.Dunham@arm.com 7411768SCurtis.Dunham@arm.com //event to send response needs to be here 7511768SCurtis.Dunham@arm.com 7611768SCurtis.Dunham@arm.com private: 7711768SCurtis.Dunham@arm.com // prevent copying of a MainMemory object 7811768SCurtis.Dunham@arm.com PhysicalMemory(const PhysicalMemory &specmem); 7911768SCurtis.Dunham@arm.com const PhysicalMemory &operator=(const PhysicalMemory &specmem); 8010037SARM gem5 Developers 8110037SARM gem5 Developers protected: 8210037SARM gem5 Developers Addr base_addr; 8311768SCurtis.Dunham@arm.com Addr pmem_size; 8411768SCurtis.Dunham@arm.com uint8_t *pmem_addr; 8511768SCurtis.Dunham@arm.com int page_ptr; 8611768SCurtis.Dunham@arm.com 8711768SCurtis.Dunham@arm.com public: 8811768SCurtis.Dunham@arm.com Addr new_page(); 8911768SCurtis.Dunham@arm.com uint64_t size() { return pmem_size; } 9011768SCurtis.Dunham@arm.com 9110037SARM gem5 Developers public: 9211768SCurtis.Dunham@arm.com PhysicalMemory(const std::string &n); 9311768SCurtis.Dunham@arm.com virtual ~PhysicalMemory(); 9411768SCurtis.Dunham@arm.com 9511768SCurtis.Dunham@arm.com protected: 9610037SARM gem5 Developers // error handling for prot_* functions 9711768SCurtis.Dunham@arm.com void prot_access_error(Addr addr, int size, const std::string &func); 9811768SCurtis.Dunham@arm.com 9911768SCurtis.Dunham@arm.com public: 10011768SCurtis.Dunham@arm.com virtual int deviceBlockSize(); 10111768SCurtis.Dunham@arm.com 10211768SCurtis.Dunham@arm.com // Read/Write arbitrary amounts of data to simulated memory space 10311768SCurtis.Dunham@arm.com void prot_read(Addr addr, uint8_t *p, int size); 10411768SCurtis.Dunham@arm.com void prot_write(Addr addr, const uint8_t *p, int size); 10511768SCurtis.Dunham@arm.com void prot_memset(Addr addr, uint8_t val, int size); 10611768SCurtis.Dunham@arm.com 10711768SCurtis.Dunham@arm.com // fast back-door memory access for vtophys(), remote gdb, etc. 10811768SCurtis.Dunham@arm.com uint64_t phys_read_qword(Addr addr) const; 10911768SCurtis.Dunham@arm.com private: 11011768SCurtis.Dunham@arm.com bool doTimingAccess(Packet &pkt); 11111768SCurtis.Dunham@arm.com Tick doAtomicAccess(Packet &pkt); 11211768SCurtis.Dunham@arm.com void doFunctionalAccess(Packet &pkt); 11311768SCurtis.Dunham@arm.com 11411768SCurtis.Dunham@arm.com void recvStatusChange(Port::Status status); 11510037SARM gem5 Developers 11611768SCurtis.Dunham@arm.com public: 11711768SCurtis.Dunham@arm.com virtual void serialize(std::ostream &os); 11811768SCurtis.Dunham@arm.com virtual void unserialize(Checkpoint *cp, const std::string §ion); 11911768SCurtis.Dunham@arm.com}; 12010037SARM gem5 Developers 12111768SCurtis.Dunham@arm.com/*uint64_t 12211768SCurtis.Dunham@arm.comPhysicalMemory::phys_read_qword(Addr addr) const 12311768SCurtis.Dunham@arm.com{ 12411768SCurtis.Dunham@arm.com if (addr + sizeof(uint64_t) > pmem_size) 12511768SCurtis.Dunham@arm.com return 0; 12611768SCurtis.Dunham@arm.com 12710037SARM gem5 Developers return *(uint64_t *)(pmem_addr + addr); 12811768SCurtis.Dunham@arm.com}*/ 12911768SCurtis.Dunham@arm.com 13011768SCurtis.Dunham@arm.com 13111768SCurtis.Dunham@arm.com#endif //__PHYSICAL_MEMORY_HH__ 13211768SCurtis.Dunham@arm.com