abstract_mem.cc revision 9293
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2001-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ron Dreslinski
41 *          Ali Saidi
42 *          Andreas Hansson
43 */
44
45#include "arch/registers.hh"
46#include "config/the_isa.hh"
47#include "debug/LLSC.hh"
48#include "debug/MemoryAccess.hh"
49#include "mem/abstract_mem.hh"
50#include "mem/packet_access.hh"
51#include "sim/system.hh"
52
53using namespace std;
54
55AbstractMemory::AbstractMemory(const Params *p) :
56    MemObject(p), range(params()->range), pmemAddr(NULL),
57    confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map),
58    _system(NULL)
59{
60    if (size() % TheISA::PageBytes != 0)
61        panic("Memory Size not divisible by page size\n");
62}
63
64void
65AbstractMemory::setBackingStore(uint8_t* pmem_addr)
66{
67    pmemAddr = pmem_addr;
68}
69
70void
71AbstractMemory::regStats()
72{
73    using namespace Stats;
74
75    assert(system());
76
77    bytesRead
78        .init(system()->maxMasters())
79        .name(name() + ".bytes_read")
80        .desc("Number of bytes read from this memory")
81        .flags(total | nozero | nonan)
82        ;
83    for (int i = 0; i < system()->maxMasters(); i++) {
84        bytesRead.subname(i, system()->getMasterName(i));
85    }
86    bytesInstRead
87        .init(system()->maxMasters())
88        .name(name() + ".bytes_inst_read")
89        .desc("Number of instructions bytes read from this memory")
90        .flags(total | nozero | nonan)
91        ;
92    for (int i = 0; i < system()->maxMasters(); i++) {
93        bytesInstRead.subname(i, system()->getMasterName(i));
94    }
95    bytesWritten
96        .init(system()->maxMasters())
97        .name(name() + ".bytes_written")
98        .desc("Number of bytes written to this memory")
99        .flags(total | nozero | nonan)
100        ;
101    for (int i = 0; i < system()->maxMasters(); i++) {
102        bytesWritten.subname(i, system()->getMasterName(i));
103    }
104    numReads
105        .init(system()->maxMasters())
106        .name(name() + ".num_reads")
107        .desc("Number of read requests responded to by this memory")
108        .flags(total | nozero | nonan)
109        ;
110    for (int i = 0; i < system()->maxMasters(); i++) {
111        numReads.subname(i, system()->getMasterName(i));
112    }
113    numWrites
114        .init(system()->maxMasters())
115        .name(name() + ".num_writes")
116        .desc("Number of write requests responded to by this memory")
117        .flags(total | nozero | nonan)
118        ;
119    for (int i = 0; i < system()->maxMasters(); i++) {
120        numWrites.subname(i, system()->getMasterName(i));
121    }
122    numOther
123        .init(system()->maxMasters())
124        .name(name() + ".num_other")
125        .desc("Number of other requests responded to by this memory")
126        .flags(total | nozero | nonan)
127        ;
128    for (int i = 0; i < system()->maxMasters(); i++) {
129        numOther.subname(i, system()->getMasterName(i));
130    }
131    bwRead
132        .name(name() + ".bw_read")
133        .desc("Total read bandwidth from this memory (bytes/s)")
134        .precision(0)
135        .prereq(bytesRead)
136        .flags(total | nozero | nonan)
137        ;
138    for (int i = 0; i < system()->maxMasters(); i++) {
139        bwRead.subname(i, system()->getMasterName(i));
140    }
141
142    bwInstRead
143        .name(name() + ".bw_inst_read")
144        .desc("Instruction read bandwidth from this memory (bytes/s)")
145        .precision(0)
146        .prereq(bytesInstRead)
147        .flags(total | nozero | nonan)
148        ;
149    for (int i = 0; i < system()->maxMasters(); i++) {
150        bwInstRead.subname(i, system()->getMasterName(i));
151    }
152    bwWrite
153        .name(name() + ".bw_write")
154        .desc("Write bandwidth from this memory (bytes/s)")
155        .precision(0)
156        .prereq(bytesWritten)
157        .flags(total | nozero | nonan)
158        ;
159    for (int i = 0; i < system()->maxMasters(); i++) {
160        bwWrite.subname(i, system()->getMasterName(i));
161    }
162    bwTotal
163        .name(name() + ".bw_total")
164        .desc("Total bandwidth to/from this memory (bytes/s)")
165        .precision(0)
166        .prereq(bwTotal)
167        .flags(total | nozero | nonan)
168        ;
169    for (int i = 0; i < system()->maxMasters(); i++) {
170        bwTotal.subname(i, system()->getMasterName(i));
171    }
172    bwRead = bytesRead / simSeconds;
173    bwInstRead = bytesInstRead / simSeconds;
174    bwWrite = bytesWritten / simSeconds;
175    bwTotal = (bytesRead + bytesWritten) / simSeconds;
176}
177
178AddrRange
179AbstractMemory::getAddrRange() const
180{
181    return range;
182}
183
184// Add load-locked to tracking list.  Should only be called if the
185// operation is a load and the LLSC flag is set.
186void
187AbstractMemory::trackLoadLocked(PacketPtr pkt)
188{
189    Request *req = pkt->req;
190    Addr paddr = LockedAddr::mask(req->getPaddr());
191
192    // first we check if we already have a locked addr for this
193    // xc.  Since each xc only gets one, we just update the
194    // existing record with the new address.
195    list<LockedAddr>::iterator i;
196
197    for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) {
198        if (i->matchesContext(req)) {
199            DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n",
200                    req->contextId(), paddr);
201            i->addr = paddr;
202            return;
203        }
204    }
205
206    // no record for this xc: need to allocate a new one
207    DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n",
208            req->contextId(), paddr);
209    lockedAddrList.push_front(LockedAddr(req));
210}
211
212
213// Called on *writes* only... both regular stores and
214// store-conditional operations.  Check for conventional stores which
215// conflict with locked addresses, and for success/failure of store
216// conditionals.
217bool
218AbstractMemory::checkLockedAddrList(PacketPtr pkt)
219{
220    Request *req = pkt->req;
221    Addr paddr = LockedAddr::mask(req->getPaddr());
222    bool isLLSC = pkt->isLLSC();
223
224    // Initialize return value.  Non-conditional stores always
225    // succeed.  Assume conditional stores will fail until proven
226    // otherwise.
227    bool allowStore = !isLLSC;
228
229    // Iterate over list.  Note that there could be multiple matching records,
230    // as more than one context could have done a load locked to this location.
231    // Only remove records when we succeed in finding a record for (xc, addr);
232    // then, remove all records with this address.  Failed store-conditionals do
233    // not blow unrelated reservations.
234    list<LockedAddr>::iterator i = lockedAddrList.begin();
235
236    if (isLLSC) {
237        while (i != lockedAddrList.end()) {
238            if (i->addr == paddr && i->matchesContext(req)) {
239                // it's a store conditional, and as far as the memory system can
240                // tell, the requesting context's lock is still valid.
241                DPRINTF(LLSC, "StCond success: context %d addr %#x\n",
242                        req->contextId(), paddr);
243                allowStore = true;
244                break;
245            }
246            // If we didn't find a match, keep searching!  Someone else may well
247            // have a reservation on this line here but we may find ours in just
248            // a little while.
249            i++;
250        }
251        req->setExtraData(allowStore ? 1 : 0);
252    }
253    // LLSCs that succeeded AND non-LLSC stores both fall into here:
254    if (allowStore) {
255        // We write address paddr.  However, there may be several entries with a
256        // reservation on this address (for other contextIds) and they must all
257        // be removed.
258        i = lockedAddrList.begin();
259        while (i != lockedAddrList.end()) {
260            if (i->addr == paddr) {
261                DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n",
262                        i->contextId, paddr);
263                i = lockedAddrList.erase(i);
264            } else {
265                i++;
266            }
267        }
268    }
269
270    return allowStore;
271}
272
273
274#if TRACING_ON
275
276#define CASE(A, T)                                                      \
277  case sizeof(T):                                                       \
278    DPRINTF(MemoryAccess,"%s of size %i on address 0x%x data 0x%x\n",   \
279            A, pkt->getSize(), pkt->getAddr(), pkt->get<T>());          \
280  break
281
282
283#define TRACE_PACKET(A)                                                 \
284    do {                                                                \
285        switch (pkt->getSize()) {                                       \
286          CASE(A, uint64_t);                                            \
287          CASE(A, uint32_t);                                            \
288          CASE(A, uint16_t);                                            \
289          CASE(A, uint8_t);                                             \
290          default:                                                      \
291            DPRINTF(MemoryAccess, "%s of size %i on address 0x%x\n",    \
292                    A, pkt->getSize(), pkt->getAddr());                 \
293            DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize());\
294        }                                                               \
295    } while (0)
296
297#else
298
299#define TRACE_PACKET(A)
300
301#endif
302
303void
304AbstractMemory::access(PacketPtr pkt)
305{
306    assert(pkt->getAddr() >= range.start &&
307           (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
308
309    if (pkt->memInhibitAsserted()) {
310        DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n",
311                pkt->getAddr());
312        return;
313    }
314
315    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
316
317    if (pkt->cmd == MemCmd::SwapReq) {
318        TheISA::IntReg overwrite_val;
319        bool overwrite_mem;
320        uint64_t condition_val64;
321        uint32_t condition_val32;
322
323        if (!pmemAddr)
324            panic("Swap only works if there is real memory (i.e. null=False)");
325        assert(sizeof(TheISA::IntReg) >= pkt->getSize());
326
327        overwrite_mem = true;
328        // keep a copy of our possible write value, and copy what is at the
329        // memory address into the packet
330        std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize());
331        std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
332
333        if (pkt->req->isCondSwap()) {
334            if (pkt->getSize() == sizeof(uint64_t)) {
335                condition_val64 = pkt->req->getExtraData();
336                overwrite_mem = !std::memcmp(&condition_val64, hostAddr,
337                                             sizeof(uint64_t));
338            } else if (pkt->getSize() == sizeof(uint32_t)) {
339                condition_val32 = (uint32_t)pkt->req->getExtraData();
340                overwrite_mem = !std::memcmp(&condition_val32, hostAddr,
341                                             sizeof(uint32_t));
342            } else
343                panic("Invalid size for conditional read/write\n");
344        }
345
346        if (overwrite_mem)
347            std::memcpy(hostAddr, &overwrite_val, pkt->getSize());
348
349        assert(!pkt->req->isInstFetch());
350        TRACE_PACKET("Read/Write");
351        numOther[pkt->req->masterId()]++;
352    } else if (pkt->isRead()) {
353        assert(!pkt->isWrite());
354        if (pkt->isLLSC()) {
355            trackLoadLocked(pkt);
356        }
357        if (pmemAddr)
358            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
359        TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read");
360        numReads[pkt->req->masterId()]++;
361        bytesRead[pkt->req->masterId()] += pkt->getSize();
362        if (pkt->req->isInstFetch())
363            bytesInstRead[pkt->req->masterId()] += pkt->getSize();
364    } else if (pkt->isWrite()) {
365        if (writeOK(pkt)) {
366            if (pmemAddr)
367                memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
368            assert(!pkt->req->isInstFetch());
369            TRACE_PACKET("Write");
370            numWrites[pkt->req->masterId()]++;
371            bytesWritten[pkt->req->masterId()] += pkt->getSize();
372        }
373    } else if (pkt->isInvalidate()) {
374        // no need to do anything
375    } else {
376        panic("unimplemented");
377    }
378
379    if (pkt->needsResponse()) {
380        pkt->makeResponse();
381    }
382}
383
384void
385AbstractMemory::functionalAccess(PacketPtr pkt)
386{
387    assert(pkt->getAddr() >= range.start &&
388           (pkt->getAddr() + pkt->getSize() - 1) <= range.end);
389
390    uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start;
391
392    if (pkt->isRead()) {
393        if (pmemAddr)
394            memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize());
395        TRACE_PACKET("Read");
396        pkt->makeResponse();
397    } else if (pkt->isWrite()) {
398        if (pmemAddr)
399            memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize());
400        TRACE_PACKET("Write");
401        pkt->makeResponse();
402    } else if (pkt->isPrint()) {
403        Packet::PrintReqState *prs =
404            dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
405        assert(prs);
406        // Need to call printLabels() explicitly since we're not going
407        // through printObj().
408        prs->printLabels();
409        // Right now we just print the single byte at the specified address.
410        ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr);
411    } else {
412        panic("AbstractMemory: unimplemented functional command %s",
413              pkt->cmdString());
414    }
415}
416