abstract_mem.cc revision 10102
12391SN/A/* 28931Sandreas.hansson@arm.com * Copyright (c) 2010-2012 ARM Limited 37733SN/A * All rights reserved 47733SN/A * 57733SN/A * The license below extends only to copyright in the software and shall 67733SN/A * not be construed as granting a license to any other intellectual 77733SN/A * property including but not limited to intellectual property relating 87733SN/A * to a hardware implementation of the functionality of the software 97733SN/A * licensed hereunder. You may use the software subject to the license 107733SN/A * terms below provided that you ensure that this notice is replicated 117733SN/A * unmodified and in its entirety in all distributions of the software, 127733SN/A * modified or unmodified, in source code or in binary form. 137733SN/A * 142391SN/A * Copyright (c) 2001-2005 The Regents of The University of Michigan 152391SN/A * All rights reserved. 162391SN/A * 172391SN/A * Redistribution and use in source and binary forms, with or without 182391SN/A * modification, are permitted provided that the following conditions are 192391SN/A * met: redistributions of source code must retain the above copyright 202391SN/A * notice, this list of conditions and the following disclaimer; 212391SN/A * redistributions in binary form must reproduce the above copyright 222391SN/A * notice, this list of conditions and the following disclaimer in the 232391SN/A * documentation and/or other materials provided with the distribution; 242391SN/A * neither the name of the copyright holders nor the names of its 252391SN/A * contributors may be used to endorse or promote products derived from 262391SN/A * this software without specific prior written permission. 272391SN/A * 282391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302391SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312391SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322391SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392665SN/A * 402665SN/A * Authors: Ron Dreslinski 412914SN/A * Ali Saidi 428931Sandreas.hansson@arm.com * Andreas Hansson 432391SN/A */ 442391SN/A 456329SN/A#include "arch/registers.hh" 466658SN/A#include "config/the_isa.hh" 4710102Sali.saidi@arm.com#include "cpu/base.hh" 4810102Sali.saidi@arm.com#include "cpu/thread_context.hh" 498232SN/A#include "debug/LLSC.hh" 508232SN/A#include "debug/MemoryAccess.hh" 518931Sandreas.hansson@arm.com#include "mem/abstract_mem.hh" 523879SN/A#include "mem/packet_access.hh" 539053Sdam.sunwoo@arm.com#include "sim/system.hh" 542394SN/A 552391SN/Ausing namespace std; 562391SN/A 578931Sandreas.hansson@arm.comAbstractMemory::AbstractMemory(const Params *p) : 588931Sandreas.hansson@arm.com MemObject(p), range(params()->range), pmemAddr(NULL), 599053Sdam.sunwoo@arm.com confTableReported(p->conf_table_reported), inAddrMap(p->in_addr_map), 609053Sdam.sunwoo@arm.com _system(NULL) 612391SN/A{ 627730SN/A if (size() % TheISA::PageBytes != 0) 632391SN/A panic("Memory Size not divisible by page size\n"); 642391SN/A} 652391SN/A 669293Sandreas.hansson@arm.comvoid 679293Sandreas.hansson@arm.comAbstractMemory::setBackingStore(uint8_t* pmem_addr) 682391SN/A{ 699293Sandreas.hansson@arm.com pmemAddr = pmem_addr; 702391SN/A} 712391SN/A 728719SN/Avoid 738931Sandreas.hansson@arm.comAbstractMemory::regStats() 748719SN/A{ 758719SN/A using namespace Stats; 768719SN/A 779053Sdam.sunwoo@arm.com assert(system()); 789053Sdam.sunwoo@arm.com 798719SN/A bytesRead 809053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 818719SN/A .name(name() + ".bytes_read") 828719SN/A .desc("Number of bytes read from this memory") 839053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 848719SN/A ; 859053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 869053Sdam.sunwoo@arm.com bytesRead.subname(i, system()->getMasterName(i)); 879053Sdam.sunwoo@arm.com } 888719SN/A bytesInstRead 899053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 908719SN/A .name(name() + ".bytes_inst_read") 918719SN/A .desc("Number of instructions bytes read from this memory") 929053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 938719SN/A ; 949053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 959053Sdam.sunwoo@arm.com bytesInstRead.subname(i, system()->getMasterName(i)); 969053Sdam.sunwoo@arm.com } 978719SN/A bytesWritten 989053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 998719SN/A .name(name() + ".bytes_written") 1008719SN/A .desc("Number of bytes written to this memory") 1019053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1028719SN/A ; 1039053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1049053Sdam.sunwoo@arm.com bytesWritten.subname(i, system()->getMasterName(i)); 1059053Sdam.sunwoo@arm.com } 1068719SN/A numReads 1079053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1088719SN/A .name(name() + ".num_reads") 1098719SN/A .desc("Number of read requests responded to by this memory") 1109053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1118719SN/A ; 1129053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1139053Sdam.sunwoo@arm.com numReads.subname(i, system()->getMasterName(i)); 1149053Sdam.sunwoo@arm.com } 1158719SN/A numWrites 1169053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1178719SN/A .name(name() + ".num_writes") 1188719SN/A .desc("Number of write requests responded to by this memory") 1199053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1208719SN/A ; 1219053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1229053Sdam.sunwoo@arm.com numWrites.subname(i, system()->getMasterName(i)); 1239053Sdam.sunwoo@arm.com } 1248719SN/A numOther 1259053Sdam.sunwoo@arm.com .init(system()->maxMasters()) 1268719SN/A .name(name() + ".num_other") 1278719SN/A .desc("Number of other requests responded to by this memory") 1289053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1298719SN/A ; 1309053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1319053Sdam.sunwoo@arm.com numOther.subname(i, system()->getMasterName(i)); 1329053Sdam.sunwoo@arm.com } 1338719SN/A bwRead 1348719SN/A .name(name() + ".bw_read") 1358719SN/A .desc("Total read bandwidth from this memory (bytes/s)") 1368719SN/A .precision(0) 1378719SN/A .prereq(bytesRead) 1389053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1398719SN/A ; 1409053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1419053Sdam.sunwoo@arm.com bwRead.subname(i, system()->getMasterName(i)); 1429053Sdam.sunwoo@arm.com } 1439053Sdam.sunwoo@arm.com 1448719SN/A bwInstRead 1458719SN/A .name(name() + ".bw_inst_read") 1468719SN/A .desc("Instruction read bandwidth from this memory (bytes/s)") 1478719SN/A .precision(0) 1488719SN/A .prereq(bytesInstRead) 1499053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1508719SN/A ; 1519053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1529053Sdam.sunwoo@arm.com bwInstRead.subname(i, system()->getMasterName(i)); 1539053Sdam.sunwoo@arm.com } 1548719SN/A bwWrite 1558719SN/A .name(name() + ".bw_write") 1568719SN/A .desc("Write bandwidth from this memory (bytes/s)") 1578719SN/A .precision(0) 1588719SN/A .prereq(bytesWritten) 1599053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1608719SN/A ; 1619053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1629053Sdam.sunwoo@arm.com bwWrite.subname(i, system()->getMasterName(i)); 1639053Sdam.sunwoo@arm.com } 1648719SN/A bwTotal 1658719SN/A .name(name() + ".bw_total") 1668719SN/A .desc("Total bandwidth to/from this memory (bytes/s)") 1678719SN/A .precision(0) 1688719SN/A .prereq(bwTotal) 1699053Sdam.sunwoo@arm.com .flags(total | nozero | nonan) 1708719SN/A ; 1719053Sdam.sunwoo@arm.com for (int i = 0; i < system()->maxMasters(); i++) { 1729053Sdam.sunwoo@arm.com bwTotal.subname(i, system()->getMasterName(i)); 1739053Sdam.sunwoo@arm.com } 1748719SN/A bwRead = bytesRead / simSeconds; 1758719SN/A bwInstRead = bytesInstRead / simSeconds; 1768719SN/A bwWrite = bytesWritten / simSeconds; 1778719SN/A bwTotal = (bytesRead + bytesWritten) / simSeconds; 1788719SN/A} 1798719SN/A 1809235Sandreas.hansson@arm.comAddrRange 1819098Sandreas.hansson@arm.comAbstractMemory::getAddrRange() const 1822408SN/A{ 1838931Sandreas.hansson@arm.com return range; 1842408SN/A} 1852408SN/A 1863170SN/A// Add load-locked to tracking list. Should only be called if the 1876076SN/A// operation is a load and the LLSC flag is set. 1883170SN/Avoid 1898931Sandreas.hansson@arm.comAbstractMemory::trackLoadLocked(PacketPtr pkt) 1903170SN/A{ 1914626SN/A Request *req = pkt->req; 1923170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 1933170SN/A 1943170SN/A // first we check if we already have a locked addr for this 1953170SN/A // xc. Since each xc only gets one, we just update the 1963170SN/A // existing record with the new address. 1973170SN/A list<LockedAddr>::iterator i; 1983170SN/A 1993170SN/A for (i = lockedAddrList.begin(); i != lockedAddrList.end(); ++i) { 2003170SN/A if (i->matchesContext(req)) { 2015714SN/A DPRINTF(LLSC, "Modifying lock record: context %d addr %#x\n", 2025714SN/A req->contextId(), paddr); 2033170SN/A i->addr = paddr; 2043170SN/A return; 2053170SN/A } 2063170SN/A } 2073170SN/A 2083170SN/A // no record for this xc: need to allocate a new one 2095714SN/A DPRINTF(LLSC, "Adding lock record: context %d addr %#x\n", 2105714SN/A req->contextId(), paddr); 2113170SN/A lockedAddrList.push_front(LockedAddr(req)); 2123170SN/A} 2133170SN/A 2143170SN/A 2153170SN/A// Called on *writes* only... both regular stores and 2163170SN/A// store-conditional operations. Check for conventional stores which 2173170SN/A// conflict with locked addresses, and for success/failure of store 2183170SN/A// conditionals. 2193170SN/Abool 2208931Sandreas.hansson@arm.comAbstractMemory::checkLockedAddrList(PacketPtr pkt) 2213170SN/A{ 2224626SN/A Request *req = pkt->req; 2233170SN/A Addr paddr = LockedAddr::mask(req->getPaddr()); 2246102SN/A bool isLLSC = pkt->isLLSC(); 2253170SN/A 2263170SN/A // Initialize return value. Non-conditional stores always 2273170SN/A // succeed. Assume conditional stores will fail until proven 2283170SN/A // otherwise. 2299080Smatt.evans@arm.com bool allowStore = !isLLSC; 2303170SN/A 2319080Smatt.evans@arm.com // Iterate over list. Note that there could be multiple matching records, 2329080Smatt.evans@arm.com // as more than one context could have done a load locked to this location. 2339080Smatt.evans@arm.com // Only remove records when we succeed in finding a record for (xc, addr); 2349080Smatt.evans@arm.com // then, remove all records with this address. Failed store-conditionals do 2359080Smatt.evans@arm.com // not blow unrelated reservations. 2363170SN/A list<LockedAddr>::iterator i = lockedAddrList.begin(); 2373170SN/A 2389080Smatt.evans@arm.com if (isLLSC) { 2399080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2409080Smatt.evans@arm.com if (i->addr == paddr && i->matchesContext(req)) { 2419080Smatt.evans@arm.com // it's a store conditional, and as far as the memory system can 2429080Smatt.evans@arm.com // tell, the requesting context's lock is still valid. 2435714SN/A DPRINTF(LLSC, "StCond success: context %d addr %#x\n", 2445714SN/A req->contextId(), paddr); 2459080Smatt.evans@arm.com allowStore = true; 2469080Smatt.evans@arm.com break; 2473170SN/A } 2489080Smatt.evans@arm.com // If we didn't find a match, keep searching! Someone else may well 2499080Smatt.evans@arm.com // have a reservation on this line here but we may find ours in just 2509080Smatt.evans@arm.com // a little while. 2519080Smatt.evans@arm.com i++; 2523170SN/A } 2539080Smatt.evans@arm.com req->setExtraData(allowStore ? 1 : 0); 2549080Smatt.evans@arm.com } 2559080Smatt.evans@arm.com // LLSCs that succeeded AND non-LLSC stores both fall into here: 2569080Smatt.evans@arm.com if (allowStore) { 2579080Smatt.evans@arm.com // We write address paddr. However, there may be several entries with a 2589080Smatt.evans@arm.com // reservation on this address (for other contextIds) and they must all 2599080Smatt.evans@arm.com // be removed. 2609080Smatt.evans@arm.com i = lockedAddrList.begin(); 2619080Smatt.evans@arm.com while (i != lockedAddrList.end()) { 2629080Smatt.evans@arm.com if (i->addr == paddr) { 2639080Smatt.evans@arm.com DPRINTF(LLSC, "Erasing lock record: context %d addr %#x\n", 2649080Smatt.evans@arm.com i->contextId, paddr); 26510102Sali.saidi@arm.com // For ARM, a spinlock would typically include a Wait 26610102Sali.saidi@arm.com // For Event (WFE) to conserve energy. The ARMv8 26710102Sali.saidi@arm.com // architecture specifies that an event is 26810102Sali.saidi@arm.com // automatically generated when clearing the exclusive 26910102Sali.saidi@arm.com // monitor to wake up the processor in WFE. 27010102Sali.saidi@arm.com system()->getThreadContext(i->contextId)->getCpuPtr()->wakeup(); 2719080Smatt.evans@arm.com i = lockedAddrList.erase(i); 2729080Smatt.evans@arm.com } else { 2739080Smatt.evans@arm.com i++; 2749080Smatt.evans@arm.com } 2753170SN/A } 2763170SN/A } 2773170SN/A 2789080Smatt.evans@arm.com return allowStore; 2793170SN/A} 2803170SN/A 2814626SN/A 2824626SN/A#if TRACING_ON 2834626SN/A 2849931SAli.Saidi@ARM.com#define CASE(A, T) \ 2859931SAli.Saidi@ARM.com case sizeof(T): \ 2869931SAli.Saidi@ARM.com DPRINTF(MemoryAccess,"%s from %s of size %i on address 0x%x data " \ 2879931SAli.Saidi@ARM.com "0x%x %c\n", A, system()->getMasterName(pkt->req->masterId()),\ 2889931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), pkt->get<T>(), \ 2899931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 2904626SN/A break 2914626SN/A 2924626SN/A 2934626SN/A#define TRACE_PACKET(A) \ 2944626SN/A do { \ 2954626SN/A switch (pkt->getSize()) { \ 2964626SN/A CASE(A, uint64_t); \ 2974626SN/A CASE(A, uint32_t); \ 2984626SN/A CASE(A, uint16_t); \ 2994626SN/A CASE(A, uint8_t); \ 3004626SN/A default: \ 3019931SAli.Saidi@ARM.com DPRINTF(MemoryAccess, "%s from %s of size %i on address 0x%x %c\n",\ 3029931SAli.Saidi@ARM.com A, system()->getMasterName(pkt->req->masterId()), \ 3039931SAli.Saidi@ARM.com pkt->getSize(), pkt->getAddr(), \ 3049931SAli.Saidi@ARM.com pkt->req->isUncacheable() ? 'U' : 'C'); \ 3059931SAli.Saidi@ARM.com DDUMP(MemoryAccess, pkt->getPtr<uint8_t>(), pkt->getSize()); \ 3069931SAli.Saidi@ARM.com } \ 3074626SN/A } while (0) 3084626SN/A 3094626SN/A#else 3104626SN/A 3114626SN/A#define TRACE_PACKET(A) 3124626SN/A 3134626SN/A#endif 3144626SN/A 3158931Sandreas.hansson@arm.comvoid 3168931Sandreas.hansson@arm.comAbstractMemory::access(PacketPtr pkt) 3172413SN/A{ 3189405Sandreas.hansson@arm.com assert(AddrRange(pkt->getAddr(), 3199405Sandreas.hansson@arm.com pkt->getAddr() + pkt->getSize() - 1).isSubset(range)); 3202414SN/A 3214626SN/A if (pkt->memInhibitAsserted()) { 3224626SN/A DPRINTF(MemoryAccess, "mem inhibited on 0x%x: not responding\n", 3234626SN/A pkt->getAddr()); 3248931Sandreas.hansson@arm.com return; 3253175SN/A } 3264626SN/A 3279405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 3284626SN/A 3294626SN/A if (pkt->cmd == MemCmd::SwapReq) { 3308931Sandreas.hansson@arm.com TheISA::IntReg overwrite_val; 3314040SN/A bool overwrite_mem; 3324040SN/A uint64_t condition_val64; 3334040SN/A uint32_t condition_val32; 3344040SN/A 3355477SN/A if (!pmemAddr) 3365477SN/A panic("Swap only works if there is real memory (i.e. null=False)"); 3378931Sandreas.hansson@arm.com assert(sizeof(TheISA::IntReg) >= pkt->getSize()); 3384040SN/A 3394040SN/A overwrite_mem = true; 3404040SN/A // keep a copy of our possible write value, and copy what is at the 3414040SN/A // memory address into the packet 3424052SN/A std::memcpy(&overwrite_val, pkt->getPtr<uint8_t>(), pkt->getSize()); 3434626SN/A std::memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3444040SN/A 3454040SN/A if (pkt->req->isCondSwap()) { 3464040SN/A if (pkt->getSize() == sizeof(uint64_t)) { 3474052SN/A condition_val64 = pkt->req->getExtraData(); 3484626SN/A overwrite_mem = !std::memcmp(&condition_val64, hostAddr, 3494626SN/A sizeof(uint64_t)); 3504040SN/A } else if (pkt->getSize() == sizeof(uint32_t)) { 3514052SN/A condition_val32 = (uint32_t)pkt->req->getExtraData(); 3524626SN/A overwrite_mem = !std::memcmp(&condition_val32, hostAddr, 3534626SN/A sizeof(uint32_t)); 3544040SN/A } else 3554040SN/A panic("Invalid size for conditional read/write\n"); 3564040SN/A } 3574040SN/A 3584040SN/A if (overwrite_mem) 3594626SN/A std::memcpy(hostAddr, &overwrite_val, pkt->getSize()); 3604040SN/A 3616429SN/A assert(!pkt->req->isInstFetch()); 3624626SN/A TRACE_PACKET("Read/Write"); 3639053Sdam.sunwoo@arm.com numOther[pkt->req->masterId()]++; 3644626SN/A } else if (pkt->isRead()) { 3654626SN/A assert(!pkt->isWrite()); 3666102SN/A if (pkt->isLLSC()) { 3674626SN/A trackLoadLocked(pkt); 3684040SN/A } 3695477SN/A if (pmemAddr) 3705477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 3716429SN/A TRACE_PACKET(pkt->req->isInstFetch() ? "IFetch" : "Read"); 3729053Sdam.sunwoo@arm.com numReads[pkt->req->masterId()]++; 3739053Sdam.sunwoo@arm.com bytesRead[pkt->req->masterId()] += pkt->getSize(); 3748719SN/A if (pkt->req->isInstFetch()) 3759053Sdam.sunwoo@arm.com bytesInstRead[pkt->req->masterId()] += pkt->getSize(); 3764626SN/A } else if (pkt->isWrite()) { 3774626SN/A if (writeOK(pkt)) { 3789663Suri.wiener@arm.com if (pmemAddr) { 3795477SN/A memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 3809663Suri.wiener@arm.com DPRINTF(MemoryAccess, "%s wrote %x bytes to address %x\n", 3819663Suri.wiener@arm.com __func__, pkt->getSize(), pkt->getAddr()); 3829663Suri.wiener@arm.com } 3836429SN/A assert(!pkt->req->isInstFetch()); 3844626SN/A TRACE_PACKET("Write"); 3859053Sdam.sunwoo@arm.com numWrites[pkt->req->masterId()]++; 3869053Sdam.sunwoo@arm.com bytesWritten[pkt->req->masterId()] += pkt->getSize(); 3874626SN/A } 3884626SN/A } else if (pkt->isInvalidate()) { 3898931Sandreas.hansson@arm.com // no need to do anything 3904040SN/A } else { 3912413SN/A panic("unimplemented"); 3922413SN/A } 3932420SN/A 3944626SN/A if (pkt->needsResponse()) { 3958931Sandreas.hansson@arm.com pkt->makeResponse(); 3964626SN/A } 3972413SN/A} 3982413SN/A 3998931Sandreas.hansson@arm.comvoid 4008931Sandreas.hansson@arm.comAbstractMemory::functionalAccess(PacketPtr pkt) 4018931Sandreas.hansson@arm.com{ 4029405Sandreas.hansson@arm.com assert(AddrRange(pkt->getAddr(), 4039405Sandreas.hansson@arm.com pkt->getAddr() + pkt->getSize() - 1).isSubset(range)); 4044626SN/A 4059405Sandreas.hansson@arm.com uint8_t *hostAddr = pmemAddr + pkt->getAddr() - range.start(); 4064626SN/A 4075314SN/A if (pkt->isRead()) { 4085477SN/A if (pmemAddr) 4095477SN/A memcpy(pkt->getPtr<uint8_t>(), hostAddr, pkt->getSize()); 4104626SN/A TRACE_PACKET("Read"); 4118931Sandreas.hansson@arm.com pkt->makeResponse(); 4125314SN/A } else if (pkt->isWrite()) { 4135477SN/A if (pmemAddr) 4145477SN/A memcpy(hostAddr, pkt->getPtr<uint8_t>(), pkt->getSize()); 4154626SN/A TRACE_PACKET("Write"); 4168931Sandreas.hansson@arm.com pkt->makeResponse(); 4175314SN/A } else if (pkt->isPrint()) { 4185315SN/A Packet::PrintReqState *prs = 4195315SN/A dynamic_cast<Packet::PrintReqState*>(pkt->senderState); 4208992SAli.Saidi@ARM.com assert(prs); 4215315SN/A // Need to call printLabels() explicitly since we're not going 4225315SN/A // through printObj(). 4235314SN/A prs->printLabels(); 4245315SN/A // Right now we just print the single byte at the specified address. 4255314SN/A ccprintf(prs->os, "%s%#x\n", prs->curPrefix(), *hostAddr); 4264626SN/A } else { 4278931Sandreas.hansson@arm.com panic("AbstractMemory: unimplemented functional command %s", 4284626SN/A pkt->cmdString()); 4294626SN/A } 4304490SN/A} 431