HMCController.py revision 11184:07b0dacf27d6 
1# Copyright (c) 2012-2013 ARM Limited
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13# Copyright (c) 2015 The University of Bologna
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38#
39# Authors: Erfan Azarkhish
40
41from m5.params import *
42from XBar import *
43
44# References:
45# [1] http://www.open-silicon.com/open-silicon-ips/hmc/
46# [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link
47#   Power Management and Two-Level Prefetching," TVLSI 2015
48
49# The HMCController class highlights the fact that a component is required
50# between host and HMC to convert the host protocol (AXI for example) to the
51# serial links protocol. Moreover, this component should have large internal
52# queueing to hide the access latency of the HMC.
53# Plus, this controller can implement more advanced global scheduling policies
54# and can reorder and steer transactions if required. A good example of such
55# component is available in [1].
56# Also in [2] there is a similar component which is connected to all serial
57# links, and it schedules the requests to the ones which are not busy.
58# These two references clarify two things:
59# 1. The serial links support the same address range and packets can travel
60#  over any of them.
61# 2. One host can be connected to more than 1 serial link simply to achieve
62#  higher bandwidth, and not for any other reason.
63
64# In this model, we have used a round-robin counter, because it is the
65# simplest way to schedule packets over the non-busy serial links. However,
66# more advanced scheduling algorithms are possible and even host can dedicate
67# each serial link to a portion of the address space and interleave packets
68# over them. Yet in this model, we have not made any such assumptions on the
69# address space.
70
71class HMCController(NoncoherentXBar):
72        type = 'HMCController'
73        cxx_header = "mem/hmc_controller.hh"
74