DRAMSim2.py revision 10066:06a33d872798 
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365081Sgblack@eecs.umich.edu# Authors: Andreas Hansson
375081Sgblack@eecs.umich.edu
385081Sgblack@eecs.umich.edufrom m5.params import *
395081Sgblack@eecs.umich.edufrom AbstractMemory import *
405081Sgblack@eecs.umich.edu
415081Sgblack@eecs.umich.edu# A wrapper for DRAMSim2 multi-channel memory controller
425081Sgblack@eecs.umich.educlass DRAMSim2(AbstractMemory):
435081Sgblack@eecs.umich.edu    type = 'DRAMSim2'
445081Sgblack@eecs.umich.edu    cxx_header = "mem/dramsim2.hh"
455081Sgblack@eecs.umich.edu
465081Sgblack@eecs.umich.edu    # A single port for now
47    port = SlavePort("Slave port")
48
49    deviceConfigFile = Param.String("ini/DDR3_micron_32M_8B_x8_sg15.ini",
50                                    "Device configuration file")
51    systemConfigFile = Param.String("system.ini.example",
52                                    "Memory organisation configuration file")
53    filePath = Param.String("ext/dramsim2/DRAMSim2/",
54                            "Directory to prepend to file names")
55    traceFile = Param.String("", "Output file for trace generation")
56    enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output")
57