Bridge.py revision 9338 
1# Copyright (c) 2012 ARM Limited
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39# Authors: Ali Saidi
40#          Andreas Hansson
41
42from m5.params import *
43from MemObject import MemObject
44
45class Bridge(MemObject):
46    type = 'Bridge'
47    cxx_header = "mem/bridge.hh"
48    slave = SlavePort('Slave port')
49    master = MasterPort('Master port')
50    req_size = Param.Int(16, "The number of requests to buffer")
51    resp_size = Param.Int(16, "The number of responses to buffer")
52    delay = Param.Latency('0ns', "The latency of this bridge")
53    ranges = VectorParam.AddrRange([AllMemory],
54                                   "Address ranges to pass through the bridge")
55