vector_register_file.hh revision 11308:7d8836fd043d 
1/*
2 * Copyright (c) 2015 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * For use for simulation and test purposes only
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions are met:
9 *
10 * 1. Redistributions of source code must retain the above copyright notice,
11 * this list of conditions and the following disclaimer.
12 *
13 * 2. Redistributions in binary form must reproduce the above copyright notice,
14 * this list of conditions and the following disclaimer in the documentation
15 * and/or other materials provided with the distribution.
16 *
17 * 3. Neither the name of the copyright holder nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
25 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
31 * POSSIBILITY OF SUCH DAMAGE.
32 *
33 * Author: John Kalamatianos
34 */
35
36#ifndef __VECTOR_REGISTER_FILE_HH__
37#define __VECTOR_REGISTER_FILE_HH__
38
39#include <list>
40
41#include "base/statistics.hh"
42#include "base/types.hh"
43#include "gpu-compute/vector_register_state.hh"
44#include "sim/sim_object.hh"
45
46class ComputeUnit;
47class Shader;
48class SimplePoolManager;
49class Wavefront;
50
51struct VectorRegisterFileParams;
52
53enum class VrfAccessType : uint8_t
54{
55    READ = 0x01,
56    WRITE = 0x02,
57    RD_WR = READ | WRITE
58};
59
60// Vector Register File
61class VectorRegisterFile : public SimObject
62{
63  public:
64    VectorRegisterFile(const VectorRegisterFileParams *p);
65
66    void setParent(ComputeUnit *_computeUnit);
67
68    // Read a register
69    template<typename T>
70    T
71    read(int regIdx, int threadId=0)
72    {
73        T p0 = vgprState->read<T>(regIdx, threadId);
74
75        return p0;
76    }
77
78    // Write a register
79    template<typename T>
80    void
81    write(int regIdx, T value, int threadId=0)
82    {
83        vgprState->write<T>(regIdx, value, threadId);
84    }
85
86    uint8_t regBusy(int idx, uint32_t operandSize) const;
87    uint8_t regNxtBusy(int idx, uint32_t operandSize) const;
88
89    int numRegs() const { return numRegsPerSimd; }
90
91    void markReg(int regIdx, uint32_t operandSize, uint8_t value);
92    void preMarkReg(int regIdx, uint32_t operandSize, uint8_t value);
93
94    virtual void exec(GPUDynInstPtr ii, Wavefront *w);
95
96    virtual int exec(uint64_t dynamic_id, Wavefront *w,
97                     std::vector<uint32_t> &regVec, uint32_t operandSize,
98                     uint64_t timestamp);
99
100    bool operandsReady(Wavefront *w, GPUDynInstPtr ii) const;
101    virtual void updateEvents() { }
102    virtual void updateResources(Wavefront *w, GPUDynInstPtr ii);
103
104    virtual bool
105    isReadConflict(int memWfId, int exeWfId) const
106    {
107        return false;
108    }
109
110    virtual bool
111    isWriteConflict(int memWfId, int exeWfId) const
112    {
113        return false;
114    }
115
116    virtual bool vrfOperandAccessReady(uint64_t dynamic_id, Wavefront *w,
117                                       GPUDynInstPtr ii,
118                                       VrfAccessType accessType);
119
120    virtual bool vrfOperandAccessReady(Wavefront *w, GPUDynInstPtr ii,
121                                       VrfAccessType accessType);
122
123    SimplePoolManager *manager;
124
125  protected:
126    ComputeUnit* computeUnit;
127    int simdId;
128
129    // flag indicating if a register is busy
130    std::vector<uint8_t> busy;
131    // flag indicating if a register will be busy (by instructions
132    // in the SIMD pipeline)
133    std::vector<uint8_t> nxtBusy;
134
135    // numer of registers (bank size) per simd unit (bank)
136    int numRegsPerSimd;
137
138    // vector register state
139    VecRegisterState *vgprState;
140};
141
142#endif // __VECTOR_REGISTER_FILE_HH__
143