compute_unit.cc revision 12749
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1712697Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its 1812697Santhony.gutierrez@amd.com * contributors may be used to endorse or promote products derived from this 1912697Santhony.gutierrez@amd.com * software without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3312697Santhony.gutierrez@amd.com * Authors: John Kalamatianos, 3412697Santhony.gutierrez@amd.com * Anthony Gutierrez 3511308Santhony.gutierrez@amd.com */ 3612697Santhony.gutierrez@amd.com 3711534Sjohn.kalamatianos@amd.com#include "gpu-compute/compute_unit.hh" 3811308Santhony.gutierrez@amd.com 3911534Sjohn.kalamatianos@amd.com#include <limits> 4011308Santhony.gutierrez@amd.com 4111308Santhony.gutierrez@amd.com#include "base/output.hh" 4211308Santhony.gutierrez@amd.com#include "debug/GPUDisp.hh" 4311308Santhony.gutierrez@amd.com#include "debug/GPUExec.hh" 4411308Santhony.gutierrez@amd.com#include "debug/GPUFetch.hh" 4511308Santhony.gutierrez@amd.com#include "debug/GPUMem.hh" 4611308Santhony.gutierrez@amd.com#include "debug/GPUPort.hh" 4711308Santhony.gutierrez@amd.com#include "debug/GPUPrefetch.hh" 4811308Santhony.gutierrez@amd.com#include "debug/GPUSync.hh" 4911308Santhony.gutierrez@amd.com#include "debug/GPUTLB.hh" 5011308Santhony.gutierrez@amd.com#include "gpu-compute/dispatcher.hh" 5111308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_dyn_inst.hh" 5211308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_static_inst.hh" 5311308Santhony.gutierrez@amd.com#include "gpu-compute/ndrange.hh" 5411308Santhony.gutierrez@amd.com#include "gpu-compute/shader.hh" 5511308Santhony.gutierrez@amd.com#include "gpu-compute/simple_pool_manager.hh" 5611308Santhony.gutierrez@amd.com#include "gpu-compute/vector_register_file.hh" 5711308Santhony.gutierrez@amd.com#include "gpu-compute/wavefront.hh" 5811308Santhony.gutierrez@amd.com#include "mem/page_table.hh" 5911308Santhony.gutierrez@amd.com#include "sim/process.hh" 6011308Santhony.gutierrez@amd.com 6111308Santhony.gutierrez@amd.comComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p), 6211308Santhony.gutierrez@amd.com scoreboardCheckStage(p), scheduleStage(p), execStage(p), 6311308Santhony.gutierrez@amd.com globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0), 6411308Santhony.gutierrez@amd.com cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs), 6511308Santhony.gutierrez@amd.com spBypassPipeLength(p->spbypass_pipe_length), 6611308Santhony.gutierrez@amd.com dpBypassPipeLength(p->dpbypass_pipe_length), 6711308Santhony.gutierrez@amd.com issuePeriod(p->issue_period), 6811308Santhony.gutierrez@amd.com numGlbMemUnits(p->num_global_mem_pipes), 6911308Santhony.gutierrez@amd.com numLocMemUnits(p->num_shared_mem_pipes), 7011308Santhony.gutierrez@amd.com perLaneTLB(p->perLaneTLB), prefetchDepth(p->prefetch_depth), 7111308Santhony.gutierrez@amd.com prefetchStride(p->prefetch_stride), prefetchType(p->prefetch_prev_type), 7211308Santhony.gutierrez@amd.com xact_cas_mode(p->xactCasMode), debugSegFault(p->debugSegFault), 7311308Santhony.gutierrez@amd.com functionalTLB(p->functionalTLB), localMemBarrier(p->localMemBarrier), 7411308Santhony.gutierrez@amd.com countPages(p->countPages), barrier_id(0), 7511308Santhony.gutierrez@amd.com vrfToCoalescerBusWidth(p->vrf_to_coalescer_bus_width), 7611308Santhony.gutierrez@amd.com coalescerToVrfBusWidth(p->coalescer_to_vrf_bus_width), 7711308Santhony.gutierrez@amd.com req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()), 7811308Santhony.gutierrez@amd.com resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()), 7912680Sgiacomo.travaglini@arm.com _masterId(p->system->getMasterId(this, "ComputeUnit")), 8011698Santhony.gutierrez@amd.com lds(*p->localDataStore), _cacheLineSize(p->system->cacheLineSize()), 8111698Santhony.gutierrez@amd.com globalSeqNum(0), wavefrontSize(p->wfSize), 8211692Santhony.gutierrez@amd.com kernelLaunchInst(new KernelLaunchStaticInst()) 8311308Santhony.gutierrez@amd.com{ 8411534Sjohn.kalamatianos@amd.com /** 8511534Sjohn.kalamatianos@amd.com * This check is necessary because std::bitset only provides conversion 8611534Sjohn.kalamatianos@amd.com * to unsigned long or unsigned long long via to_ulong() or to_ullong(). 8711534Sjohn.kalamatianos@amd.com * there are * a few places in the code where to_ullong() is used, however 8811534Sjohn.kalamatianos@amd.com * if VSZ is larger than a value the host can support then bitset will 8911534Sjohn.kalamatianos@amd.com * throw a runtime exception. we should remove all use of to_long() or 9011534Sjohn.kalamatianos@amd.com * to_ullong() so we can have VSZ greater than 64b, however until that is 9111534Sjohn.kalamatianos@amd.com * done this assert is required. 9211534Sjohn.kalamatianos@amd.com */ 9311534Sjohn.kalamatianos@amd.com fatal_if(p->wfSize > std::numeric_limits<unsigned long long>::digits || 9411534Sjohn.kalamatianos@amd.com p->wfSize <= 0, 9511534Sjohn.kalamatianos@amd.com "WF size is larger than the host can support"); 9611534Sjohn.kalamatianos@amd.com fatal_if(!isPowerOf2(wavefrontSize), 9711534Sjohn.kalamatianos@amd.com "Wavefront size should be a power of 2"); 9811308Santhony.gutierrez@amd.com // calculate how many cycles a vector load or store will need to transfer 9911308Santhony.gutierrez@amd.com // its data over the corresponding buses 10011534Sjohn.kalamatianos@amd.com numCyclesPerStoreTransfer = 10111534Sjohn.kalamatianos@amd.com (uint32_t)ceil((double)(wfSize() * sizeof(uint32_t)) / 10211534Sjohn.kalamatianos@amd.com (double)vrfToCoalescerBusWidth); 10311308Santhony.gutierrez@amd.com 10411534Sjohn.kalamatianos@amd.com numCyclesPerLoadTransfer = (wfSize() * sizeof(uint32_t)) 10511308Santhony.gutierrez@amd.com / coalescerToVrfBusWidth; 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com lastVaddrWF.resize(numSIMDs); 10811308Santhony.gutierrez@amd.com wfList.resize(numSIMDs); 10911308Santhony.gutierrez@amd.com 11011308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 11111308Santhony.gutierrez@amd.com lastVaddrWF[j].resize(p->n_wf); 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com for (int i = 0; i < p->n_wf; ++i) { 11411534Sjohn.kalamatianos@amd.com lastVaddrWF[j][i].resize(wfSize()); 11511308Santhony.gutierrez@amd.com 11611308Santhony.gutierrez@amd.com wfList[j].push_back(p->wavefronts[j * p->n_wf + i]); 11711308Santhony.gutierrez@amd.com wfList[j][i]->setParent(this); 11811308Santhony.gutierrez@amd.com 11911534Sjohn.kalamatianos@amd.com for (int k = 0; k < wfSize(); ++k) { 12011308Santhony.gutierrez@amd.com lastVaddrWF[j][i][k] = 0; 12111308Santhony.gutierrez@amd.com } 12211308Santhony.gutierrez@amd.com } 12311308Santhony.gutierrez@amd.com } 12411308Santhony.gutierrez@amd.com 12511534Sjohn.kalamatianos@amd.com lastVaddrSimd.resize(numSIMDs); 12611308Santhony.gutierrez@amd.com 12711308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 12811534Sjohn.kalamatianos@amd.com lastVaddrSimd[i].resize(wfSize(), 0); 12911308Santhony.gutierrez@amd.com } 13011308Santhony.gutierrez@amd.com 13111534Sjohn.kalamatianos@amd.com lastVaddrCU.resize(wfSize()); 13211308Santhony.gutierrez@amd.com 13311308Santhony.gutierrez@amd.com lds.setParent(this); 13411308Santhony.gutierrez@amd.com 13511308Santhony.gutierrez@amd.com if (p->execPolicy == "OLDEST-FIRST") { 13611308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::OLDEST; 13711308Santhony.gutierrez@amd.com } else if (p->execPolicy == "ROUND-ROBIN") { 13811308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::RR; 13911308Santhony.gutierrez@amd.com } else { 14011308Santhony.gutierrez@amd.com fatal("Invalid WF execution policy (CU)\n"); 14111308Santhony.gutierrez@amd.com } 14211308Santhony.gutierrez@amd.com 14311534Sjohn.kalamatianos@amd.com memPort.resize(wfSize()); 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com // resize the tlbPort vectorArray 14611534Sjohn.kalamatianos@amd.com int tlbPort_width = perLaneTLB ? wfSize() : 1; 14711308Santhony.gutierrez@amd.com tlbPort.resize(tlbPort_width); 14811308Santhony.gutierrez@amd.com 14911308Santhony.gutierrez@amd.com cuExitCallback = new CUExitCallback(this); 15011308Santhony.gutierrez@amd.com registerExitCallback(cuExitCallback); 15111308Santhony.gutierrez@amd.com 15211308Santhony.gutierrez@amd.com xactCasLoadMap.clear(); 15311308Santhony.gutierrez@amd.com lastExecCycle.resize(numSIMDs, 0); 15411308Santhony.gutierrez@amd.com 15511308Santhony.gutierrez@amd.com for (int i = 0; i < vrf.size(); ++i) { 15611308Santhony.gutierrez@amd.com vrf[i]->setParent(this); 15711308Santhony.gutierrez@amd.com } 15811308Santhony.gutierrez@amd.com 15911308Santhony.gutierrez@amd.com numVecRegsPerSimd = vrf[0]->numRegs(); 16011308Santhony.gutierrez@amd.com} 16111308Santhony.gutierrez@amd.com 16211308Santhony.gutierrez@amd.comComputeUnit::~ComputeUnit() 16311308Santhony.gutierrez@amd.com{ 16411308Santhony.gutierrez@amd.com // Delete wavefront slots 16511534Sjohn.kalamatianos@amd.com for (int j = 0; j < numSIMDs; ++j) { 16611308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 16711308Santhony.gutierrez@amd.com delete wfList[j][i]; 16811308Santhony.gutierrez@amd.com } 16911534Sjohn.kalamatianos@amd.com lastVaddrSimd[j].clear(); 17011534Sjohn.kalamatianos@amd.com } 17111534Sjohn.kalamatianos@amd.com lastVaddrCU.clear(); 17211308Santhony.gutierrez@amd.com readyList.clear(); 17311308Santhony.gutierrez@amd.com waveStatusList.clear(); 17411308Santhony.gutierrez@amd.com dispatchList.clear(); 17511308Santhony.gutierrez@amd.com vectorAluInstAvail.clear(); 17611308Santhony.gutierrez@amd.com delete cuExitCallback; 17711308Santhony.gutierrez@amd.com delete ldsPort; 17811308Santhony.gutierrez@amd.com} 17911308Santhony.gutierrez@amd.com 18011308Santhony.gutierrez@amd.comvoid 18111657Salexandru.dutu@amd.comComputeUnit::fillKernelState(Wavefront *w, NDRange *ndr) 18211308Santhony.gutierrez@amd.com{ 18311308Santhony.gutierrez@amd.com w->resizeRegFiles(ndr->q.cRegCount, ndr->q.sRegCount, ndr->q.dRegCount); 18411308Santhony.gutierrez@amd.com 18511639Salexandru.dutu@amd.com w->workGroupSz[0] = ndr->q.wgSize[0]; 18611639Salexandru.dutu@amd.com w->workGroupSz[1] = ndr->q.wgSize[1]; 18711639Salexandru.dutu@amd.com w->workGroupSz[2] = ndr->q.wgSize[2]; 18811639Salexandru.dutu@amd.com w->wgSz = w->workGroupSz[0] * w->workGroupSz[1] * w->workGroupSz[2]; 18911639Salexandru.dutu@amd.com w->gridSz[0] = ndr->q.gdSize[0]; 19011639Salexandru.dutu@amd.com w->gridSz[1] = ndr->q.gdSize[1]; 19111639Salexandru.dutu@amd.com w->gridSz[2] = ndr->q.gdSize[2]; 19211308Santhony.gutierrez@amd.com w->kernelArgs = ndr->q.args; 19311308Santhony.gutierrez@amd.com w->privSizePerItem = ndr->q.privMemPerItem; 19411308Santhony.gutierrez@amd.com w->spillSizePerItem = ndr->q.spillMemPerItem; 19511308Santhony.gutierrez@amd.com w->roBase = ndr->q.roMemStart; 19611308Santhony.gutierrez@amd.com w->roSize = ndr->q.roMemTotal; 19711657Salexandru.dutu@amd.com w->computeActualWgSz(ndr); 19811308Santhony.gutierrez@amd.com} 19911308Santhony.gutierrez@amd.com 20011308Santhony.gutierrez@amd.comvoid 20111308Santhony.gutierrez@amd.comComputeUnit::updateEvents() { 20211308Santhony.gutierrez@amd.com 20311308Santhony.gutierrez@amd.com if (!timestampVec.empty()) { 20411308Santhony.gutierrez@amd.com uint32_t vecSize = timestampVec.size(); 20511308Santhony.gutierrez@amd.com uint32_t i = 0; 20611308Santhony.gutierrez@amd.com while (i < vecSize) { 20711308Santhony.gutierrez@amd.com if (timestampVec[i] <= shader->tick_cnt) { 20811308Santhony.gutierrez@amd.com std::pair<uint32_t, uint32_t> regInfo = regIdxVec[i]; 20911308Santhony.gutierrez@amd.com vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t), 21011308Santhony.gutierrez@amd.com statusVec[i]); 21111308Santhony.gutierrez@amd.com timestampVec.erase(timestampVec.begin() + i); 21211308Santhony.gutierrez@amd.com regIdxVec.erase(regIdxVec.begin() + i); 21311308Santhony.gutierrez@amd.com statusVec.erase(statusVec.begin() + i); 21411308Santhony.gutierrez@amd.com --vecSize; 21511308Santhony.gutierrez@amd.com --i; 21611308Santhony.gutierrez@amd.com } 21711308Santhony.gutierrez@amd.com ++i; 21811308Santhony.gutierrez@amd.com } 21911308Santhony.gutierrez@amd.com } 22011308Santhony.gutierrez@amd.com 22111308Santhony.gutierrez@amd.com for (int i = 0; i< numSIMDs; ++i) { 22211308Santhony.gutierrez@amd.com vrf[i]->updateEvents(); 22311308Santhony.gutierrez@amd.com } 22411308Santhony.gutierrez@amd.com} 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.com 22711308Santhony.gutierrez@amd.comvoid 22811657Salexandru.dutu@amd.comComputeUnit::startWavefront(Wavefront *w, int waveId, LdsChunk *ldsChunk, 22911657Salexandru.dutu@amd.com NDRange *ndr) 23011308Santhony.gutierrez@amd.com{ 23111308Santhony.gutierrez@amd.com static int _n_wave = 0; 23211308Santhony.gutierrez@amd.com 23311638Salexandru.dutu@amd.com VectorMask init_mask; 23411638Salexandru.dutu@amd.com init_mask.reset(); 23511638Salexandru.dutu@amd.com 23611638Salexandru.dutu@amd.com for (int k = 0; k < wfSize(); ++k) { 23711657Salexandru.dutu@amd.com if (k + waveId * wfSize() < w->actualWgSzTotal) 23811638Salexandru.dutu@amd.com init_mask[k] = 1; 23911638Salexandru.dutu@amd.com } 24011638Salexandru.dutu@amd.com 24111639Salexandru.dutu@amd.com w->kernId = ndr->dispatchId; 24211643Salexandru.dutu@amd.com w->wfId = waveId; 24311639Salexandru.dutu@amd.com w->initMask = init_mask.to_ullong(); 24411308Santhony.gutierrez@amd.com 24511534Sjohn.kalamatianos@amd.com for (int k = 0; k < wfSize(); ++k) { 24611657Salexandru.dutu@amd.com w->workItemId[0][k] = (k + waveId * wfSize()) % w->actualWgSz[0]; 24711657Salexandru.dutu@amd.com w->workItemId[1][k] = ((k + waveId * wfSize()) / w->actualWgSz[0]) % 24811657Salexandru.dutu@amd.com w->actualWgSz[1]; 24911657Salexandru.dutu@amd.com w->workItemId[2][k] = (k + waveId * wfSize()) / 25011657Salexandru.dutu@amd.com (w->actualWgSz[0] * w->actualWgSz[1]); 25111308Santhony.gutierrez@amd.com 25211657Salexandru.dutu@amd.com w->workItemFlatId[k] = w->workItemId[2][k] * w->actualWgSz[0] * 25311657Salexandru.dutu@amd.com w->actualWgSz[1] + w->workItemId[1][k] * w->actualWgSz[0] + 25411639Salexandru.dutu@amd.com w->workItemId[0][k]; 25511308Santhony.gutierrez@amd.com } 25611308Santhony.gutierrez@amd.com 25711657Salexandru.dutu@amd.com w->barrierSlots = divCeil(w->actualWgSzTotal, wfSize()); 25811308Santhony.gutierrez@amd.com 25911639Salexandru.dutu@amd.com w->barCnt.resize(wfSize(), 0); 26011308Santhony.gutierrez@amd.com 26111639Salexandru.dutu@amd.com w->maxBarCnt = 0; 26211639Salexandru.dutu@amd.com w->oldBarrierCnt = 0; 26311639Salexandru.dutu@amd.com w->barrierCnt = 0; 26411308Santhony.gutierrez@amd.com 26511638Salexandru.dutu@amd.com w->privBase = ndr->q.privMemStart; 26611638Salexandru.dutu@amd.com ndr->q.privMemStart += ndr->q.privMemPerItem * wfSize(); 26711638Salexandru.dutu@amd.com 26811638Salexandru.dutu@amd.com w->spillBase = ndr->q.spillMemStart; 26911638Salexandru.dutu@amd.com ndr->q.spillMemStart += ndr->q.spillMemPerItem * wfSize(); 27011638Salexandru.dutu@amd.com 27111638Salexandru.dutu@amd.com w->pushToReconvergenceStack(0, UINT32_MAX, init_mask.to_ulong()); 27211308Santhony.gutierrez@amd.com 27311308Santhony.gutierrez@amd.com // WG state 27411639Salexandru.dutu@amd.com w->wgId = ndr->globalWgId; 27511639Salexandru.dutu@amd.com w->dispatchId = ndr->dispatchId; 27611639Salexandru.dutu@amd.com w->workGroupId[0] = w->wgId % ndr->numWg[0]; 27711639Salexandru.dutu@amd.com w->workGroupId[1] = (w->wgId / ndr->numWg[0]) % ndr->numWg[1]; 27811639Salexandru.dutu@amd.com w->workGroupId[2] = w->wgId / (ndr->numWg[0] * ndr->numWg[1]); 27911308Santhony.gutierrez@amd.com 28011639Salexandru.dutu@amd.com w->barrierId = barrier_id; 28111308Santhony.gutierrez@amd.com w->stalledAtBarrier = false; 28211308Santhony.gutierrez@amd.com 28311638Salexandru.dutu@amd.com // set the wavefront context to have a pointer to this section of the LDS 28411638Salexandru.dutu@amd.com w->ldsChunk = ldsChunk; 28511308Santhony.gutierrez@amd.com 28611308Santhony.gutierrez@amd.com int32_t refCount M5_VAR_USED = 28711639Salexandru.dutu@amd.com lds.increaseRefCounter(w->dispatchId, w->wgId); 28811308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: increase ref ctr wg[%d] to [%d]\n", 28911639Salexandru.dutu@amd.com cu_id, w->wgId, refCount); 29011308Santhony.gutierrez@amd.com 29111308Santhony.gutierrez@amd.com w->instructionBuffer.clear(); 29211308Santhony.gutierrez@amd.com 29311308Santhony.gutierrez@amd.com if (w->pendingFetch) 29411308Santhony.gutierrez@amd.com w->dropFetch = true; 29511308Santhony.gutierrez@amd.com 29611308Santhony.gutierrez@amd.com // is this the last wavefront in the workgroup 29711308Santhony.gutierrez@amd.com // if set the spillWidth to be the remaining work-items 29811308Santhony.gutierrez@amd.com // so that the vector access is correct 29911657Salexandru.dutu@amd.com if ((waveId + 1) * wfSize() >= w->actualWgSzTotal) { 30011657Salexandru.dutu@amd.com w->spillWidth = w->actualWgSzTotal - (waveId * wfSize()); 30111308Santhony.gutierrez@amd.com } else { 30211534Sjohn.kalamatianos@amd.com w->spillWidth = wfSize(); 30311308Santhony.gutierrez@amd.com } 30411308Santhony.gutierrez@amd.com 30511308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Scheduling wfDynId/barrier_id %d/%d on CU%d: " 30611308Santhony.gutierrez@amd.com "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId); 30711308Santhony.gutierrez@amd.com 30811308Santhony.gutierrez@amd.com w->start(++_n_wave, ndr->q.code_ptr); 30911308Santhony.gutierrez@amd.com} 31011308Santhony.gutierrez@amd.com 31111308Santhony.gutierrez@amd.comvoid 31211308Santhony.gutierrez@amd.comComputeUnit::StartWorkgroup(NDRange *ndr) 31311308Santhony.gutierrez@amd.com{ 31411308Santhony.gutierrez@amd.com // reserve the LDS capacity allocated to the work group 31511308Santhony.gutierrez@amd.com // disambiguated by the dispatch ID and workgroup ID, which should be 31611308Santhony.gutierrez@amd.com // globally unique 31711308Santhony.gutierrez@amd.com LdsChunk *ldsChunk = lds.reserveSpace(ndr->dispatchId, ndr->globalWgId, 31811308Santhony.gutierrez@amd.com ndr->q.ldsSize); 31911308Santhony.gutierrez@amd.com 32011308Santhony.gutierrez@amd.com // Send L1 cache acquire 32111308Santhony.gutierrez@amd.com // isKernel + isAcquire = Kernel Begin 32211308Santhony.gutierrez@amd.com if (shader->impl_kern_boundary_sync) { 32311692Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = 32411692Santhony.gutierrez@amd.com std::make_shared<GPUDynInst>(this, nullptr, kernelLaunchInst, 32511692Santhony.gutierrez@amd.com getAndIncSeqNum()); 32611308Santhony.gutierrez@amd.com 32711308Santhony.gutierrez@amd.com gpuDynInst->useContinuation = false; 32811308Santhony.gutierrez@amd.com injectGlobalMemFence(gpuDynInst, true); 32911308Santhony.gutierrez@amd.com } 33011308Santhony.gutierrez@amd.com 33111308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by wavefront 33211308Santhony.gutierrez@amd.com int vregDemand = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 33311643Salexandru.dutu@amd.com int wave_id = 0; 33411308Santhony.gutierrez@amd.com 33511308Santhony.gutierrez@amd.com // Assign WFs by spreading them across SIMDs, 1 WF per SIMD at a time 33611308Santhony.gutierrez@amd.com for (int m = 0; m < shader->n_wf * numSIMDs; ++m) { 33711308Santhony.gutierrez@amd.com Wavefront *w = wfList[m % numSIMDs][m / numSIMDs]; 33811308Santhony.gutierrez@amd.com // Check if this wavefront slot is available: 33911308Santhony.gutierrez@amd.com // It must be stopped and not waiting 34011308Santhony.gutierrez@amd.com // for a release to complete S_RETURNING 34111308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_STOPPED) { 34211657Salexandru.dutu@amd.com fillKernelState(w, ndr); 34311308Santhony.gutierrez@amd.com // if we have scheduled all work items then stop 34411308Santhony.gutierrez@amd.com // scheduling wavefronts 34511657Salexandru.dutu@amd.com if (wave_id * wfSize() >= w->actualWgSzTotal) 34611308Santhony.gutierrez@amd.com break; 34711308Santhony.gutierrez@amd.com 34811308Santhony.gutierrez@amd.com // reserve vector registers for the scheduled wavefront 34911308Santhony.gutierrez@amd.com assert(vectorRegsReserved[m % numSIMDs] <= numVecRegsPerSimd); 35011308Santhony.gutierrez@amd.com uint32_t normSize = 0; 35111308Santhony.gutierrez@amd.com 35211308Santhony.gutierrez@amd.com w->startVgprIndex = vrf[m % numSIMDs]->manager-> 35311308Santhony.gutierrez@amd.com allocateRegion(vregDemand, &normSize); 35411308Santhony.gutierrez@amd.com 35511308Santhony.gutierrez@amd.com w->reservedVectorRegs = normSize; 35611308Santhony.gutierrez@amd.com vectorRegsReserved[m % numSIMDs] += w->reservedVectorRegs; 35711308Santhony.gutierrez@amd.com 35811657Salexandru.dutu@amd.com startWavefront(w, wave_id, ldsChunk, ndr); 35911643Salexandru.dutu@amd.com ++wave_id; 36011308Santhony.gutierrez@amd.com } 36111308Santhony.gutierrez@amd.com } 36211308Santhony.gutierrez@amd.com ++barrier_id; 36311308Santhony.gutierrez@amd.com} 36411308Santhony.gutierrez@amd.com 36511308Santhony.gutierrez@amd.comint 36611308Santhony.gutierrez@amd.comComputeUnit::ReadyWorkgroup(NDRange *ndr) 36711308Santhony.gutierrez@amd.com{ 36811308Santhony.gutierrez@amd.com // Get true size of workgroup (after clamping to grid size) 36911308Santhony.gutierrez@amd.com int trueWgSize[3]; 37011308Santhony.gutierrez@amd.com int trueWgSizeTotal = 1; 37111308Santhony.gutierrez@amd.com 37211308Santhony.gutierrez@amd.com for (int d = 0; d < 3; ++d) { 37311308Santhony.gutierrez@amd.com trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] - 37411308Santhony.gutierrez@amd.com ndr->wgId[d] * ndr->q.wgSize[d]); 37511308Santhony.gutierrez@amd.com 37611308Santhony.gutierrez@amd.com trueWgSizeTotal *= trueWgSize[d]; 37711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSize[%d] = %d\n", d, trueWgSize[d]); 37811308Santhony.gutierrez@amd.com } 37911308Santhony.gutierrez@amd.com 38011308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSizeTotal = %d\n", trueWgSizeTotal); 38111308Santhony.gutierrez@amd.com 38211308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by each 38311308Santhony.gutierrez@amd.com // work item of the work group 38411308Santhony.gutierrez@amd.com int vregDemandPerWI = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 38511308Santhony.gutierrez@amd.com bool vregAvail = true; 38611534Sjohn.kalamatianos@amd.com int numWfs = (trueWgSizeTotal + wfSize() - 1) / wfSize(); 38711308Santhony.gutierrez@amd.com int freeWfSlots = 0; 38811308Santhony.gutierrez@amd.com // check if the total number of VGPRs required by all WFs of the WG 38911308Santhony.gutierrez@amd.com // fit in the VRFs of all SIMD units 39011308Santhony.gutierrez@amd.com assert((numWfs * vregDemandPerWI) <= (numSIMDs * numVecRegsPerSimd)); 39111308Santhony.gutierrez@amd.com int numMappedWfs = 0; 39211308Santhony.gutierrez@amd.com std::vector<int> numWfsPerSimd; 39311308Santhony.gutierrez@amd.com numWfsPerSimd.resize(numSIMDs, 0); 39411308Santhony.gutierrez@amd.com // find how many free WF slots we have across all SIMDs 39511308Santhony.gutierrez@amd.com for (int j = 0; j < shader->n_wf; ++j) { 39611308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 39711308Santhony.gutierrez@amd.com if (wfList[i][j]->status == Wavefront::S_STOPPED) { 39811308Santhony.gutierrez@amd.com // count the number of free WF slots 39911308Santhony.gutierrez@amd.com ++freeWfSlots; 40011308Santhony.gutierrez@amd.com if (numMappedWfs < numWfs) { 40111308Santhony.gutierrez@amd.com // count the WFs to be assigned per SIMD 40211308Santhony.gutierrez@amd.com numWfsPerSimd[i]++; 40311308Santhony.gutierrez@amd.com } 40411308Santhony.gutierrez@amd.com numMappedWfs++; 40511308Santhony.gutierrez@amd.com } 40611308Santhony.gutierrez@amd.com } 40711308Santhony.gutierrez@amd.com } 40811308Santhony.gutierrez@amd.com 40911308Santhony.gutierrez@amd.com // if there are enough free WF slots then find if there are enough 41011308Santhony.gutierrez@amd.com // free VGPRs per SIMD based on the WF->SIMD mapping 41111308Santhony.gutierrez@amd.com if (freeWfSlots >= numWfs) { 41211308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 41311308Santhony.gutierrez@amd.com // find if there are enough free VGPR regions in the SIMD's VRF 41411308Santhony.gutierrez@amd.com // to accommodate the WFs of the new WG that would be mapped to 41511308Santhony.gutierrez@amd.com // this SIMD unit 41611308Santhony.gutierrez@amd.com vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j], 41711308Santhony.gutierrez@amd.com vregDemandPerWI); 41811308Santhony.gutierrez@amd.com 41911308Santhony.gutierrez@amd.com // stop searching if there is at least one SIMD 42011308Santhony.gutierrez@amd.com // whose VRF does not have enough free VGPR pools. 42111308Santhony.gutierrez@amd.com // This is because a WG is scheduled only if ALL 42211308Santhony.gutierrez@amd.com // of its WFs can be scheduled 42311308Santhony.gutierrez@amd.com if (!vregAvail) 42411308Santhony.gutierrez@amd.com break; 42511308Santhony.gutierrez@amd.com } 42611308Santhony.gutierrez@amd.com } 42711308Santhony.gutierrez@amd.com 42811308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Free WF slots = %d, VGPR Availability = %d\n", 42911308Santhony.gutierrez@amd.com freeWfSlots, vregAvail); 43011308Santhony.gutierrez@amd.com 43111308Santhony.gutierrez@amd.com if (!vregAvail) { 43211308Santhony.gutierrez@amd.com ++numTimesWgBlockedDueVgprAlloc; 43311308Santhony.gutierrez@amd.com } 43411308Santhony.gutierrez@amd.com 43511308Santhony.gutierrez@amd.com // Return true if enough WF slots to submit workgroup and if there are 43611308Santhony.gutierrez@amd.com // enough VGPRs to schedule all WFs to their SIMD units 43711308Santhony.gutierrez@amd.com if (!lds.canReserve(ndr->q.ldsSize)) { 43811308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation++; 43911308Santhony.gutierrez@amd.com } 44011308Santhony.gutierrez@amd.com 44111308Santhony.gutierrez@amd.com // Return true if (a) there are enough free WF slots to submit 44211308Santhony.gutierrez@amd.com // workgrounp and (b) if there are enough VGPRs to schedule all WFs to their 44311308Santhony.gutierrez@amd.com // SIMD units and (c) if there is enough space in LDS 44411308Santhony.gutierrez@amd.com return freeWfSlots >= numWfs && vregAvail && lds.canReserve(ndr->q.ldsSize); 44511308Santhony.gutierrez@amd.com} 44611308Santhony.gutierrez@amd.com 44711308Santhony.gutierrez@amd.comint 44811308Santhony.gutierrez@amd.comComputeUnit::AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots) 44911308Santhony.gutierrez@amd.com{ 45011308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id); 45111308Santhony.gutierrez@amd.com int ccnt = 0; 45211308Santhony.gutierrez@amd.com 45311308Santhony.gutierrez@amd.com for (int i_simd = 0; i_simd < numSIMDs; ++i_simd) { 45411308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf) { 45511308Santhony.gutierrez@amd.com Wavefront *w = wfList[i_simd][i_wf]; 45611308Santhony.gutierrez@amd.com 45711308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING) { 45811308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "Checking WF[%d][%d]\n", i_simd, i_wf); 45911308Santhony.gutierrez@amd.com 46011308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_id = %d, _barrier_id = %d\n", 46111639Salexandru.dutu@amd.com w->barrierId, _barrier_id); 46211308Santhony.gutierrez@amd.com 46311308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_cnt %d, bcnt = %d\n", 46411639Salexandru.dutu@amd.com w->barrierCnt, bcnt); 46511308Santhony.gutierrez@amd.com } 46611308Santhony.gutierrez@amd.com 46711308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING && 46811639Salexandru.dutu@amd.com w->barrierId == _barrier_id && w->barrierCnt == bcnt && 46911639Salexandru.dutu@amd.com !w->outstandingReqs) { 47011308Santhony.gutierrez@amd.com ++ccnt; 47111308Santhony.gutierrez@amd.com 47211308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "WF[%d][%d] at barrier, increment ccnt to " 47311308Santhony.gutierrez@amd.com "%d\n", i_simd, i_wf, ccnt); 47411308Santhony.gutierrez@amd.com } 47511308Santhony.gutierrez@amd.com } 47611308Santhony.gutierrez@amd.com } 47711308Santhony.gutierrez@amd.com 47811308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: returning allAtBarrier ccnt = %d, bslots = %d\n", 47911308Santhony.gutierrez@amd.com cu_id, ccnt, bslots); 48011308Santhony.gutierrez@amd.com 48111308Santhony.gutierrez@amd.com return ccnt == bslots; 48211308Santhony.gutierrez@amd.com} 48311308Santhony.gutierrez@amd.com 48411308Santhony.gutierrez@amd.com// Check if the current wavefront is blocked on additional resources. 48511308Santhony.gutierrez@amd.combool 48611308Santhony.gutierrez@amd.comComputeUnit::cedeSIMD(int simdId, int wfSlotId) 48711308Santhony.gutierrez@amd.com{ 48811308Santhony.gutierrez@amd.com bool cede = false; 48911308Santhony.gutierrez@amd.com 49011308Santhony.gutierrez@amd.com // If --xact-cas-mode option is enabled in run.py, then xact_cas_ld 49111308Santhony.gutierrez@amd.com // magic instructions will impact the scheduling of wavefronts 49211308Santhony.gutierrez@amd.com if (xact_cas_mode) { 49311308Santhony.gutierrez@amd.com /* 49411308Santhony.gutierrez@amd.com * When a wavefront calls xact_cas_ld, it adds itself to a per address 49511308Santhony.gutierrez@amd.com * queue. All per address queues are managed by the xactCasLoadMap. 49611308Santhony.gutierrez@amd.com * 49711308Santhony.gutierrez@amd.com * A wavefront is not blocked if: it is not in ANY per address queue or 49811308Santhony.gutierrez@amd.com * if it is at the head of a per address queue. 49911308Santhony.gutierrez@amd.com */ 50011308Santhony.gutierrez@amd.com for (auto itMap : xactCasLoadMap) { 50111308Santhony.gutierrez@amd.com std::list<waveIdentifier> curWaveIDQueue = itMap.second.waveIDQueue; 50211308Santhony.gutierrez@amd.com 50311308Santhony.gutierrez@amd.com if (!curWaveIDQueue.empty()) { 50411308Santhony.gutierrez@amd.com for (auto it : curWaveIDQueue) { 50511308Santhony.gutierrez@amd.com waveIdentifier cur_wave = it; 50611308Santhony.gutierrez@amd.com 50711308Santhony.gutierrez@amd.com if (cur_wave.simdId == simdId && 50811308Santhony.gutierrez@amd.com cur_wave.wfSlotId == wfSlotId) { 50911308Santhony.gutierrez@amd.com // 2 possibilities 51011308Santhony.gutierrez@amd.com // 1: this WF has a green light 51111308Santhony.gutierrez@amd.com // 2: another WF has a green light 51211308Santhony.gutierrez@amd.com waveIdentifier owner_wave = curWaveIDQueue.front(); 51311308Santhony.gutierrez@amd.com 51411308Santhony.gutierrez@amd.com if (owner_wave.simdId != cur_wave.simdId || 51511308Santhony.gutierrez@amd.com owner_wave.wfSlotId != cur_wave.wfSlotId) { 51611308Santhony.gutierrez@amd.com // possibility 2 51711308Santhony.gutierrez@amd.com cede = true; 51811308Santhony.gutierrez@amd.com break; 51911308Santhony.gutierrez@amd.com } else { 52011308Santhony.gutierrez@amd.com // possibility 1 52111308Santhony.gutierrez@amd.com break; 52211308Santhony.gutierrez@amd.com } 52311308Santhony.gutierrez@amd.com } 52411308Santhony.gutierrez@amd.com } 52511308Santhony.gutierrez@amd.com } 52611308Santhony.gutierrez@amd.com } 52711308Santhony.gutierrez@amd.com } 52811308Santhony.gutierrez@amd.com 52911308Santhony.gutierrez@amd.com return cede; 53011308Santhony.gutierrez@amd.com} 53111308Santhony.gutierrez@amd.com 53211308Santhony.gutierrez@amd.com// Execute one clock worth of work on the ComputeUnit. 53311308Santhony.gutierrez@amd.comvoid 53411308Santhony.gutierrez@amd.comComputeUnit::exec() 53511308Santhony.gutierrez@amd.com{ 53611308Santhony.gutierrez@amd.com updateEvents(); 53711308Santhony.gutierrez@amd.com // Execute pipeline stages in reverse order to simulate 53811308Santhony.gutierrez@amd.com // the pipeline latency 53911308Santhony.gutierrez@amd.com globalMemoryPipe.exec(); 54011308Santhony.gutierrez@amd.com localMemoryPipe.exec(); 54111308Santhony.gutierrez@amd.com execStage.exec(); 54211308Santhony.gutierrez@amd.com scheduleStage.exec(); 54311308Santhony.gutierrez@amd.com scoreboardCheckStage.exec(); 54411308Santhony.gutierrez@amd.com fetchStage.exec(); 54511308Santhony.gutierrez@amd.com 54611308Santhony.gutierrez@amd.com totalCycles++; 54711308Santhony.gutierrez@amd.com} 54811308Santhony.gutierrez@amd.com 54911308Santhony.gutierrez@amd.comvoid 55011308Santhony.gutierrez@amd.comComputeUnit::init() 55111308Santhony.gutierrez@amd.com{ 55211308Santhony.gutierrez@amd.com // Initialize CU Bus models 55311345Sjohn.kalamatianos@amd.com glbMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 55411345Sjohn.kalamatianos@amd.com locMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 55511308Santhony.gutierrez@amd.com nextGlbMemBus = 0; 55611308Santhony.gutierrez@amd.com nextLocMemBus = 0; 55711308Santhony.gutierrez@amd.com fatal_if(numGlbMemUnits > 1, 55811308Santhony.gutierrez@amd.com "No support for multiple Global Memory Pipelines exists!!!"); 55911308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus.resize(numGlbMemUnits); 56011308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 56111308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus[j] = WaitClass(); 56211345Sjohn.kalamatianos@amd.com vrfToGlobalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 56311308Santhony.gutierrez@amd.com } 56411308Santhony.gutierrez@amd.com 56511308Santhony.gutierrez@amd.com fatal_if(numLocMemUnits > 1, 56611308Santhony.gutierrez@amd.com "No support for multiple Local Memory Pipelines exists!!!"); 56711308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus.resize(numLocMemUnits); 56811308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 56911308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus[j] = WaitClass(); 57011345Sjohn.kalamatianos@amd.com vrfToLocalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 57111308Santhony.gutierrez@amd.com } 57211308Santhony.gutierrez@amd.com vectorRegsReserved.resize(numSIMDs, 0); 57311308Santhony.gutierrez@amd.com aluPipe.resize(numSIMDs); 57411308Santhony.gutierrez@amd.com wfWait.resize(numSIMDs + numLocMemUnits + numGlbMemUnits); 57511308Santhony.gutierrez@amd.com 57611308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs + numLocMemUnits + numGlbMemUnits; ++i) { 57711308Santhony.gutierrez@amd.com wfWait[i] = WaitClass(); 57811345Sjohn.kalamatianos@amd.com wfWait[i].init(&shader->tick_cnt, shader->ticks(1)); 57911308Santhony.gutierrez@amd.com } 58011308Santhony.gutierrez@amd.com 58111308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 58211308Santhony.gutierrez@amd.com aluPipe[i] = WaitClass(); 58311345Sjohn.kalamatianos@amd.com aluPipe[i].init(&shader->tick_cnt, shader->ticks(1)); 58411308Santhony.gutierrez@amd.com } 58511308Santhony.gutierrez@amd.com 58611308Santhony.gutierrez@amd.com // Setup space for call args 58711308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 58811308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 58911534Sjohn.kalamatianos@amd.com wfList[j][i]->initCallArgMem(shader->funcargs_size, wavefrontSize); 59011308Santhony.gutierrez@amd.com } 59111308Santhony.gutierrez@amd.com } 59211308Santhony.gutierrez@amd.com 59311308Santhony.gutierrez@amd.com // Initializing pipeline resources 59411308Santhony.gutierrez@amd.com readyList.resize(numSIMDs + numGlbMemUnits + numLocMemUnits); 59511308Santhony.gutierrez@amd.com waveStatusList.resize(numSIMDs); 59611308Santhony.gutierrez@amd.com 59711308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 59811308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 59911308Santhony.gutierrez@amd.com waveStatusList[j].push_back( 60011308Santhony.gutierrez@amd.com std::make_pair(wfList[j][i], BLOCKED)); 60111308Santhony.gutierrez@amd.com } 60211308Santhony.gutierrez@amd.com } 60311308Santhony.gutierrez@amd.com 60411308Santhony.gutierrez@amd.com for (int j = 0; j < (numSIMDs + numGlbMemUnits + numLocMemUnits); ++j) { 60511308Santhony.gutierrez@amd.com dispatchList.push_back(std::make_pair((Wavefront*)nullptr, EMPTY)); 60611308Santhony.gutierrez@amd.com } 60711308Santhony.gutierrez@amd.com 60811308Santhony.gutierrez@amd.com fetchStage.init(this); 60911308Santhony.gutierrez@amd.com scoreboardCheckStage.init(this); 61011308Santhony.gutierrez@amd.com scheduleStage.init(this); 61111308Santhony.gutierrez@amd.com execStage.init(this); 61211308Santhony.gutierrez@amd.com globalMemoryPipe.init(this); 61311308Santhony.gutierrez@amd.com localMemoryPipe.init(this); 61411308Santhony.gutierrez@amd.com // initialize state for statistics calculation 61511308Santhony.gutierrez@amd.com vectorAluInstAvail.resize(numSIMDs, false); 61611308Santhony.gutierrez@amd.com shrMemInstAvail = 0; 61711308Santhony.gutierrez@amd.com glbMemInstAvail = 0; 61811308Santhony.gutierrez@amd.com} 61911308Santhony.gutierrez@amd.com 62011308Santhony.gutierrez@amd.combool 62111308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvTimingResp(PacketPtr pkt) 62211308Santhony.gutierrez@amd.com{ 62311308Santhony.gutierrez@amd.com // Ruby has completed the memory op. Schedule the mem_resp_event at the 62411308Santhony.gutierrez@amd.com // appropriate cycle to process the timing memory response 62511308Santhony.gutierrez@amd.com // This delay represents the pipeline delay 62611308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 62711308Santhony.gutierrez@amd.com int index = sender_state->port_index; 62811308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 62911308Santhony.gutierrez@amd.com 63011308Santhony.gutierrez@amd.com // Is the packet returned a Kernel End or Barrier 63111308Santhony.gutierrez@amd.com if (pkt->req->isKernel() && pkt->req->isRelease()) { 63211308Santhony.gutierrez@amd.com Wavefront *w = 63311308Santhony.gutierrez@amd.com computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId]; 63411308Santhony.gutierrez@amd.com 63511308Santhony.gutierrez@amd.com // Check if we are waiting on Kernel End Release 63611308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RETURNING) { 63711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: WF[%d][%d][wv=%d]: WG id completed %d\n", 63811308Santhony.gutierrez@amd.com computeUnit->cu_id, w->simdId, w->wfSlotId, 63911639Salexandru.dutu@amd.com w->wfDynId, w->kernId); 64011308Santhony.gutierrez@amd.com 64111308Santhony.gutierrez@amd.com computeUnit->shader->dispatcher->notifyWgCompl(w); 64211308Santhony.gutierrez@amd.com w->status = Wavefront::S_STOPPED; 64311308Santhony.gutierrez@amd.com } else { 64411639Salexandru.dutu@amd.com w->outstandingReqs--; 64511308Santhony.gutierrez@amd.com } 64611308Santhony.gutierrez@amd.com 64711308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: WF[%d][%d]: barrier_cnt = %d\n", 64811308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 64911639Salexandru.dutu@amd.com gpuDynInst->wfSlotId, w->barrierCnt); 65011308Santhony.gutierrez@amd.com 65111308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 65211692Santhony.gutierrez@amd.com assert(!gpuDynInst->isNoScope()); 65311308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 65411308Santhony.gutierrez@amd.com gpuDynInst); 65511308Santhony.gutierrez@amd.com } 65611308Santhony.gutierrez@amd.com 65711308Santhony.gutierrez@amd.com delete pkt->senderState; 65811308Santhony.gutierrez@amd.com delete pkt; 65911308Santhony.gutierrez@amd.com return true; 66011308Santhony.gutierrez@amd.com } else if (pkt->req->isKernel() && pkt->req->isAcquire()) { 66111308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 66211692Santhony.gutierrez@amd.com assert(!gpuDynInst->isNoScope()); 66311308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 66411308Santhony.gutierrez@amd.com gpuDynInst); 66511308Santhony.gutierrez@amd.com } 66611308Santhony.gutierrez@amd.com 66711308Santhony.gutierrez@amd.com delete pkt->senderState; 66811308Santhony.gutierrez@amd.com delete pkt; 66911308Santhony.gutierrez@amd.com return true; 67011308Santhony.gutierrez@amd.com } 67111308Santhony.gutierrez@amd.com 67212126Sspwilson2@wisc.edu EventFunctionWrapper *mem_resp_event = 67312126Sspwilson2@wisc.edu computeUnit->memPort[index]->createMemRespEvent(pkt); 67411308Santhony.gutierrez@amd.com 67511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n", 67611308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 67711308Santhony.gutierrez@amd.com index, pkt->req->getPaddr()); 67811308Santhony.gutierrez@amd.com 67911308Santhony.gutierrez@amd.com computeUnit->schedule(mem_resp_event, 68011308Santhony.gutierrez@amd.com curTick() + computeUnit->resp_tick_latency); 68111308Santhony.gutierrez@amd.com return true; 68211308Santhony.gutierrez@amd.com} 68311308Santhony.gutierrez@amd.com 68411308Santhony.gutierrez@amd.comvoid 68511308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvReqRetry() 68611308Santhony.gutierrez@amd.com{ 68711308Santhony.gutierrez@amd.com int len = retries.size(); 68811308Santhony.gutierrez@amd.com 68911308Santhony.gutierrez@amd.com assert(len > 0); 69011308Santhony.gutierrez@amd.com 69111308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 69211308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 69311308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second; 69411308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n", 69511308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 69611308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 69711308Santhony.gutierrez@amd.com 69811308Santhony.gutierrez@amd.com /** Currently Ruby can return false due to conflicts for the particular 69911308Santhony.gutierrez@amd.com * cache block or address. Thus other requests should be allowed to 70011308Santhony.gutierrez@amd.com * pass and the data port should expect multiple retries. */ 70111308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 70211308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "failed again!\n"); 70311308Santhony.gutierrez@amd.com break; 70411308Santhony.gutierrez@amd.com } else { 70511308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "successful!\n"); 70611308Santhony.gutierrez@amd.com retries.pop_front(); 70711308Santhony.gutierrez@amd.com } 70811308Santhony.gutierrez@amd.com } 70911308Santhony.gutierrez@amd.com} 71011308Santhony.gutierrez@amd.com 71111308Santhony.gutierrez@amd.combool 71211308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt) 71311308Santhony.gutierrez@amd.com{ 71411308Santhony.gutierrez@amd.com computeUnit->fetchStage.processFetchReturn(pkt); 71511308Santhony.gutierrez@amd.com 71611308Santhony.gutierrez@amd.com return true; 71711308Santhony.gutierrez@amd.com} 71811308Santhony.gutierrez@amd.com 71911308Santhony.gutierrez@amd.comvoid 72011308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvReqRetry() 72111308Santhony.gutierrez@amd.com{ 72211308Santhony.gutierrez@amd.com int len = retries.size(); 72311308Santhony.gutierrez@amd.com 72411308Santhony.gutierrez@amd.com assert(len > 0); 72511308Santhony.gutierrez@amd.com 72611308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 72711308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 72811308Santhony.gutierrez@amd.com Wavefront *wavefront M5_VAR_USED = retries.front().second; 72911308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n", 73011308Santhony.gutierrez@amd.com computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, 73111308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 73211308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 73311308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "failed again!\n"); 73411308Santhony.gutierrez@amd.com break; 73511308Santhony.gutierrez@amd.com } else { 73611308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "successful!\n"); 73711308Santhony.gutierrez@amd.com retries.pop_front(); 73811308Santhony.gutierrez@amd.com } 73911308Santhony.gutierrez@amd.com } 74011308Santhony.gutierrez@amd.com} 74111308Santhony.gutierrez@amd.com 74211308Santhony.gutierrez@amd.comvoid 74311308Santhony.gutierrez@amd.comComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 74411308Santhony.gutierrez@amd.com{ 74511308Santhony.gutierrez@amd.com // There must be a way around this check to do the globalMemStart... 74611308Santhony.gutierrez@amd.com Addr tmp_vaddr = pkt->req->getVaddr(); 74711308Santhony.gutierrez@amd.com 74811308Santhony.gutierrez@amd.com updatePageDivergenceDist(tmp_vaddr); 74911308Santhony.gutierrez@amd.com 75011308Santhony.gutierrez@amd.com pkt->req->setVirt(pkt->req->getAsid(), tmp_vaddr, pkt->req->getSize(), 75111308Santhony.gutierrez@amd.com pkt->req->getFlags(), pkt->req->masterId(), 75211308Santhony.gutierrez@amd.com pkt->req->getPC()); 75311308Santhony.gutierrez@amd.com 75411308Santhony.gutierrez@amd.com // figure out the type of the request to set read/write 75511308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode; 75611308Santhony.gutierrez@amd.com assert(pkt->isRead() || pkt->isWrite()); 75711308Santhony.gutierrez@amd.com 75811308Santhony.gutierrez@amd.com // Check write before read for atomic operations 75911308Santhony.gutierrez@amd.com // since atomic operations should use BaseTLB::Write 76011308Santhony.gutierrez@amd.com if (pkt->isWrite()){ 76111308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Write; 76211308Santhony.gutierrez@amd.com } else if (pkt->isRead()) { 76311308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Read; 76411308Santhony.gutierrez@amd.com } else { 76511308Santhony.gutierrez@amd.com fatal("pkt is not a read nor a write\n"); 76611308Santhony.gutierrez@amd.com } 76711308Santhony.gutierrez@amd.com 76811308Santhony.gutierrez@amd.com tlbCycles -= curTick(); 76911308Santhony.gutierrez@amd.com ++tlbRequests; 77011308Santhony.gutierrez@amd.com 77111308Santhony.gutierrez@amd.com int tlbPort_index = perLaneTLB ? index : 0; 77211308Santhony.gutierrez@amd.com 77311308Santhony.gutierrez@amd.com if (shader->timingSim) { 77411308Santhony.gutierrez@amd.com if (debugSegFault) { 77511308Santhony.gutierrez@amd.com Process *p = shader->gpuTc->getProcessPtr(); 77611308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 77711308Santhony.gutierrez@amd.com unsigned size = pkt->getSize(); 77811308Santhony.gutierrez@amd.com 77911308Santhony.gutierrez@amd.com if ((vaddr + size - 1) % 64 < vaddr % 64) { 78011308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Access to addr %#x is unaligned!\n", 78111308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr); 78211308Santhony.gutierrez@amd.com } 78311308Santhony.gutierrez@amd.com 78411308Santhony.gutierrez@amd.com Addr paddr; 78511308Santhony.gutierrez@amd.com 78611308Santhony.gutierrez@amd.com if (!p->pTable->translate(vaddr, paddr)) { 78711308Santhony.gutierrez@amd.com if (!p->fixupStackFault(vaddr)) { 78811308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Fault on addr %#x!\n", 78911308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 79011308Santhony.gutierrez@amd.com vaddr); 79111308Santhony.gutierrez@amd.com } 79211308Santhony.gutierrez@amd.com } 79311308Santhony.gutierrez@amd.com } 79411308Santhony.gutierrez@amd.com 79511308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 79611308Santhony.gutierrez@amd.com pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index); 79711308Santhony.gutierrez@amd.com 79811308Santhony.gutierrez@amd.com // This is the senderState needed by the TLB hierarchy to function 79911308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 80011308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false, 80111308Santhony.gutierrez@amd.com pkt->senderState); 80211308Santhony.gutierrez@amd.com 80311308Santhony.gutierrez@amd.com pkt->senderState = translation_state; 80411308Santhony.gutierrez@amd.com 80511308Santhony.gutierrez@amd.com if (functionalTLB) { 80611308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 80711308Santhony.gutierrez@amd.com 80811308Santhony.gutierrez@amd.com // update the hitLevel distribution 80911308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 81011308Santhony.gutierrez@amd.com assert(hit_level != -1); 81111308Santhony.gutierrez@amd.com hitsPerTLBLevel[hit_level]++; 81211308Santhony.gutierrez@amd.com 81311308Santhony.gutierrez@amd.com // New SenderState for the memory access 81411308Santhony.gutierrez@amd.com X86ISA::GpuTLB::TranslationState *sender_state = 81511308Santhony.gutierrez@amd.com safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState); 81611308Santhony.gutierrez@amd.com 81711308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 81811308Santhony.gutierrez@amd.com delete sender_state->saved; 81911308Santhony.gutierrez@amd.com delete sender_state; 82011308Santhony.gutierrez@amd.com 82111308Santhony.gutierrez@amd.com assert(pkt->req->hasPaddr()); 82211308Santhony.gutierrez@amd.com assert(pkt->req->hasSize()); 82311308Santhony.gutierrez@amd.com 82411308Santhony.gutierrez@amd.com uint8_t *tmpData = pkt->getPtr<uint8_t>(); 82511308Santhony.gutierrez@amd.com 82611308Santhony.gutierrez@amd.com // this is necessary because the GPU TLB receives packets instead 82711308Santhony.gutierrez@amd.com // of requests. when the translation is complete, all relevent 82811308Santhony.gutierrez@amd.com // fields in the request will be populated, but not in the packet. 82911308Santhony.gutierrez@amd.com // here we create the new packet so we can set the size, addr, 83011308Santhony.gutierrez@amd.com // and proper flags. 83111308Santhony.gutierrez@amd.com PacketPtr oldPkt = pkt; 83211308Santhony.gutierrez@amd.com pkt = new Packet(oldPkt->req, oldPkt->cmd); 83311308Santhony.gutierrez@amd.com delete oldPkt; 83411308Santhony.gutierrez@amd.com pkt->dataStatic(tmpData); 83511308Santhony.gutierrez@amd.com 83611308Santhony.gutierrez@amd.com 83711308Santhony.gutierrez@amd.com // New SenderState for the memory access 83811308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, 83911308Santhony.gutierrez@amd.com index, nullptr); 84011308Santhony.gutierrez@amd.com 84111308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index); 84211308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[index] = hit_level; 84311308Santhony.gutierrez@amd.com 84411308Santhony.gutierrez@amd.com 84511308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the 84611308Santhony.gutierrez@amd.com // appropriate cycle to send the timing memory request to ruby 84712126Sspwilson2@wisc.edu EventFunctionWrapper *mem_req_event = 84812126Sspwilson2@wisc.edu memPort[index]->createMemReqEvent(pkt); 84911308Santhony.gutierrez@amd.com 85011308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data " 85111308Santhony.gutierrez@amd.com "scheduled\n", cu_id, gpuDynInst->simdId, 85211308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, index, pkt->req->getPaddr()); 85311308Santhony.gutierrez@amd.com 85411308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 85511308Santhony.gutierrez@amd.com } else if (tlbPort[tlbPort_index]->isStalled()) { 85611308Santhony.gutierrez@amd.com assert(tlbPort[tlbPort_index]->retries.size() > 0); 85711308Santhony.gutierrez@amd.com 85811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 85911308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 86011308Santhony.gutierrez@amd.com tmp_vaddr); 86111308Santhony.gutierrez@amd.com 86211308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 86311308Santhony.gutierrez@amd.com } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) { 86411308Santhony.gutierrez@amd.com // Stall the data port; 86511308Santhony.gutierrez@amd.com // No more packet will be issued till 86611308Santhony.gutierrez@amd.com // ruby indicates resources are freed by 86711308Santhony.gutierrez@amd.com // a recvReqRetry() call back on this port. 86811308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->stallPort(); 86911308Santhony.gutierrez@amd.com 87011308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 87111308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 87211308Santhony.gutierrez@amd.com tmp_vaddr); 87311308Santhony.gutierrez@amd.com 87411308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 87511308Santhony.gutierrez@amd.com } else { 87611308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, 87711308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: Translation for addr %#x sent!\n", 87811308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, tmp_vaddr); 87911308Santhony.gutierrez@amd.com } 88011308Santhony.gutierrez@amd.com } else { 88111308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::MemFenceReq) { 88211308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 88311308Santhony.gutierrez@amd.com } else { 88411308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ll << index)); 88511308Santhony.gutierrez@amd.com } 88611308Santhony.gutierrez@amd.com 88711308Santhony.gutierrez@amd.com // New SenderState for the memory access 88811308Santhony.gutierrez@amd.com delete pkt->senderState; 88911308Santhony.gutierrez@amd.com 89011308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 89111308Santhony.gutierrez@amd.com pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode, 89211308Santhony.gutierrez@amd.com shader->gpuTc); 89311308Santhony.gutierrez@amd.com 89411308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 89511308Santhony.gutierrez@amd.com 89611308Santhony.gutierrez@amd.com // the addr of the packet is not modified, so we need to create a new 89711308Santhony.gutierrez@amd.com // packet, or otherwise the memory access will have the old virtual 89811308Santhony.gutierrez@amd.com // address sent in the translation packet, instead of the physical 89911308Santhony.gutierrez@amd.com // address returned by the translation. 90011308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd); 90111308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 90211308Santhony.gutierrez@amd.com 90311308Santhony.gutierrez@amd.com // Translation is done. It is safe to send the packet to memory. 90411308Santhony.gutierrez@amd.com memPort[0]->sendFunctional(new_pkt); 90511308Santhony.gutierrez@amd.com 90611308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: index %d: addr %#x\n", cu_id, 90711308Santhony.gutierrez@amd.com gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 90811308Santhony.gutierrez@amd.com new_pkt->req->getPaddr()); 90911308Santhony.gutierrez@amd.com 91011308Santhony.gutierrez@amd.com // safe_cast the senderState 91111308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *sender_state = 91211308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 91311308Santhony.gutierrez@amd.com 91411308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 91511308Santhony.gutierrez@amd.com delete new_pkt; 91611308Santhony.gutierrez@amd.com delete pkt->senderState; 91711308Santhony.gutierrez@amd.com delete pkt; 91811308Santhony.gutierrez@amd.com } 91911308Santhony.gutierrez@amd.com} 92011308Santhony.gutierrez@amd.com 92111308Santhony.gutierrez@amd.comvoid 92211308Santhony.gutierrez@amd.comComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 92311308Santhony.gutierrez@amd.com{ 92412126Sspwilson2@wisc.edu EventFunctionWrapper *mem_req_event = 92512126Sspwilson2@wisc.edu memPort[index]->createMemReqEvent(pkt); 92611308Santhony.gutierrez@amd.com 92711308Santhony.gutierrez@amd.com 92811308Santhony.gutierrez@amd.com // New SenderState for the memory access 92911308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index, 93011308Santhony.gutierrez@amd.com nullptr); 93111308Santhony.gutierrez@amd.com 93211308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x sync scheduled\n", 93311308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 93411308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 93511308Santhony.gutierrez@amd.com 93611308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 93711308Santhony.gutierrez@amd.com} 93811308Santhony.gutierrez@amd.com 93911308Santhony.gutierrez@amd.comvoid 94011308Santhony.gutierrez@amd.comComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch, 94112749Sgiacomo.travaglini@arm.com RequestPtr req) 94211308Santhony.gutierrez@amd.com{ 94311692Santhony.gutierrez@amd.com assert(gpuDynInst->isGlobalSeg()); 94411692Santhony.gutierrez@amd.com 94511308Santhony.gutierrez@amd.com if (!req) { 94612749Sgiacomo.travaglini@arm.com req = std::make_shared<Request>( 94712749Sgiacomo.travaglini@arm.com 0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId); 94811308Santhony.gutierrez@amd.com } 94911308Santhony.gutierrez@amd.com req->setPaddr(0); 95011308Santhony.gutierrez@amd.com if (kernelLaunch) { 95111308Santhony.gutierrez@amd.com req->setFlags(Request::KERNEL); 95211308Santhony.gutierrez@amd.com } 95311308Santhony.gutierrez@amd.com 95411308Santhony.gutierrez@amd.com // for non-kernel MemFence operations, memorder flags are set depending 95511308Santhony.gutierrez@amd.com // on which type of request is currently being sent, so this 95611308Santhony.gutierrez@amd.com // should be set by the caller (e.g. if an inst has acq-rel 95711308Santhony.gutierrez@amd.com // semantics, it will send one acquire req an one release req) 95811308Santhony.gutierrez@amd.com gpuDynInst->setRequestFlags(req, kernelLaunch); 95911308Santhony.gutierrez@amd.com 96011308Santhony.gutierrez@amd.com // a mem fence must correspond to an acquire/release request 96111308Santhony.gutierrez@amd.com assert(req->isAcquire() || req->isRelease()); 96211308Santhony.gutierrez@amd.com 96311308Santhony.gutierrez@amd.com // create packet 96411308Santhony.gutierrez@amd.com PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq); 96511308Santhony.gutierrez@amd.com 96611308Santhony.gutierrez@amd.com // set packet's sender state 96711308Santhony.gutierrez@amd.com pkt->senderState = 96811308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, 0, nullptr); 96911308Santhony.gutierrez@amd.com 97011308Santhony.gutierrez@amd.com // send the packet 97111308Santhony.gutierrez@amd.com sendSyncRequest(gpuDynInst, 0, pkt); 97211308Santhony.gutierrez@amd.com} 97311308Santhony.gutierrez@amd.com 97411308Santhony.gutierrez@amd.comvoid 97512126Sspwilson2@wisc.eduComputeUnit::DataPort::processMemRespEvent(PacketPtr pkt) 97611308Santhony.gutierrez@amd.com{ 97711308Santhony.gutierrez@amd.com DataPort::SenderState *sender_state = 97811308Santhony.gutierrez@amd.com safe_cast<DataPort::SenderState*>(pkt->senderState); 97911308Santhony.gutierrez@amd.com 98011308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 98112126Sspwilson2@wisc.edu ComputeUnit *compute_unit = computeUnit; 98211308Santhony.gutierrez@amd.com 98311308Santhony.gutierrez@amd.com assert(gpuDynInst); 98411308Santhony.gutierrez@amd.com 98511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n", 98611308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 98712126Sspwilson2@wisc.edu pkt->req->getPaddr(), index); 98811308Santhony.gutierrez@amd.com 98911308Santhony.gutierrez@amd.com Addr paddr = pkt->req->getPaddr(); 99011308Santhony.gutierrez@amd.com 99111308Santhony.gutierrez@amd.com if (pkt->cmd != MemCmd::MemFenceResp) { 99211308Santhony.gutierrez@amd.com int index = gpuDynInst->memStatusVector[paddr].back(); 99311308Santhony.gutierrez@amd.com 99411308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "Response for addr %#x, index %d\n", 99511308Santhony.gutierrez@amd.com pkt->req->getPaddr(), index); 99611308Santhony.gutierrez@amd.com 99711308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[paddr].pop_back(); 99811308Santhony.gutierrez@amd.com gpuDynInst->pAddr = pkt->req->getPaddr(); 99911308Santhony.gutierrez@amd.com 100011308Santhony.gutierrez@amd.com if (pkt->isRead() || pkt->isWrite()) { 100111308Santhony.gutierrez@amd.com 100211308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg <= MAX_REGS_FOR_NON_VEC_MEM_INST) { 100311308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 100411308Santhony.gutierrez@amd.com } else { 100511308Santhony.gutierrez@amd.com assert(gpuDynInst->statusVector[index] > 0); 100611308Santhony.gutierrez@amd.com gpuDynInst->statusVector[index]--; 100711308Santhony.gutierrez@amd.com 100811308Santhony.gutierrez@amd.com if (!gpuDynInst->statusVector[index]) 100911308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 101011308Santhony.gutierrez@amd.com } 101111308Santhony.gutierrez@amd.com 101211308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "bitvector is now %#x\n", 101311308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector); 101411308Santhony.gutierrez@amd.com 101511308Santhony.gutierrez@amd.com if (gpuDynInst->statusBitVector == VectorMask(0)) { 101611308Santhony.gutierrez@amd.com auto iter = gpuDynInst->memStatusVector.begin(); 101711308Santhony.gutierrez@amd.com auto end = gpuDynInst->memStatusVector.end(); 101811308Santhony.gutierrez@amd.com 101911308Santhony.gutierrez@amd.com while (iter != end) { 102011308Santhony.gutierrez@amd.com assert(iter->second.empty()); 102111308Santhony.gutierrez@amd.com ++iter; 102211308Santhony.gutierrez@amd.com } 102311308Santhony.gutierrez@amd.com 102411308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector.clear(); 102511308Santhony.gutierrez@amd.com 102611308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST) 102711308Santhony.gutierrez@amd.com gpuDynInst->statusVector.clear(); 102811308Santhony.gutierrez@amd.com 102911700Santhony.gutierrez@amd.com compute_unit->globalMemoryPipe.handleResponse(gpuDynInst); 103011308Santhony.gutierrez@amd.com 103111308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: packet totally complete\n", 103211308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 103311308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 103411308Santhony.gutierrez@amd.com 103511308Santhony.gutierrez@amd.com // after clearing the status vectors, 103611308Santhony.gutierrez@amd.com // see if there is a continuation to perform 103711308Santhony.gutierrez@amd.com // the continuation may generate more work for 103811308Santhony.gutierrez@amd.com // this memory request 103911308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 104011692Santhony.gutierrez@amd.com assert(!gpuDynInst->isNoScope()); 104112126Sspwilson2@wisc.edu gpuDynInst->execContinuation( 104212126Sspwilson2@wisc.edu gpuDynInst->staticInstruction(), 104312126Sspwilson2@wisc.edu gpuDynInst); 104411308Santhony.gutierrez@amd.com } 104511308Santhony.gutierrez@amd.com } 104611308Santhony.gutierrez@amd.com } 104711308Santhony.gutierrez@amd.com } else { 104811308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 104911308Santhony.gutierrez@amd.com 105011308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 105111692Santhony.gutierrez@amd.com assert(!gpuDynInst->isNoScope()); 105211308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 105311308Santhony.gutierrez@amd.com gpuDynInst); 105411308Santhony.gutierrez@amd.com } 105511308Santhony.gutierrez@amd.com } 105611308Santhony.gutierrez@amd.com 105711308Santhony.gutierrez@amd.com delete pkt->senderState; 105811308Santhony.gutierrez@amd.com delete pkt; 105911308Santhony.gutierrez@amd.com} 106011308Santhony.gutierrez@amd.com 106111308Santhony.gutierrez@amd.comComputeUnit* 106211308Santhony.gutierrez@amd.comComputeUnitParams::create() 106311308Santhony.gutierrez@amd.com{ 106411308Santhony.gutierrez@amd.com return new ComputeUnit(this); 106511308Santhony.gutierrez@amd.com} 106611308Santhony.gutierrez@amd.com 106711308Santhony.gutierrez@amd.combool 106811308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) 106911308Santhony.gutierrez@amd.com{ 107011308Santhony.gutierrez@amd.com Addr line = pkt->req->getPaddr(); 107111308Santhony.gutierrez@amd.com 107211308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLBPort received %#x->%#x\n", computeUnit->cu_id, 107311308Santhony.gutierrez@amd.com pkt->req->getVaddr(), line); 107411308Santhony.gutierrez@amd.com 107511308Santhony.gutierrez@amd.com assert(pkt->senderState); 107611308Santhony.gutierrez@amd.com computeUnit->tlbCycles += curTick(); 107711308Santhony.gutierrez@amd.com 107811308Santhony.gutierrez@amd.com // pop off the TLB translation state 107911308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 108011308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 108111308Santhony.gutierrez@amd.com 108211308Santhony.gutierrez@amd.com // no PageFaults are permitted for data accesses 108312717Sbrandon.potter@amd.com if (!translation_state->tlbEntry) { 108411308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 108511308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(translation_state->saved); 108611308Santhony.gutierrez@amd.com 108711308Santhony.gutierrez@amd.com Wavefront *w M5_VAR_USED = 108811308Santhony.gutierrez@amd.com computeUnit->wfList[sender_state->_gpuDynInst->simdId] 108911308Santhony.gutierrez@amd.com [sender_state->_gpuDynInst->wfSlotId]; 109011308Santhony.gutierrez@amd.com 109111308Santhony.gutierrez@amd.com DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId, 109211308Santhony.gutierrez@amd.com pkt->req->getVaddr()); 109311308Santhony.gutierrez@amd.com } 109411308Santhony.gutierrez@amd.com 109511308Santhony.gutierrez@amd.com // update the hitLevel distribution 109611308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 109711308Santhony.gutierrez@amd.com computeUnit->hitsPerTLBLevel[hit_level]++; 109811308Santhony.gutierrez@amd.com 109911308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 110011308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 110111308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 110211308Santhony.gutierrez@amd.com 110311308Santhony.gutierrez@amd.com // for prefetch pkt 110411308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode = translation_state->tlbMode; 110511308Santhony.gutierrez@amd.com 110611308Santhony.gutierrez@amd.com delete translation_state; 110711308Santhony.gutierrez@amd.com 110811308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 110911308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 111011308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(pkt->senderState); 111111308Santhony.gutierrez@amd.com 111211308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 111311308Santhony.gutierrez@amd.com int mp_index = sender_state->portIndex; 111411308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 111511308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[line].push_back(mp_index); 111611308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[mp_index] = hit_level; 111711308Santhony.gutierrez@amd.com 111811308Santhony.gutierrez@amd.com MemCmd requestCmd; 111911308Santhony.gutierrez@amd.com 112011308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::ReadResp) { 112111308Santhony.gutierrez@amd.com requestCmd = MemCmd::ReadReq; 112211308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::WriteResp) { 112311308Santhony.gutierrez@amd.com requestCmd = MemCmd::WriteReq; 112411308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::SwapResp) { 112511308Santhony.gutierrez@amd.com requestCmd = MemCmd::SwapReq; 112611308Santhony.gutierrez@amd.com } else { 112711308Santhony.gutierrez@amd.com panic("unsupported response to request conversion %s\n", 112811308Santhony.gutierrez@amd.com pkt->cmd.toString()); 112911308Santhony.gutierrez@amd.com } 113011308Santhony.gutierrez@amd.com 113111308Santhony.gutierrez@amd.com if (computeUnit->prefetchDepth) { 113211308Santhony.gutierrez@amd.com int simdId = gpuDynInst->simdId; 113311308Santhony.gutierrez@amd.com int wfSlotId = gpuDynInst->wfSlotId; 113411308Santhony.gutierrez@amd.com Addr last = 0; 113511308Santhony.gutierrez@amd.com 113611308Santhony.gutierrez@amd.com switch(computeUnit->prefetchType) { 113711534Sjohn.kalamatianos@amd.com case Enums::PF_CU: 113811308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrCU[mp_index]; 113911308Santhony.gutierrez@amd.com break; 114011534Sjohn.kalamatianos@amd.com case Enums::PF_PHASE: 114111534Sjohn.kalamatianos@amd.com last = computeUnit->lastVaddrSimd[simdId][mp_index]; 114211308Santhony.gutierrez@amd.com break; 114311534Sjohn.kalamatianos@amd.com case Enums::PF_WF: 114411308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index]; 114511534Sjohn.kalamatianos@amd.com default: 114611308Santhony.gutierrez@amd.com break; 114711308Santhony.gutierrez@amd.com } 114811308Santhony.gutierrez@amd.com 114911308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n", 115011308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index, last); 115111308Santhony.gutierrez@amd.com 115211308Santhony.gutierrez@amd.com int stride = last ? (roundDown(vaddr, TheISA::PageBytes) - 115311308Santhony.gutierrez@amd.com roundDown(last, TheISA::PageBytes)) >> TheISA::PageShift 115411308Santhony.gutierrez@amd.com : 0; 115511308Santhony.gutierrez@amd.com 115611308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Stride is %d\n", stride); 115711308Santhony.gutierrez@amd.com 115811308Santhony.gutierrez@amd.com computeUnit->lastVaddrCU[mp_index] = vaddr; 115911534Sjohn.kalamatianos@amd.com computeUnit->lastVaddrSimd[simdId][mp_index] = vaddr; 116011308Santhony.gutierrez@amd.com computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr; 116111308Santhony.gutierrez@amd.com 116211308Santhony.gutierrez@amd.com stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ? 116311308Santhony.gutierrez@amd.com computeUnit->prefetchStride: stride; 116411308Santhony.gutierrez@amd.com 116511308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr, 116611308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index); 116711308Santhony.gutierrez@amd.com 116811308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Prefetching from %#x:", vaddr); 116911308Santhony.gutierrez@amd.com 117011308Santhony.gutierrez@amd.com // Prefetch Next few pages atomically 117111308Santhony.gutierrez@amd.com for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) { 117211308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride, 117311308Santhony.gutierrez@amd.com vaddr+stride*pf*TheISA::PageBytes); 117411308Santhony.gutierrez@amd.com 117511308Santhony.gutierrez@amd.com if (!stride) 117611308Santhony.gutierrez@amd.com break; 117711308Santhony.gutierrez@amd.com 117812749Sgiacomo.travaglini@arm.com RequestPtr prefetch_req = std::make_shared<Request>( 117912749Sgiacomo.travaglini@arm.com 0, vaddr + stride * pf * TheISA::PageBytes, 118012749Sgiacomo.travaglini@arm.com sizeof(uint8_t), 0, 118112749Sgiacomo.travaglini@arm.com computeUnit->masterId(), 118212749Sgiacomo.travaglini@arm.com 0, 0, nullptr); 118311308Santhony.gutierrez@amd.com 118411308Santhony.gutierrez@amd.com PacketPtr prefetch_pkt = new Packet(prefetch_req, requestCmd); 118511308Santhony.gutierrez@amd.com uint8_t foo = 0; 118611308Santhony.gutierrez@amd.com prefetch_pkt->dataStatic(&foo); 118711308Santhony.gutierrez@amd.com 118811308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 118911308Santhony.gutierrez@amd.com prefetch_pkt->senderState = 119011308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, 119111308Santhony.gutierrez@amd.com computeUnit->shader->gpuTc, 119211308Santhony.gutierrez@amd.com true); 119311308Santhony.gutierrez@amd.com 119411308Santhony.gutierrez@amd.com // Currently prefetches are zero-latency, hence the sendFunctional 119511308Santhony.gutierrez@amd.com sendFunctional(prefetch_pkt); 119611308Santhony.gutierrez@amd.com 119711308Santhony.gutierrez@amd.com /* safe_cast the senderState */ 119811308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *tlb_state = 119911308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>( 120011308Santhony.gutierrez@amd.com prefetch_pkt->senderState); 120111308Santhony.gutierrez@amd.com 120211308Santhony.gutierrez@amd.com 120311308Santhony.gutierrez@amd.com delete tlb_state->tlbEntry; 120411308Santhony.gutierrez@amd.com delete tlb_state; 120511308Santhony.gutierrez@amd.com delete prefetch_pkt; 120611308Santhony.gutierrez@amd.com } 120711308Santhony.gutierrez@amd.com } 120811308Santhony.gutierrez@amd.com 120911308Santhony.gutierrez@amd.com // First we must convert the response cmd back to a request cmd so that 121011308Santhony.gutierrez@amd.com // the request can be sent through the cu's master port 121111308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, requestCmd); 121211308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 121311308Santhony.gutierrez@amd.com delete pkt->senderState; 121411308Santhony.gutierrez@amd.com delete pkt; 121511308Santhony.gutierrez@amd.com 121611308Santhony.gutierrez@amd.com // New SenderState for the memory access 121711308Santhony.gutierrez@amd.com new_pkt->senderState = 121811308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index, 121911308Santhony.gutierrez@amd.com nullptr); 122011308Santhony.gutierrez@amd.com 122111308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the appropriate 122211308Santhony.gutierrez@amd.com // cycle to send the timing memory request to ruby 122312126Sspwilson2@wisc.edu EventFunctionWrapper *mem_req_event = 122412126Sspwilson2@wisc.edu computeUnit->memPort[mp_index]->createMemReqEvent(new_pkt); 122511308Santhony.gutierrez@amd.com 122611308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data scheduled\n", 122711308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 122811308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, mp_index, new_pkt->req->getPaddr()); 122911308Santhony.gutierrez@amd.com 123011308Santhony.gutierrez@amd.com computeUnit->schedule(mem_req_event, curTick() + 123111308Santhony.gutierrez@amd.com computeUnit->req_tick_latency); 123211308Santhony.gutierrez@amd.com 123311308Santhony.gutierrez@amd.com return true; 123411308Santhony.gutierrez@amd.com} 123511308Santhony.gutierrez@amd.com 123612126Sspwilson2@wisc.eduEventFunctionWrapper* 123712126Sspwilson2@wisc.eduComputeUnit::DataPort::createMemReqEvent(PacketPtr pkt) 123811308Santhony.gutierrez@amd.com{ 123912126Sspwilson2@wisc.edu return new EventFunctionWrapper( 124012126Sspwilson2@wisc.edu [this, pkt]{ processMemReqEvent(pkt); }, 124112126Sspwilson2@wisc.edu "ComputeUnit memory request event", true); 124212126Sspwilson2@wisc.edu} 124312126Sspwilson2@wisc.edu 124412126Sspwilson2@wisc.eduEventFunctionWrapper* 124512126Sspwilson2@wisc.eduComputeUnit::DataPort::createMemRespEvent(PacketPtr pkt) 124612126Sspwilson2@wisc.edu{ 124712126Sspwilson2@wisc.edu return new EventFunctionWrapper( 124812126Sspwilson2@wisc.edu [this, pkt]{ processMemRespEvent(pkt); }, 124912126Sspwilson2@wisc.edu "ComputeUnit memory response event", true); 125011308Santhony.gutierrez@amd.com} 125111308Santhony.gutierrez@amd.com 125211308Santhony.gutierrez@amd.comvoid 125312126Sspwilson2@wisc.eduComputeUnit::DataPort::processMemReqEvent(PacketPtr pkt) 125411308Santhony.gutierrez@amd.com{ 125511308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 125611308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 125712126Sspwilson2@wisc.edu ComputeUnit *compute_unit M5_VAR_USED = computeUnit; 125811308Santhony.gutierrez@amd.com 125912126Sspwilson2@wisc.edu if (!(sendTimingReq(pkt))) { 126012126Sspwilson2@wisc.edu retries.push_back(std::make_pair(pkt, gpuDynInst)); 126111308Santhony.gutierrez@amd.com 126211308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 126311308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req failed!\n", 126411308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 126512126Sspwilson2@wisc.edu gpuDynInst->wfSlotId, index, 126611308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 126711308Santhony.gutierrez@amd.com } else { 126811308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 126911308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req sent!\n", 127011308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 127112126Sspwilson2@wisc.edu gpuDynInst->wfSlotId, index, 127211308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 127311308Santhony.gutierrez@amd.com } 127411308Santhony.gutierrez@amd.com} 127511308Santhony.gutierrez@amd.com 127611308Santhony.gutierrez@amd.com/* 127711308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, 127811308Santhony.gutierrez@amd.com * if <retries> queue is not Retry sending the translation 127911308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 128011308Santhony.gutierrez@amd.com * a translation completes. 128111308Santhony.gutierrez@amd.com */ 128211308Santhony.gutierrez@amd.comvoid 128311308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvReqRetry() 128411308Santhony.gutierrez@amd.com{ 128511308Santhony.gutierrez@amd.com int len = retries.size(); 128611308Santhony.gutierrez@amd.com 128711308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLB recvReqRetry - %d pending requests\n", 128811308Santhony.gutierrez@amd.com computeUnit->cu_id, len); 128911308Santhony.gutierrez@amd.com 129011308Santhony.gutierrez@amd.com assert(len > 0); 129111308Santhony.gutierrez@amd.com assert(isStalled()); 129211308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 129311308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 129411308Santhony.gutierrez@amd.com unstallPort(); 129511308Santhony.gutierrez@amd.com 129611308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 129711308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 129811308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 129911308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr); 130011308Santhony.gutierrez@amd.com 130111308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 130211308Santhony.gutierrez@amd.com // Stall port 130311308Santhony.gutierrez@amd.com stallPort(); 130411308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 130511308Santhony.gutierrez@amd.com break; 130611308Santhony.gutierrez@amd.com } else { 130711308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 130811308Santhony.gutierrez@amd.com retries.pop_front(); 130911308Santhony.gutierrez@amd.com } 131011308Santhony.gutierrez@amd.com } 131111308Santhony.gutierrez@amd.com} 131211308Santhony.gutierrez@amd.com 131311308Santhony.gutierrez@amd.combool 131411308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt) 131511308Santhony.gutierrez@amd.com{ 131611308Santhony.gutierrez@amd.com Addr line M5_VAR_USED = pkt->req->getPaddr(); 131711308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n", 131811308Santhony.gutierrez@amd.com computeUnit->cu_id, pkt->req->getVaddr(), line); 131911308Santhony.gutierrez@amd.com 132011308Santhony.gutierrez@amd.com assert(pkt->senderState); 132111308Santhony.gutierrez@amd.com 132211308Santhony.gutierrez@amd.com // pop off the TLB translation state 132311308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 132411308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 132511308Santhony.gutierrez@amd.com 132612717Sbrandon.potter@amd.com bool success = translation_state->tlbEntry != nullptr; 132711308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 132811308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 132911308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 133011308Santhony.gutierrez@amd.com delete translation_state; 133111308Santhony.gutierrez@amd.com 133211308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 133311308Santhony.gutierrez@amd.com ITLBPort::SenderState *sender_state = 133411308Santhony.gutierrez@amd.com safe_cast<ITLBPort::SenderState*>(pkt->senderState); 133511308Santhony.gutierrez@amd.com 133611308Santhony.gutierrez@amd.com // get the wavefront associated with this translation request 133711308Santhony.gutierrez@amd.com Wavefront *wavefront = sender_state->wavefront; 133811308Santhony.gutierrez@amd.com delete pkt->senderState; 133911308Santhony.gutierrez@amd.com 134011308Santhony.gutierrez@amd.com if (success) { 134111308Santhony.gutierrez@amd.com // pkt is reused in fetch(), don't delete it here. However, we must 134211308Santhony.gutierrez@amd.com // reset the command to be a request so that it can be sent through 134311308Santhony.gutierrez@amd.com // the cu's master port 134411308Santhony.gutierrez@amd.com assert(pkt->cmd == MemCmd::ReadResp); 134511308Santhony.gutierrez@amd.com pkt->cmd = MemCmd::ReadReq; 134611308Santhony.gutierrez@amd.com 134711308Santhony.gutierrez@amd.com computeUnit->fetchStage.fetch(pkt, wavefront); 134811308Santhony.gutierrez@amd.com } else { 134911308Santhony.gutierrez@amd.com if (wavefront->dropFetch) { 135011308Santhony.gutierrez@amd.com assert(wavefront->instructionBuffer.empty()); 135111308Santhony.gutierrez@amd.com wavefront->dropFetch = false; 135211308Santhony.gutierrez@amd.com } 135311308Santhony.gutierrez@amd.com 135411308Santhony.gutierrez@amd.com wavefront->pendingFetch = 0; 135511308Santhony.gutierrez@amd.com } 135611308Santhony.gutierrez@amd.com 135711308Santhony.gutierrez@amd.com return true; 135811308Santhony.gutierrez@amd.com} 135911308Santhony.gutierrez@amd.com 136011308Santhony.gutierrez@amd.com/* 136111308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, if 136211308Santhony.gutierrez@amd.com * <retries> queue is not empty. Retry sending the translation 136311308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 136411308Santhony.gutierrez@amd.com * a translation completes. 136511308Santhony.gutierrez@amd.com */ 136611308Santhony.gutierrez@amd.comvoid 136711308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvReqRetry() 136811308Santhony.gutierrez@amd.com{ 136911308Santhony.gutierrez@amd.com 137011308Santhony.gutierrez@amd.com int len = retries.size(); 137111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLB recvReqRetry - %d pending requests\n", len); 137211308Santhony.gutierrez@amd.com 137311308Santhony.gutierrez@amd.com assert(len > 0); 137411308Santhony.gutierrez@amd.com assert(isStalled()); 137511308Santhony.gutierrez@amd.com 137611308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 137711308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 137811308Santhony.gutierrez@amd.com unstallPort(); 137911308Santhony.gutierrez@amd.com 138011308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 138111308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 138211308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 138311308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr); 138411308Santhony.gutierrez@amd.com 138511308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 138611308Santhony.gutierrez@amd.com stallPort(); // Stall port 138711308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 138811308Santhony.gutierrez@amd.com break; 138911308Santhony.gutierrez@amd.com } else { 139011308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 139111308Santhony.gutierrez@amd.com retries.pop_front(); 139211308Santhony.gutierrez@amd.com } 139311308Santhony.gutierrez@amd.com } 139411308Santhony.gutierrez@amd.com} 139511308Santhony.gutierrez@amd.com 139611308Santhony.gutierrez@amd.comvoid 139711308Santhony.gutierrez@amd.comComputeUnit::regStats() 139811308Santhony.gutierrez@amd.com{ 139911523Sdavid.guillen@arm.com MemObject::regStats(); 140011523Sdavid.guillen@arm.com 140111695Santhony.gutierrez@amd.com vALUInsts 140211695Santhony.gutierrez@amd.com .name(name() + ".valu_insts") 140311695Santhony.gutierrez@amd.com .desc("Number of vector ALU insts issued.") 140411695Santhony.gutierrez@amd.com ; 140511695Santhony.gutierrez@amd.com vALUInstsPerWF 140611695Santhony.gutierrez@amd.com .name(name() + ".valu_insts_per_wf") 140711695Santhony.gutierrez@amd.com .desc("The avg. number of vector ALU insts issued per-wavefront.") 140811695Santhony.gutierrez@amd.com ; 140911695Santhony.gutierrez@amd.com sALUInsts 141011695Santhony.gutierrez@amd.com .name(name() + ".salu_insts") 141111695Santhony.gutierrez@amd.com .desc("Number of scalar ALU insts issued.") 141211695Santhony.gutierrez@amd.com ; 141311695Santhony.gutierrez@amd.com sALUInstsPerWF 141411695Santhony.gutierrez@amd.com .name(name() + ".salu_insts_per_wf") 141511695Santhony.gutierrez@amd.com .desc("The avg. number of scalar ALU insts issued per-wavefront.") 141611695Santhony.gutierrez@amd.com ; 141711695Santhony.gutierrez@amd.com instCyclesVALU 141811695Santhony.gutierrez@amd.com .name(name() + ".inst_cycles_valu") 141911695Santhony.gutierrez@amd.com .desc("Number of cycles needed to execute VALU insts.") 142011695Santhony.gutierrez@amd.com ; 142111695Santhony.gutierrez@amd.com instCyclesSALU 142211695Santhony.gutierrez@amd.com .name(name() + ".inst_cycles_salu") 142311695Santhony.gutierrez@amd.com .desc("Number of cycles needed to execute SALU insts.") 142411695Santhony.gutierrez@amd.com ; 142511695Santhony.gutierrez@amd.com threadCyclesVALU 142611695Santhony.gutierrez@amd.com .name(name() + ".thread_cycles_valu") 142711695Santhony.gutierrez@amd.com .desc("Number of thread cycles used to execute vector ALU ops. " 142811695Santhony.gutierrez@amd.com "Similar to instCyclesVALU but multiplied by the number of " 142911695Santhony.gutierrez@amd.com "active threads.") 143011695Santhony.gutierrez@amd.com ; 143111695Santhony.gutierrez@amd.com vALUUtilization 143211695Santhony.gutierrez@amd.com .name(name() + ".valu_utilization") 143311695Santhony.gutierrez@amd.com .desc("Percentage of active vector ALU threads in a wave.") 143411695Santhony.gutierrez@amd.com ; 143511695Santhony.gutierrez@amd.com ldsNoFlatInsts 143611695Santhony.gutierrez@amd.com .name(name() + ".lds_no_flat_insts") 143711695Santhony.gutierrez@amd.com .desc("Number of LDS insts issued, not including FLAT " 143811695Santhony.gutierrez@amd.com "accesses that resolve to LDS.") 143911695Santhony.gutierrez@amd.com ; 144011695Santhony.gutierrez@amd.com ldsNoFlatInstsPerWF 144111695Santhony.gutierrez@amd.com .name(name() + ".lds_no_flat_insts_per_wf") 144211695Santhony.gutierrez@amd.com .desc("The avg. number of LDS insts (not including FLAT " 144311695Santhony.gutierrez@amd.com "accesses that resolve to LDS) per-wavefront.") 144411695Santhony.gutierrez@amd.com ; 144511695Santhony.gutierrez@amd.com flatVMemInsts 144611695Santhony.gutierrez@amd.com .name(name() + ".flat_vmem_insts") 144711695Santhony.gutierrez@amd.com .desc("The number of FLAT insts that resolve to vmem issued.") 144811695Santhony.gutierrez@amd.com ; 144911695Santhony.gutierrez@amd.com flatVMemInstsPerWF 145011695Santhony.gutierrez@amd.com .name(name() + ".flat_vmem_insts_per_wf") 145111695Santhony.gutierrez@amd.com .desc("The average number of FLAT insts that resolve to vmem " 145211695Santhony.gutierrez@amd.com "issued per-wavefront.") 145311695Santhony.gutierrez@amd.com ; 145411695Santhony.gutierrez@amd.com flatLDSInsts 145511695Santhony.gutierrez@amd.com .name(name() + ".flat_lds_insts") 145611695Santhony.gutierrez@amd.com .desc("The number of FLAT insts that resolve to LDS issued.") 145711695Santhony.gutierrez@amd.com ; 145811695Santhony.gutierrez@amd.com flatLDSInstsPerWF 145911695Santhony.gutierrez@amd.com .name(name() + ".flat_lds_insts_per_wf") 146011695Santhony.gutierrez@amd.com .desc("The average number of FLAT insts that resolve to LDS " 146111695Santhony.gutierrez@amd.com "issued per-wavefront.") 146211695Santhony.gutierrez@amd.com ; 146311695Santhony.gutierrez@amd.com vectorMemWrites 146411695Santhony.gutierrez@amd.com .name(name() + ".vector_mem_writes") 146511695Santhony.gutierrez@amd.com .desc("Number of vector mem write insts (excluding FLAT insts).") 146611695Santhony.gutierrez@amd.com ; 146711695Santhony.gutierrez@amd.com vectorMemWritesPerWF 146811695Santhony.gutierrez@amd.com .name(name() + ".vector_mem_writes_per_wf") 146911695Santhony.gutierrez@amd.com .desc("The average number of vector mem write insts " 147011695Santhony.gutierrez@amd.com "(excluding FLAT insts) per-wavefront.") 147111695Santhony.gutierrez@amd.com ; 147211695Santhony.gutierrez@amd.com vectorMemReads 147311695Santhony.gutierrez@amd.com .name(name() + ".vector_mem_reads") 147411695Santhony.gutierrez@amd.com .desc("Number of vector mem read insts (excluding FLAT insts).") 147511695Santhony.gutierrez@amd.com ; 147611695Santhony.gutierrez@amd.com vectorMemReadsPerWF 147711695Santhony.gutierrez@amd.com .name(name() + ".vector_mem_reads_per_wf") 147811695Santhony.gutierrez@amd.com .desc("The avg. number of vector mem read insts (excluding " 147911695Santhony.gutierrez@amd.com "FLAT insts) per-wavefront.") 148011695Santhony.gutierrez@amd.com ; 148111695Santhony.gutierrez@amd.com scalarMemWrites 148211695Santhony.gutierrez@amd.com .name(name() + ".scalar_mem_writes") 148311695Santhony.gutierrez@amd.com .desc("Number of scalar mem write insts.") 148411695Santhony.gutierrez@amd.com ; 148511695Santhony.gutierrez@amd.com scalarMemWritesPerWF 148611695Santhony.gutierrez@amd.com .name(name() + ".scalar_mem_writes_per_wf") 148711695Santhony.gutierrez@amd.com .desc("The average number of scalar mem write insts per-wavefront.") 148811695Santhony.gutierrez@amd.com ; 148911695Santhony.gutierrez@amd.com scalarMemReads 149011695Santhony.gutierrez@amd.com .name(name() + ".scalar_mem_reads") 149111695Santhony.gutierrez@amd.com .desc("Number of scalar mem read insts.") 149211695Santhony.gutierrez@amd.com ; 149311695Santhony.gutierrez@amd.com scalarMemReadsPerWF 149411695Santhony.gutierrez@amd.com .name(name() + ".scalar_mem_reads_per_wf") 149511695Santhony.gutierrez@amd.com .desc("The average number of scalar mem read insts per-wavefront.") 149611695Santhony.gutierrez@amd.com ; 149711695Santhony.gutierrez@amd.com 149811695Santhony.gutierrez@amd.com vALUInstsPerWF = vALUInsts / completedWfs; 149911695Santhony.gutierrez@amd.com sALUInstsPerWF = sALUInsts / completedWfs; 150011695Santhony.gutierrez@amd.com vALUUtilization = (threadCyclesVALU / (64 * instCyclesVALU)) * 100; 150111695Santhony.gutierrez@amd.com ldsNoFlatInstsPerWF = ldsNoFlatInsts / completedWfs; 150211695Santhony.gutierrez@amd.com flatVMemInstsPerWF = flatVMemInsts / completedWfs; 150311695Santhony.gutierrez@amd.com flatLDSInstsPerWF = flatLDSInsts / completedWfs; 150411695Santhony.gutierrez@amd.com vectorMemWritesPerWF = vectorMemWrites / completedWfs; 150511695Santhony.gutierrez@amd.com vectorMemReadsPerWF = vectorMemReads / completedWfs; 150611695Santhony.gutierrez@amd.com scalarMemWritesPerWF = scalarMemWrites / completedWfs; 150711695Santhony.gutierrez@amd.com scalarMemReadsPerWF = scalarMemReads / completedWfs; 150811695Santhony.gutierrez@amd.com 150911308Santhony.gutierrez@amd.com tlbCycles 151011308Santhony.gutierrez@amd.com .name(name() + ".tlb_cycles") 151111308Santhony.gutierrez@amd.com .desc("total number of cycles for all uncoalesced requests") 151211308Santhony.gutierrez@amd.com ; 151311308Santhony.gutierrez@amd.com 151411308Santhony.gutierrez@amd.com tlbRequests 151511308Santhony.gutierrez@amd.com .name(name() + ".tlb_requests") 151611308Santhony.gutierrez@amd.com .desc("number of uncoalesced requests") 151711308Santhony.gutierrez@amd.com ; 151811308Santhony.gutierrez@amd.com 151911308Santhony.gutierrez@amd.com tlbLatency 152011308Santhony.gutierrez@amd.com .name(name() + ".avg_translation_latency") 152111308Santhony.gutierrez@amd.com .desc("Avg. translation latency for data translations") 152211308Santhony.gutierrez@amd.com ; 152311308Santhony.gutierrez@amd.com 152411308Santhony.gutierrez@amd.com tlbLatency = tlbCycles / tlbRequests; 152511308Santhony.gutierrez@amd.com 152611308Santhony.gutierrez@amd.com hitsPerTLBLevel 152711308Santhony.gutierrez@amd.com .init(4) 152811308Santhony.gutierrez@amd.com .name(name() + ".TLB_hits_distribution") 152911308Santhony.gutierrez@amd.com .desc("TLB hits distribution (0 for page table, x for Lx-TLB") 153011308Santhony.gutierrez@amd.com ; 153111308Santhony.gutierrez@amd.com 153211308Santhony.gutierrez@amd.com // fixed number of TLB levels 153311308Santhony.gutierrez@amd.com for (int i = 0; i < 4; ++i) { 153411308Santhony.gutierrez@amd.com if (!i) 153511308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i,"page_table"); 153611308Santhony.gutierrez@amd.com else 153711308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i, csprintf("L%d_TLB",i)); 153811308Santhony.gutierrez@amd.com } 153911308Santhony.gutierrez@amd.com 154011308Santhony.gutierrez@amd.com execRateDist 154111308Santhony.gutierrez@amd.com .init(0, 10, 2) 154211308Santhony.gutierrez@amd.com .name(name() + ".inst_exec_rate") 154311308Santhony.gutierrez@amd.com .desc("Instruction Execution Rate: Number of executed vector " 154411308Santhony.gutierrez@amd.com "instructions per cycle") 154511308Santhony.gutierrez@amd.com ; 154611308Santhony.gutierrez@amd.com 154711308Santhony.gutierrez@amd.com ldsBankConflictDist 154811534Sjohn.kalamatianos@amd.com .init(0, wfSize(), 2) 154911308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_conflicts") 155011308Santhony.gutierrez@amd.com .desc("Number of bank conflicts per LDS memory packet") 155111308Santhony.gutierrez@amd.com ; 155211308Santhony.gutierrez@amd.com 155311308Santhony.gutierrez@amd.com ldsBankAccesses 155411308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_access_cnt") 155511308Santhony.gutierrez@amd.com .desc("Total number of LDS bank accesses") 155611308Santhony.gutierrez@amd.com ; 155711308Santhony.gutierrez@amd.com 155811308Santhony.gutierrez@amd.com pageDivergenceDist 155911534Sjohn.kalamatianos@amd.com // A wavefront can touch up to N pages per memory instruction where 156011534Sjohn.kalamatianos@amd.com // N is equal to the wavefront size 156111534Sjohn.kalamatianos@amd.com // The number of pages per bin can be configured (here it's 4). 156211534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 156311308Santhony.gutierrez@amd.com .name(name() + ".page_divergence_dist") 156411308Santhony.gutierrez@amd.com .desc("pages touched per wf (over all mem. instr.)") 156511308Santhony.gutierrez@amd.com ; 156611308Santhony.gutierrez@amd.com 156711308Santhony.gutierrez@amd.com controlFlowDivergenceDist 156811534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 156911308Santhony.gutierrez@amd.com .name(name() + ".warp_execution_dist") 157011308Santhony.gutierrez@amd.com .desc("number of lanes active per instruction (oval all instructions)") 157111308Santhony.gutierrez@amd.com ; 157211308Santhony.gutierrez@amd.com 157311308Santhony.gutierrez@amd.com activeLanesPerGMemInstrDist 157411534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 157511308Santhony.gutierrez@amd.com .name(name() + ".gmem_lanes_execution_dist") 157611308Santhony.gutierrez@amd.com .desc("number of active lanes per global memory instruction") 157711308Santhony.gutierrez@amd.com ; 157811308Santhony.gutierrez@amd.com 157911308Santhony.gutierrez@amd.com activeLanesPerLMemInstrDist 158011534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 158111308Santhony.gutierrez@amd.com .name(name() + ".lmem_lanes_execution_dist") 158211308Santhony.gutierrez@amd.com .desc("number of active lanes per local memory instruction") 158311308Santhony.gutierrez@amd.com ; 158411308Santhony.gutierrez@amd.com 158511308Santhony.gutierrez@amd.com numInstrExecuted 158611308Santhony.gutierrez@amd.com .name(name() + ".num_instr_executed") 158711308Santhony.gutierrez@amd.com .desc("number of instructions executed") 158811308Santhony.gutierrez@amd.com ; 158911308Santhony.gutierrez@amd.com 159011308Santhony.gutierrez@amd.com numVecOpsExecuted 159111308Santhony.gutierrez@amd.com .name(name() + ".num_vec_ops_executed") 159211534Sjohn.kalamatianos@amd.com .desc("number of vec ops executed (e.g. WF size/inst)") 159311308Santhony.gutierrez@amd.com ; 159411308Santhony.gutierrez@amd.com 159511308Santhony.gutierrez@amd.com totalCycles 159611308Santhony.gutierrez@amd.com .name(name() + ".num_total_cycles") 159711308Santhony.gutierrez@amd.com .desc("number of cycles the CU ran for") 159811308Santhony.gutierrez@amd.com ; 159911308Santhony.gutierrez@amd.com 160011308Santhony.gutierrez@amd.com ipc 160111308Santhony.gutierrez@amd.com .name(name() + ".ipc") 160211308Santhony.gutierrez@amd.com .desc("Instructions per cycle (this CU only)") 160311308Santhony.gutierrez@amd.com ; 160411308Santhony.gutierrez@amd.com 160511308Santhony.gutierrez@amd.com vpc 160611308Santhony.gutierrez@amd.com .name(name() + ".vpc") 160711308Santhony.gutierrez@amd.com .desc("Vector Operations per cycle (this CU only)") 160811308Santhony.gutierrez@amd.com ; 160911308Santhony.gutierrez@amd.com 161011308Santhony.gutierrez@amd.com numALUInstsExecuted 161111308Santhony.gutierrez@amd.com .name(name() + ".num_alu_insts_executed") 161211308Santhony.gutierrez@amd.com .desc("Number of dynamic non-GM memory insts executed") 161311308Santhony.gutierrez@amd.com ; 161411308Santhony.gutierrez@amd.com 161511308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation 161611308Santhony.gutierrez@amd.com .name(name() + ".wg_blocked_due_lds_alloc") 161711308Santhony.gutierrez@amd.com .desc("Workgroup blocked due to LDS capacity") 161811308Santhony.gutierrez@amd.com ; 161911308Santhony.gutierrez@amd.com 162011308Santhony.gutierrez@amd.com ipc = numInstrExecuted / totalCycles; 162111308Santhony.gutierrez@amd.com vpc = numVecOpsExecuted / totalCycles; 162211308Santhony.gutierrez@amd.com 162311308Santhony.gutierrez@amd.com numTimesWgBlockedDueVgprAlloc 162411308Santhony.gutierrez@amd.com .name(name() + ".times_wg_blocked_due_vgpr_alloc") 162511308Santhony.gutierrez@amd.com .desc("Number of times WGs are blocked due to VGPR allocation per SIMD") 162611308Santhony.gutierrez@amd.com ; 162711308Santhony.gutierrez@amd.com 162811308Santhony.gutierrez@amd.com dynamicGMemInstrCnt 162911308Santhony.gutierrez@amd.com .name(name() + ".global_mem_instr_cnt") 163011308Santhony.gutierrez@amd.com .desc("dynamic global memory instructions count") 163111308Santhony.gutierrez@amd.com ; 163211308Santhony.gutierrez@amd.com 163311308Santhony.gutierrez@amd.com dynamicLMemInstrCnt 163411308Santhony.gutierrez@amd.com .name(name() + ".local_mem_instr_cnt") 163511308Santhony.gutierrez@amd.com .desc("dynamic local memory intruction count") 163611308Santhony.gutierrez@amd.com ; 163711308Santhony.gutierrez@amd.com 163811308Santhony.gutierrez@amd.com numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt - 163911308Santhony.gutierrez@amd.com dynamicLMemInstrCnt; 164011308Santhony.gutierrez@amd.com 164111308Santhony.gutierrez@amd.com completedWfs 164211308Santhony.gutierrez@amd.com .name(name() + ".num_completed_wfs") 164311308Santhony.gutierrez@amd.com .desc("number of completed wavefronts") 164411308Santhony.gutierrez@amd.com ; 164511308Santhony.gutierrez@amd.com 164611308Santhony.gutierrez@amd.com numCASOps 164711308Santhony.gutierrez@amd.com .name(name() + ".num_CAS_ops") 164811308Santhony.gutierrez@amd.com .desc("number of compare and swap operations") 164911308Santhony.gutierrez@amd.com ; 165011308Santhony.gutierrez@amd.com 165111308Santhony.gutierrez@amd.com numFailedCASOps 165211308Santhony.gutierrez@amd.com .name(name() + ".num_failed_CAS_ops") 165311308Santhony.gutierrez@amd.com .desc("number of compare and swap operations that failed") 165411308Santhony.gutierrez@amd.com ; 165511308Santhony.gutierrez@amd.com 165611308Santhony.gutierrez@amd.com // register stats of pipeline stages 165711308Santhony.gutierrez@amd.com fetchStage.regStats(); 165811308Santhony.gutierrez@amd.com scoreboardCheckStage.regStats(); 165911308Santhony.gutierrez@amd.com scheduleStage.regStats(); 166011308Santhony.gutierrez@amd.com execStage.regStats(); 166111308Santhony.gutierrez@amd.com 166211308Santhony.gutierrez@amd.com // register stats of memory pipeline 166311308Santhony.gutierrez@amd.com globalMemoryPipe.regStats(); 166411308Santhony.gutierrez@amd.com localMemoryPipe.regStats(); 166511308Santhony.gutierrez@amd.com} 166611308Santhony.gutierrez@amd.com 166711308Santhony.gutierrez@amd.comvoid 166811695Santhony.gutierrez@amd.comComputeUnit::updateInstStats(GPUDynInstPtr gpuDynInst) 166911695Santhony.gutierrez@amd.com{ 167011695Santhony.gutierrez@amd.com if (gpuDynInst->isScalar()) { 167111695Santhony.gutierrez@amd.com if (gpuDynInst->isALU() && !gpuDynInst->isWaitcnt()) { 167211695Santhony.gutierrez@amd.com sALUInsts++; 167311695Santhony.gutierrez@amd.com instCyclesSALU++; 167411695Santhony.gutierrez@amd.com } else if (gpuDynInst->isLoad()) { 167511695Santhony.gutierrez@amd.com scalarMemReads++; 167611695Santhony.gutierrez@amd.com } else if (gpuDynInst->isStore()) { 167711695Santhony.gutierrez@amd.com scalarMemWrites++; 167811695Santhony.gutierrez@amd.com } 167911695Santhony.gutierrez@amd.com } else { 168011695Santhony.gutierrez@amd.com if (gpuDynInst->isALU()) { 168111695Santhony.gutierrez@amd.com vALUInsts++; 168211695Santhony.gutierrez@amd.com instCyclesVALU++; 168311695Santhony.gutierrez@amd.com threadCyclesVALU += gpuDynInst->wavefront()->execMask().count(); 168411695Santhony.gutierrez@amd.com } else if (gpuDynInst->isFlat()) { 168511695Santhony.gutierrez@amd.com if (gpuDynInst->isLocalMem()) { 168611695Santhony.gutierrez@amd.com flatLDSInsts++; 168711695Santhony.gutierrez@amd.com } else { 168811695Santhony.gutierrez@amd.com flatVMemInsts++; 168911695Santhony.gutierrez@amd.com } 169011695Santhony.gutierrez@amd.com } else if (gpuDynInst->isLocalMem()) { 169111695Santhony.gutierrez@amd.com ldsNoFlatInsts++; 169211695Santhony.gutierrez@amd.com } else if (gpuDynInst->isLoad()) { 169311695Santhony.gutierrez@amd.com vectorMemReads++; 169411695Santhony.gutierrez@amd.com } else if (gpuDynInst->isStore()) { 169511695Santhony.gutierrez@amd.com vectorMemWrites++; 169611695Santhony.gutierrez@amd.com } 169711695Santhony.gutierrez@amd.com } 169811695Santhony.gutierrez@amd.com} 169911695Santhony.gutierrez@amd.com 170011695Santhony.gutierrez@amd.comvoid 170111308Santhony.gutierrez@amd.comComputeUnit::updatePageDivergenceDist(Addr addr) 170211308Santhony.gutierrez@amd.com{ 170311308Santhony.gutierrez@amd.com Addr virt_page_addr = roundDown(addr, TheISA::PageBytes); 170411308Santhony.gutierrez@amd.com 170511308Santhony.gutierrez@amd.com if (!pagesTouched.count(virt_page_addr)) 170611308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr] = 1; 170711308Santhony.gutierrez@amd.com else 170811308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr]++; 170911308Santhony.gutierrez@amd.com} 171011308Santhony.gutierrez@amd.com 171111308Santhony.gutierrez@amd.comvoid 171211308Santhony.gutierrez@amd.comComputeUnit::CUExitCallback::process() 171311308Santhony.gutierrez@amd.com{ 171411308Santhony.gutierrez@amd.com if (computeUnit->countPages) { 171511308Santhony.gutierrez@amd.com std::ostream *page_stat_file = 171611364Sandreas.hansson@arm.com simout.create(computeUnit->name().c_str())->stream(); 171711308Santhony.gutierrez@amd.com 171811308Santhony.gutierrez@amd.com *page_stat_file << "page, wavefront accesses, workitem accesses" << 171911308Santhony.gutierrez@amd.com std::endl; 172011308Santhony.gutierrez@amd.com 172111308Santhony.gutierrez@amd.com for (auto iter : computeUnit->pageAccesses) { 172211308Santhony.gutierrez@amd.com *page_stat_file << std::hex << iter.first << ","; 172311308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.first << ","; 172411308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.second << std::endl; 172511308Santhony.gutierrez@amd.com } 172611308Santhony.gutierrez@amd.com } 172711308Santhony.gutierrez@amd.com } 172811308Santhony.gutierrez@amd.com 172911308Santhony.gutierrez@amd.combool 173011308Santhony.gutierrez@amd.comComputeUnit::isDone() const 173111308Santhony.gutierrez@amd.com{ 173211308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 173311308Santhony.gutierrez@amd.com if (!isSimdDone(i)) { 173411308Santhony.gutierrez@amd.com return false; 173511308Santhony.gutierrez@amd.com } 173611308Santhony.gutierrez@amd.com } 173711308Santhony.gutierrez@amd.com 173811308Santhony.gutierrez@amd.com bool glbMemBusRdy = true; 173911308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 174011308Santhony.gutierrez@amd.com glbMemBusRdy &= vrfToGlobalMemPipeBus[j].rdy(); 174111308Santhony.gutierrez@amd.com } 174211308Santhony.gutierrez@amd.com bool locMemBusRdy = true; 174311308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 174411308Santhony.gutierrez@amd.com locMemBusRdy &= vrfToLocalMemPipeBus[j].rdy(); 174511308Santhony.gutierrez@amd.com } 174611308Santhony.gutierrez@amd.com 174711308Santhony.gutierrez@amd.com if (!globalMemoryPipe.isGMLdRespFIFOWrRdy() || 174811308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMStRespFIFOWrRdy() || 174911308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMReqFIFOWrRdy() || !localMemoryPipe.isLMReqFIFOWrRdy() 175011308Santhony.gutierrez@amd.com || !localMemoryPipe.isLMRespFIFOWrRdy() || !locMemToVrfBus.rdy() || 175111308Santhony.gutierrez@amd.com !glbMemToVrfBus.rdy() || !locMemBusRdy || !glbMemBusRdy) { 175211308Santhony.gutierrez@amd.com return false; 175311308Santhony.gutierrez@amd.com } 175411308Santhony.gutierrez@amd.com 175511308Santhony.gutierrez@amd.com return true; 175611308Santhony.gutierrez@amd.com} 175711308Santhony.gutierrez@amd.com 175811308Santhony.gutierrez@amd.comint32_t 175911308Santhony.gutierrez@amd.comComputeUnit::getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const 176011308Santhony.gutierrez@amd.com{ 176111308Santhony.gutierrez@amd.com return lds.getRefCounter(dispatchId, wgId); 176211308Santhony.gutierrez@amd.com} 176311308Santhony.gutierrez@amd.com 176411308Santhony.gutierrez@amd.combool 176511308Santhony.gutierrez@amd.comComputeUnit::isSimdDone(uint32_t simdId) const 176611308Santhony.gutierrez@amd.com{ 176711308Santhony.gutierrez@amd.com assert(simdId < numSIMDs); 176811308Santhony.gutierrez@amd.com 176911308Santhony.gutierrez@amd.com for (int i=0; i < numGlbMemUnits; ++i) { 177011308Santhony.gutierrez@amd.com if (!vrfToGlobalMemPipeBus[i].rdy()) 177111308Santhony.gutierrez@amd.com return false; 177211308Santhony.gutierrez@amd.com } 177311308Santhony.gutierrez@amd.com for (int i=0; i < numLocMemUnits; ++i) { 177411308Santhony.gutierrez@amd.com if (!vrfToLocalMemPipeBus[i].rdy()) 177511308Santhony.gutierrez@amd.com return false; 177611308Santhony.gutierrez@amd.com } 177711308Santhony.gutierrez@amd.com if (!aluPipe[simdId].rdy()) { 177811308Santhony.gutierrez@amd.com return false; 177911308Santhony.gutierrez@amd.com } 178011308Santhony.gutierrez@amd.com 178111308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf){ 178211308Santhony.gutierrez@amd.com if (wfList[simdId][i_wf]->status != Wavefront::S_STOPPED) { 178311308Santhony.gutierrez@amd.com return false; 178411308Santhony.gutierrez@amd.com } 178511308Santhony.gutierrez@amd.com } 178611308Santhony.gutierrez@amd.com 178711308Santhony.gutierrez@amd.com return true; 178811308Santhony.gutierrez@amd.com} 178911308Santhony.gutierrez@amd.com 179011308Santhony.gutierrez@amd.com/** 179111308Santhony.gutierrez@amd.com * send a general request to the LDS 179211308Santhony.gutierrez@amd.com * make sure to look at the return value here as your request might be 179311308Santhony.gutierrez@amd.com * NACK'd and returning false means that you have to have some backup plan 179411308Santhony.gutierrez@amd.com */ 179511308Santhony.gutierrez@amd.combool 179611308Santhony.gutierrez@amd.comComputeUnit::sendToLds(GPUDynInstPtr gpuDynInst) 179711308Santhony.gutierrez@amd.com{ 179811308Santhony.gutierrez@amd.com // this is just a request to carry the GPUDynInstPtr 179911308Santhony.gutierrez@amd.com // back and forth 180012749Sgiacomo.travaglini@arm.com RequestPtr newRequest = std::make_shared<Request>(); 180111308Santhony.gutierrez@amd.com newRequest->setPaddr(0x0); 180211308Santhony.gutierrez@amd.com 180311308Santhony.gutierrez@amd.com // ReadReq is not evaluted by the LDS but the Packet ctor requires this 180411308Santhony.gutierrez@amd.com PacketPtr newPacket = new Packet(newRequest, MemCmd::ReadReq); 180511308Santhony.gutierrez@amd.com 180611308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 180711308Santhony.gutierrez@amd.com newPacket->senderState = new LDSPort::SenderState(gpuDynInst); 180811308Santhony.gutierrez@amd.com 180911308Santhony.gutierrez@amd.com return ldsPort->sendTimingReq(newPacket); 181011308Santhony.gutierrez@amd.com} 181111308Santhony.gutierrez@amd.com 181211308Santhony.gutierrez@amd.com/** 181311308Santhony.gutierrez@amd.com * get the result of packets sent to the LDS when they return 181411308Santhony.gutierrez@amd.com */ 181511308Santhony.gutierrez@amd.combool 181611308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvTimingResp(PacketPtr packet) 181711308Santhony.gutierrez@amd.com{ 181811308Santhony.gutierrez@amd.com const ComputeUnit::LDSPort::SenderState *senderState = 181911308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState *>(packet->senderState); 182011308Santhony.gutierrez@amd.com 182111308Santhony.gutierrez@amd.com fatal_if(!senderState, "did not get the right sort of sender state"); 182211308Santhony.gutierrez@amd.com 182311308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = senderState->getMemInst(); 182411308Santhony.gutierrez@amd.com 182511308Santhony.gutierrez@amd.com delete packet->senderState; 182611308Santhony.gutierrez@amd.com delete packet; 182711308Santhony.gutierrez@amd.com 182811308Santhony.gutierrez@amd.com computeUnit->localMemoryPipe.getLMRespFIFO().push(gpuDynInst); 182911308Santhony.gutierrez@amd.com return true; 183011308Santhony.gutierrez@amd.com} 183111308Santhony.gutierrez@amd.com 183211308Santhony.gutierrez@amd.com/** 183311308Santhony.gutierrez@amd.com * attempt to send this packet, either the port is already stalled, the request 183411308Santhony.gutierrez@amd.com * is nack'd and must stall or the request goes through 183511308Santhony.gutierrez@amd.com * when a request cannot be sent, add it to the retries queue 183611308Santhony.gutierrez@amd.com */ 183711308Santhony.gutierrez@amd.combool 183811308Santhony.gutierrez@amd.comComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt) 183911308Santhony.gutierrez@amd.com{ 184011308Santhony.gutierrez@amd.com ComputeUnit::LDSPort::SenderState *sender_state = 184111308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState); 184211308Santhony.gutierrez@amd.com fatal_if(!sender_state, "packet without a valid sender state"); 184311308Santhony.gutierrez@amd.com 184411308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = sender_state->getMemInst(); 184511308Santhony.gutierrez@amd.com 184611308Santhony.gutierrez@amd.com if (isStalled()) { 184711308Santhony.gutierrez@amd.com fatal_if(retries.empty(), "must have retries waiting to be stalled"); 184811308Santhony.gutierrez@amd.com 184911308Santhony.gutierrez@amd.com retries.push(pkt); 185011308Santhony.gutierrez@amd.com 185111308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: LDS send failed!\n", 185211308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 185311308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 185411308Santhony.gutierrez@amd.com return false; 185511308Santhony.gutierrez@amd.com } else if (!MasterPort::sendTimingReq(pkt)) { 185611308Santhony.gutierrez@amd.com // need to stall the LDS port until a recvReqRetry() is received 185711308Santhony.gutierrez@amd.com // this indicates that there is more space 185811308Santhony.gutierrez@amd.com stallPort(); 185911308Santhony.gutierrez@amd.com retries.push(pkt); 186011308Santhony.gutierrez@amd.com 186111308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req failed!\n", 186211308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 186311308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 186411308Santhony.gutierrez@amd.com return false; 186511308Santhony.gutierrez@amd.com } else { 186611308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req sent!\n", 186711308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 186811308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 186911308Santhony.gutierrez@amd.com return true; 187011308Santhony.gutierrez@amd.com } 187111308Santhony.gutierrez@amd.com} 187211308Santhony.gutierrez@amd.com 187311308Santhony.gutierrez@amd.com/** 187411308Santhony.gutierrez@amd.com * the bus is telling the port that there is now space so retrying stalled 187511308Santhony.gutierrez@amd.com * requests should work now 187611308Santhony.gutierrez@amd.com * this allows the port to have a request be nack'd and then have the receiver 187711308Santhony.gutierrez@amd.com * say when there is space, rather than simply retrying the send every cycle 187811308Santhony.gutierrez@amd.com */ 187911308Santhony.gutierrez@amd.comvoid 188011308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvReqRetry() 188111308Santhony.gutierrez@amd.com{ 188211308Santhony.gutierrez@amd.com auto queueSize = retries.size(); 188311308Santhony.gutierrez@amd.com 188411308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: LDSPort recvReqRetry - %d pending requests\n", 188511308Santhony.gutierrez@amd.com computeUnit->cu_id, queueSize); 188611308Santhony.gutierrez@amd.com 188711308Santhony.gutierrez@amd.com fatal_if(queueSize < 1, 188811308Santhony.gutierrez@amd.com "why was there a recvReqRetry() with no pending reqs?"); 188911308Santhony.gutierrez@amd.com fatal_if(!isStalled(), 189011308Santhony.gutierrez@amd.com "recvReqRetry() happened when the port was not stalled"); 189111308Santhony.gutierrez@amd.com 189211308Santhony.gutierrez@amd.com unstallPort(); 189311308Santhony.gutierrez@amd.com 189411308Santhony.gutierrez@amd.com while (!retries.empty()) { 189511308Santhony.gutierrez@amd.com PacketPtr packet = retries.front(); 189611308Santhony.gutierrez@amd.com 189711308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id); 189811308Santhony.gutierrez@amd.com 189911308Santhony.gutierrez@amd.com if (!MasterPort::sendTimingReq(packet)) { 190011308Santhony.gutierrez@amd.com // Stall port 190111308Santhony.gutierrez@amd.com stallPort(); 190211308Santhony.gutierrez@amd.com DPRINTF(GPUPort, ": LDS send failed again\n"); 190311308Santhony.gutierrez@amd.com break; 190411308Santhony.gutierrez@amd.com } else { 190511308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": LDS send successful\n"); 190611308Santhony.gutierrez@amd.com retries.pop(); 190711308Santhony.gutierrez@amd.com } 190811308Santhony.gutierrez@amd.com } 190911308Santhony.gutierrez@amd.com} 1910