compute_unit.cc revision 11639
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com * may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com * without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: John Kalamatianos, Anthony Gutierrez 3411308Santhony.gutierrez@amd.com */ 3511534Sjohn.kalamatianos@amd.com#include "gpu-compute/compute_unit.hh" 3611308Santhony.gutierrez@amd.com 3711534Sjohn.kalamatianos@amd.com#include <limits> 3811308Santhony.gutierrez@amd.com 3911308Santhony.gutierrez@amd.com#include "base/output.hh" 4011308Santhony.gutierrez@amd.com#include "debug/GPUDisp.hh" 4111308Santhony.gutierrez@amd.com#include "debug/GPUExec.hh" 4211308Santhony.gutierrez@amd.com#include "debug/GPUFetch.hh" 4311308Santhony.gutierrez@amd.com#include "debug/GPUMem.hh" 4411308Santhony.gutierrez@amd.com#include "debug/GPUPort.hh" 4511308Santhony.gutierrez@amd.com#include "debug/GPUPrefetch.hh" 4611308Santhony.gutierrez@amd.com#include "debug/GPUSync.hh" 4711308Santhony.gutierrez@amd.com#include "debug/GPUTLB.hh" 4811308Santhony.gutierrez@amd.com#include "gpu-compute/dispatcher.hh" 4911308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_dyn_inst.hh" 5011308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_static_inst.hh" 5111308Santhony.gutierrez@amd.com#include "gpu-compute/ndrange.hh" 5211308Santhony.gutierrez@amd.com#include "gpu-compute/shader.hh" 5311308Santhony.gutierrez@amd.com#include "gpu-compute/simple_pool_manager.hh" 5411308Santhony.gutierrez@amd.com#include "gpu-compute/vector_register_file.hh" 5511308Santhony.gutierrez@amd.com#include "gpu-compute/wavefront.hh" 5611308Santhony.gutierrez@amd.com#include "mem/page_table.hh" 5711308Santhony.gutierrez@amd.com#include "sim/process.hh" 5811308Santhony.gutierrez@amd.com 5911308Santhony.gutierrez@amd.comComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p), 6011308Santhony.gutierrez@amd.com scoreboardCheckStage(p), scheduleStage(p), execStage(p), 6111308Santhony.gutierrez@amd.com globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0), 6211308Santhony.gutierrez@amd.com cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs), 6311308Santhony.gutierrez@amd.com spBypassPipeLength(p->spbypass_pipe_length), 6411308Santhony.gutierrez@amd.com dpBypassPipeLength(p->dpbypass_pipe_length), 6511308Santhony.gutierrez@amd.com issuePeriod(p->issue_period), 6611308Santhony.gutierrez@amd.com numGlbMemUnits(p->num_global_mem_pipes), 6711308Santhony.gutierrez@amd.com numLocMemUnits(p->num_shared_mem_pipes), 6811308Santhony.gutierrez@amd.com perLaneTLB(p->perLaneTLB), prefetchDepth(p->prefetch_depth), 6911308Santhony.gutierrez@amd.com prefetchStride(p->prefetch_stride), prefetchType(p->prefetch_prev_type), 7011308Santhony.gutierrez@amd.com xact_cas_mode(p->xactCasMode), debugSegFault(p->debugSegFault), 7111308Santhony.gutierrez@amd.com functionalTLB(p->functionalTLB), localMemBarrier(p->localMemBarrier), 7211308Santhony.gutierrez@amd.com countPages(p->countPages), barrier_id(0), 7311308Santhony.gutierrez@amd.com vrfToCoalescerBusWidth(p->vrf_to_coalescer_bus_width), 7411308Santhony.gutierrez@amd.com coalescerToVrfBusWidth(p->coalescer_to_vrf_bus_width), 7511308Santhony.gutierrez@amd.com req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()), 7611308Santhony.gutierrez@amd.com resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()), 7711308Santhony.gutierrez@amd.com _masterId(p->system->getMasterId(name() + ".ComputeUnit")), 7811308Santhony.gutierrez@amd.com lds(*p->localDataStore), globalSeqNum(0), wavefrontSize(p->wfSize) 7911308Santhony.gutierrez@amd.com{ 8011534Sjohn.kalamatianos@amd.com /** 8111534Sjohn.kalamatianos@amd.com * This check is necessary because std::bitset only provides conversion 8211534Sjohn.kalamatianos@amd.com * to unsigned long or unsigned long long via to_ulong() or to_ullong(). 8311534Sjohn.kalamatianos@amd.com * there are * a few places in the code where to_ullong() is used, however 8411534Sjohn.kalamatianos@amd.com * if VSZ is larger than a value the host can support then bitset will 8511534Sjohn.kalamatianos@amd.com * throw a runtime exception. we should remove all use of to_long() or 8611534Sjohn.kalamatianos@amd.com * to_ullong() so we can have VSZ greater than 64b, however until that is 8711534Sjohn.kalamatianos@amd.com * done this assert is required. 8811534Sjohn.kalamatianos@amd.com */ 8911534Sjohn.kalamatianos@amd.com fatal_if(p->wfSize > std::numeric_limits<unsigned long long>::digits || 9011534Sjohn.kalamatianos@amd.com p->wfSize <= 0, 9111534Sjohn.kalamatianos@amd.com "WF size is larger than the host can support"); 9211534Sjohn.kalamatianos@amd.com fatal_if(!isPowerOf2(wavefrontSize), 9311534Sjohn.kalamatianos@amd.com "Wavefront size should be a power of 2"); 9411308Santhony.gutierrez@amd.com // calculate how many cycles a vector load or store will need to transfer 9511308Santhony.gutierrez@amd.com // its data over the corresponding buses 9611534Sjohn.kalamatianos@amd.com numCyclesPerStoreTransfer = 9711534Sjohn.kalamatianos@amd.com (uint32_t)ceil((double)(wfSize() * sizeof(uint32_t)) / 9811534Sjohn.kalamatianos@amd.com (double)vrfToCoalescerBusWidth); 9911308Santhony.gutierrez@amd.com 10011534Sjohn.kalamatianos@amd.com numCyclesPerLoadTransfer = (wfSize() * sizeof(uint32_t)) 10111308Santhony.gutierrez@amd.com / coalescerToVrfBusWidth; 10211308Santhony.gutierrez@amd.com 10311308Santhony.gutierrez@amd.com lastVaddrWF.resize(numSIMDs); 10411308Santhony.gutierrez@amd.com wfList.resize(numSIMDs); 10511308Santhony.gutierrez@amd.com 10611308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 10711308Santhony.gutierrez@amd.com lastVaddrWF[j].resize(p->n_wf); 10811308Santhony.gutierrez@amd.com 10911308Santhony.gutierrez@amd.com for (int i = 0; i < p->n_wf; ++i) { 11011534Sjohn.kalamatianos@amd.com lastVaddrWF[j][i].resize(wfSize()); 11111308Santhony.gutierrez@amd.com 11211308Santhony.gutierrez@amd.com wfList[j].push_back(p->wavefronts[j * p->n_wf + i]); 11311308Santhony.gutierrez@amd.com wfList[j][i]->setParent(this); 11411308Santhony.gutierrez@amd.com 11511534Sjohn.kalamatianos@amd.com for (int k = 0; k < wfSize(); ++k) { 11611308Santhony.gutierrez@amd.com lastVaddrWF[j][i][k] = 0; 11711308Santhony.gutierrez@amd.com } 11811308Santhony.gutierrez@amd.com } 11911308Santhony.gutierrez@amd.com } 12011308Santhony.gutierrez@amd.com 12111534Sjohn.kalamatianos@amd.com lastVaddrSimd.resize(numSIMDs); 12211308Santhony.gutierrez@amd.com 12311308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 12411534Sjohn.kalamatianos@amd.com lastVaddrSimd[i].resize(wfSize(), 0); 12511308Santhony.gutierrez@amd.com } 12611308Santhony.gutierrez@amd.com 12711534Sjohn.kalamatianos@amd.com lastVaddrCU.resize(wfSize()); 12811308Santhony.gutierrez@amd.com 12911308Santhony.gutierrez@amd.com lds.setParent(this); 13011308Santhony.gutierrez@amd.com 13111308Santhony.gutierrez@amd.com if (p->execPolicy == "OLDEST-FIRST") { 13211308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::OLDEST; 13311308Santhony.gutierrez@amd.com } else if (p->execPolicy == "ROUND-ROBIN") { 13411308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::RR; 13511308Santhony.gutierrez@amd.com } else { 13611308Santhony.gutierrez@amd.com fatal("Invalid WF execution policy (CU)\n"); 13711308Santhony.gutierrez@amd.com } 13811308Santhony.gutierrez@amd.com 13911534Sjohn.kalamatianos@amd.com memPort.resize(wfSize()); 14011308Santhony.gutierrez@amd.com 14111308Santhony.gutierrez@amd.com // resize the tlbPort vectorArray 14211534Sjohn.kalamatianos@amd.com int tlbPort_width = perLaneTLB ? wfSize() : 1; 14311308Santhony.gutierrez@amd.com tlbPort.resize(tlbPort_width); 14411308Santhony.gutierrez@amd.com 14511308Santhony.gutierrez@amd.com cuExitCallback = new CUExitCallback(this); 14611308Santhony.gutierrez@amd.com registerExitCallback(cuExitCallback); 14711308Santhony.gutierrez@amd.com 14811308Santhony.gutierrez@amd.com xactCasLoadMap.clear(); 14911308Santhony.gutierrez@amd.com lastExecCycle.resize(numSIMDs, 0); 15011308Santhony.gutierrez@amd.com 15111308Santhony.gutierrez@amd.com for (int i = 0; i < vrf.size(); ++i) { 15211308Santhony.gutierrez@amd.com vrf[i]->setParent(this); 15311308Santhony.gutierrez@amd.com } 15411308Santhony.gutierrez@amd.com 15511308Santhony.gutierrez@amd.com numVecRegsPerSimd = vrf[0]->numRegs(); 15611308Santhony.gutierrez@amd.com} 15711308Santhony.gutierrez@amd.com 15811308Santhony.gutierrez@amd.comComputeUnit::~ComputeUnit() 15911308Santhony.gutierrez@amd.com{ 16011308Santhony.gutierrez@amd.com // Delete wavefront slots 16111534Sjohn.kalamatianos@amd.com for (int j = 0; j < numSIMDs; ++j) { 16211308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 16311308Santhony.gutierrez@amd.com delete wfList[j][i]; 16411308Santhony.gutierrez@amd.com } 16511534Sjohn.kalamatianos@amd.com lastVaddrSimd[j].clear(); 16611534Sjohn.kalamatianos@amd.com } 16711534Sjohn.kalamatianos@amd.com lastVaddrCU.clear(); 16811308Santhony.gutierrez@amd.com readyList.clear(); 16911308Santhony.gutierrez@amd.com waveStatusList.clear(); 17011308Santhony.gutierrez@amd.com dispatchList.clear(); 17111308Santhony.gutierrez@amd.com vectorAluInstAvail.clear(); 17211308Santhony.gutierrez@amd.com delete cuExitCallback; 17311308Santhony.gutierrez@amd.com delete ldsPort; 17411308Santhony.gutierrez@amd.com} 17511308Santhony.gutierrez@amd.com 17611308Santhony.gutierrez@amd.comvoid 17711308Santhony.gutierrez@amd.comComputeUnit::FillKernelState(Wavefront *w, NDRange *ndr) 17811308Santhony.gutierrez@amd.com{ 17911308Santhony.gutierrez@amd.com w->resizeRegFiles(ndr->q.cRegCount, ndr->q.sRegCount, ndr->q.dRegCount); 18011308Santhony.gutierrez@amd.com 18111639Salexandru.dutu@amd.com w->workGroupSz[0] = ndr->q.wgSize[0]; 18211639Salexandru.dutu@amd.com w->workGroupSz[1] = ndr->q.wgSize[1]; 18311639Salexandru.dutu@amd.com w->workGroupSz[2] = ndr->q.wgSize[2]; 18411639Salexandru.dutu@amd.com w->wgSz = w->workGroupSz[0] * w->workGroupSz[1] * w->workGroupSz[2]; 18511639Salexandru.dutu@amd.com w->gridSz[0] = ndr->q.gdSize[0]; 18611639Salexandru.dutu@amd.com w->gridSz[1] = ndr->q.gdSize[1]; 18711639Salexandru.dutu@amd.com w->gridSz[2] = ndr->q.gdSize[2]; 18811308Santhony.gutierrez@amd.com w->kernelArgs = ndr->q.args; 18911308Santhony.gutierrez@amd.com w->privSizePerItem = ndr->q.privMemPerItem; 19011308Santhony.gutierrez@amd.com w->spillSizePerItem = ndr->q.spillMemPerItem; 19111308Santhony.gutierrez@amd.com w->roBase = ndr->q.roMemStart; 19211308Santhony.gutierrez@amd.com w->roSize = ndr->q.roMemTotal; 19311308Santhony.gutierrez@amd.com} 19411308Santhony.gutierrez@amd.com 19511308Santhony.gutierrez@amd.comvoid 19611308Santhony.gutierrez@amd.comComputeUnit::updateEvents() { 19711308Santhony.gutierrez@amd.com 19811308Santhony.gutierrez@amd.com if (!timestampVec.empty()) { 19911308Santhony.gutierrez@amd.com uint32_t vecSize = timestampVec.size(); 20011308Santhony.gutierrez@amd.com uint32_t i = 0; 20111308Santhony.gutierrez@amd.com while (i < vecSize) { 20211308Santhony.gutierrez@amd.com if (timestampVec[i] <= shader->tick_cnt) { 20311308Santhony.gutierrez@amd.com std::pair<uint32_t, uint32_t> regInfo = regIdxVec[i]; 20411308Santhony.gutierrez@amd.com vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t), 20511308Santhony.gutierrez@amd.com statusVec[i]); 20611308Santhony.gutierrez@amd.com timestampVec.erase(timestampVec.begin() + i); 20711308Santhony.gutierrez@amd.com regIdxVec.erase(regIdxVec.begin() + i); 20811308Santhony.gutierrez@amd.com statusVec.erase(statusVec.begin() + i); 20911308Santhony.gutierrez@amd.com --vecSize; 21011308Santhony.gutierrez@amd.com --i; 21111308Santhony.gutierrez@amd.com } 21211308Santhony.gutierrez@amd.com ++i; 21311308Santhony.gutierrez@amd.com } 21411308Santhony.gutierrez@amd.com } 21511308Santhony.gutierrez@amd.com 21611308Santhony.gutierrez@amd.com for (int i = 0; i< numSIMDs; ++i) { 21711308Santhony.gutierrez@amd.com vrf[i]->updateEvents(); 21811308Santhony.gutierrez@amd.com } 21911308Santhony.gutierrez@amd.com} 22011308Santhony.gutierrez@amd.com 22111308Santhony.gutierrez@amd.com 22211308Santhony.gutierrez@amd.comvoid 22311638Salexandru.dutu@amd.comComputeUnit::StartWF(Wavefront *w, int trueWgSize[], int trueWgSizeTotal, 22411638Salexandru.dutu@amd.com int cnt, LdsChunk *ldsChunk, NDRange *ndr) 22511308Santhony.gutierrez@amd.com{ 22611308Santhony.gutierrez@amd.com static int _n_wave = 0; 22711308Santhony.gutierrez@amd.com 22811308Santhony.gutierrez@amd.com // Fill in Kernel state 22911308Santhony.gutierrez@amd.com FillKernelState(w, ndr); 23011308Santhony.gutierrez@amd.com 23111638Salexandru.dutu@amd.com VectorMask init_mask; 23211638Salexandru.dutu@amd.com init_mask.reset(); 23311638Salexandru.dutu@amd.com 23411638Salexandru.dutu@amd.com for (int k = 0; k < wfSize(); ++k) { 23511638Salexandru.dutu@amd.com if (k + cnt * wfSize() < trueWgSizeTotal) 23611638Salexandru.dutu@amd.com init_mask[k] = 1; 23711638Salexandru.dutu@amd.com } 23811638Salexandru.dutu@amd.com 23911639Salexandru.dutu@amd.com w->kernId = ndr->dispatchId; 24011639Salexandru.dutu@amd.com w->dynWaveId = cnt; 24111639Salexandru.dutu@amd.com w->initMask = init_mask.to_ullong(); 24211308Santhony.gutierrez@amd.com 24311534Sjohn.kalamatianos@amd.com for (int k = 0; k < wfSize(); ++k) { 24411639Salexandru.dutu@amd.com w->workItemId[0][k] = (k+cnt*wfSize()) % trueWgSize[0]; 24511639Salexandru.dutu@amd.com w->workItemId[1][k] = 24611534Sjohn.kalamatianos@amd.com ((k + cnt * wfSize()) / trueWgSize[0]) % trueWgSize[1]; 24711639Salexandru.dutu@amd.com w->workItemId[2][k] = 24811534Sjohn.kalamatianos@amd.com (k + cnt * wfSize()) / (trueWgSize[0] * trueWgSize[1]); 24911308Santhony.gutierrez@amd.com 25011639Salexandru.dutu@amd.com w->workItemFlatId[k] = w->workItemId[2][k] * trueWgSize[0] * 25111639Salexandru.dutu@amd.com trueWgSize[1] + w->workItemId[1][k] * trueWgSize[0] + 25211639Salexandru.dutu@amd.com w->workItemId[0][k]; 25311308Santhony.gutierrez@amd.com } 25411308Santhony.gutierrez@amd.com 25511639Salexandru.dutu@amd.com w->barrierSlots = divCeil(trueWgSizeTotal, wfSize()); 25611308Santhony.gutierrez@amd.com 25711639Salexandru.dutu@amd.com w->barCnt.resize(wfSize(), 0); 25811308Santhony.gutierrez@amd.com 25911639Salexandru.dutu@amd.com w->maxBarCnt = 0; 26011639Salexandru.dutu@amd.com w->oldBarrierCnt = 0; 26111639Salexandru.dutu@amd.com w->barrierCnt = 0; 26211308Santhony.gutierrez@amd.com 26311638Salexandru.dutu@amd.com w->privBase = ndr->q.privMemStart; 26411638Salexandru.dutu@amd.com ndr->q.privMemStart += ndr->q.privMemPerItem * wfSize(); 26511638Salexandru.dutu@amd.com 26611638Salexandru.dutu@amd.com w->spillBase = ndr->q.spillMemStart; 26711638Salexandru.dutu@amd.com ndr->q.spillMemStart += ndr->q.spillMemPerItem * wfSize(); 26811638Salexandru.dutu@amd.com 26911638Salexandru.dutu@amd.com w->pushToReconvergenceStack(0, UINT32_MAX, init_mask.to_ulong()); 27011308Santhony.gutierrez@amd.com 27111308Santhony.gutierrez@amd.com // WG state 27211639Salexandru.dutu@amd.com w->wgId = ndr->globalWgId; 27311639Salexandru.dutu@amd.com w->dispatchId = ndr->dispatchId; 27411639Salexandru.dutu@amd.com w->workGroupId[0] = w->wgId % ndr->numWg[0]; 27511639Salexandru.dutu@amd.com w->workGroupId[1] = (w->wgId / ndr->numWg[0]) % ndr->numWg[1]; 27611639Salexandru.dutu@amd.com w->workGroupId[2] = w->wgId / (ndr->numWg[0] * ndr->numWg[1]); 27711308Santhony.gutierrez@amd.com 27811639Salexandru.dutu@amd.com w->barrierId = barrier_id; 27911308Santhony.gutierrez@amd.com w->stalledAtBarrier = false; 28011308Santhony.gutierrez@amd.com 28111638Salexandru.dutu@amd.com // set the wavefront context to have a pointer to this section of the LDS 28211638Salexandru.dutu@amd.com w->ldsChunk = ldsChunk; 28311308Santhony.gutierrez@amd.com 28411308Santhony.gutierrez@amd.com int32_t refCount M5_VAR_USED = 28511639Salexandru.dutu@amd.com lds.increaseRefCounter(w->dispatchId, w->wgId); 28611308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: increase ref ctr wg[%d] to [%d]\n", 28711639Salexandru.dutu@amd.com cu_id, w->wgId, refCount); 28811308Santhony.gutierrez@amd.com 28911308Santhony.gutierrez@amd.com w->instructionBuffer.clear(); 29011308Santhony.gutierrez@amd.com 29111308Santhony.gutierrez@amd.com if (w->pendingFetch) 29211308Santhony.gutierrez@amd.com w->dropFetch = true; 29311308Santhony.gutierrez@amd.com 29411308Santhony.gutierrez@amd.com // is this the last wavefront in the workgroup 29511308Santhony.gutierrez@amd.com // if set the spillWidth to be the remaining work-items 29611308Santhony.gutierrez@amd.com // so that the vector access is correct 29711534Sjohn.kalamatianos@amd.com if ((cnt + 1) * wfSize() >= trueWgSizeTotal) { 29811534Sjohn.kalamatianos@amd.com w->spillWidth = trueWgSizeTotal - (cnt * wfSize()); 29911308Santhony.gutierrez@amd.com } else { 30011534Sjohn.kalamatianos@amd.com w->spillWidth = wfSize(); 30111308Santhony.gutierrez@amd.com } 30211308Santhony.gutierrez@amd.com 30311308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Scheduling wfDynId/barrier_id %d/%d on CU%d: " 30411308Santhony.gutierrez@amd.com "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId); 30511308Santhony.gutierrez@amd.com 30611308Santhony.gutierrez@amd.com w->start(++_n_wave, ndr->q.code_ptr); 30711308Santhony.gutierrez@amd.com} 30811308Santhony.gutierrez@amd.com 30911308Santhony.gutierrez@amd.comvoid 31011308Santhony.gutierrez@amd.comComputeUnit::StartWorkgroup(NDRange *ndr) 31111308Santhony.gutierrez@amd.com{ 31211308Santhony.gutierrez@amd.com // reserve the LDS capacity allocated to the work group 31311308Santhony.gutierrez@amd.com // disambiguated by the dispatch ID and workgroup ID, which should be 31411308Santhony.gutierrez@amd.com // globally unique 31511308Santhony.gutierrez@amd.com LdsChunk *ldsChunk = lds.reserveSpace(ndr->dispatchId, ndr->globalWgId, 31611308Santhony.gutierrez@amd.com ndr->q.ldsSize); 31711308Santhony.gutierrez@amd.com 31811308Santhony.gutierrez@amd.com // Send L1 cache acquire 31911308Santhony.gutierrez@amd.com // isKernel + isAcquire = Kernel Begin 32011308Santhony.gutierrez@amd.com if (shader->impl_kern_boundary_sync) { 32111534Sjohn.kalamatianos@amd.com GPUDynInstPtr gpuDynInst = std::make_shared<GPUDynInst>(this, 32211308Santhony.gutierrez@amd.com nullptr, 32311308Santhony.gutierrez@amd.com nullptr, 0); 32411308Santhony.gutierrez@amd.com 32511308Santhony.gutierrez@amd.com gpuDynInst->useContinuation = false; 32611308Santhony.gutierrez@amd.com gpuDynInst->memoryOrder = Enums::MEMORY_ORDER_SC_ACQUIRE; 32711308Santhony.gutierrez@amd.com gpuDynInst->scope = Enums::MEMORY_SCOPE_SYSTEM; 32811308Santhony.gutierrez@amd.com injectGlobalMemFence(gpuDynInst, true); 32911308Santhony.gutierrez@amd.com } 33011308Santhony.gutierrez@amd.com 33111308Santhony.gutierrez@amd.com // Get true size of workgroup (after clamping to grid size) 33211308Santhony.gutierrez@amd.com int trueWgSize[3]; 33311308Santhony.gutierrez@amd.com int trueWgSizeTotal = 1; 33411308Santhony.gutierrez@amd.com 33511308Santhony.gutierrez@amd.com for (int d = 0; d < 3; ++d) { 33611308Santhony.gutierrez@amd.com trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] - 33711308Santhony.gutierrez@amd.com ndr->wgId[d] * ndr->q.wgSize[d]); 33811308Santhony.gutierrez@amd.com 33911308Santhony.gutierrez@amd.com trueWgSizeTotal *= trueWgSize[d]; 34011308Santhony.gutierrez@amd.com } 34111308Santhony.gutierrez@amd.com 34211308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by wavefront 34311308Santhony.gutierrez@amd.com int vregDemand = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 34411308Santhony.gutierrez@amd.com int cnt = 0; 34511308Santhony.gutierrez@amd.com 34611308Santhony.gutierrez@amd.com // Assign WFs by spreading them across SIMDs, 1 WF per SIMD at a time 34711308Santhony.gutierrez@amd.com for (int m = 0; m < shader->n_wf * numSIMDs; ++m) { 34811308Santhony.gutierrez@amd.com Wavefront *w = wfList[m % numSIMDs][m / numSIMDs]; 34911308Santhony.gutierrez@amd.com // Check if this wavefront slot is available: 35011308Santhony.gutierrez@amd.com // It must be stopped and not waiting 35111308Santhony.gutierrez@amd.com // for a release to complete S_RETURNING 35211308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_STOPPED) { 35311308Santhony.gutierrez@amd.com // if we have scheduled all work items then stop 35411308Santhony.gutierrez@amd.com // scheduling wavefronts 35511534Sjohn.kalamatianos@amd.com if (cnt * wfSize() >= trueWgSizeTotal) 35611308Santhony.gutierrez@amd.com break; 35711308Santhony.gutierrez@amd.com 35811308Santhony.gutierrez@amd.com // reserve vector registers for the scheduled wavefront 35911308Santhony.gutierrez@amd.com assert(vectorRegsReserved[m % numSIMDs] <= numVecRegsPerSimd); 36011308Santhony.gutierrez@amd.com uint32_t normSize = 0; 36111308Santhony.gutierrez@amd.com 36211308Santhony.gutierrez@amd.com w->startVgprIndex = vrf[m % numSIMDs]->manager-> 36311308Santhony.gutierrez@amd.com allocateRegion(vregDemand, &normSize); 36411308Santhony.gutierrez@amd.com 36511308Santhony.gutierrez@amd.com w->reservedVectorRegs = normSize; 36611308Santhony.gutierrez@amd.com vectorRegsReserved[m % numSIMDs] += w->reservedVectorRegs; 36711308Santhony.gutierrez@amd.com 36811638Salexandru.dutu@amd.com StartWF(w, trueWgSize, trueWgSizeTotal, cnt, ldsChunk, ndr); 36911308Santhony.gutierrez@amd.com ++cnt; 37011308Santhony.gutierrez@amd.com } 37111308Santhony.gutierrez@amd.com } 37211308Santhony.gutierrez@amd.com ++barrier_id; 37311308Santhony.gutierrez@amd.com} 37411308Santhony.gutierrez@amd.com 37511308Santhony.gutierrez@amd.comint 37611308Santhony.gutierrez@amd.comComputeUnit::ReadyWorkgroup(NDRange *ndr) 37711308Santhony.gutierrez@amd.com{ 37811308Santhony.gutierrez@amd.com // Get true size of workgroup (after clamping to grid size) 37911308Santhony.gutierrez@amd.com int trueWgSize[3]; 38011308Santhony.gutierrez@amd.com int trueWgSizeTotal = 1; 38111308Santhony.gutierrez@amd.com 38211308Santhony.gutierrez@amd.com for (int d = 0; d < 3; ++d) { 38311308Santhony.gutierrez@amd.com trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] - 38411308Santhony.gutierrez@amd.com ndr->wgId[d] * ndr->q.wgSize[d]); 38511308Santhony.gutierrez@amd.com 38611308Santhony.gutierrez@amd.com trueWgSizeTotal *= trueWgSize[d]; 38711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSize[%d] = %d\n", d, trueWgSize[d]); 38811308Santhony.gutierrez@amd.com } 38911308Santhony.gutierrez@amd.com 39011308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSizeTotal = %d\n", trueWgSizeTotal); 39111308Santhony.gutierrez@amd.com 39211308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by each 39311308Santhony.gutierrez@amd.com // work item of the work group 39411308Santhony.gutierrez@amd.com int vregDemandPerWI = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 39511308Santhony.gutierrez@amd.com bool vregAvail = true; 39611534Sjohn.kalamatianos@amd.com int numWfs = (trueWgSizeTotal + wfSize() - 1) / wfSize(); 39711308Santhony.gutierrez@amd.com int freeWfSlots = 0; 39811308Santhony.gutierrez@amd.com // check if the total number of VGPRs required by all WFs of the WG 39911308Santhony.gutierrez@amd.com // fit in the VRFs of all SIMD units 40011308Santhony.gutierrez@amd.com assert((numWfs * vregDemandPerWI) <= (numSIMDs * numVecRegsPerSimd)); 40111308Santhony.gutierrez@amd.com int numMappedWfs = 0; 40211308Santhony.gutierrez@amd.com std::vector<int> numWfsPerSimd; 40311308Santhony.gutierrez@amd.com numWfsPerSimd.resize(numSIMDs, 0); 40411308Santhony.gutierrez@amd.com // find how many free WF slots we have across all SIMDs 40511308Santhony.gutierrez@amd.com for (int j = 0; j < shader->n_wf; ++j) { 40611308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 40711308Santhony.gutierrez@amd.com if (wfList[i][j]->status == Wavefront::S_STOPPED) { 40811308Santhony.gutierrez@amd.com // count the number of free WF slots 40911308Santhony.gutierrez@amd.com ++freeWfSlots; 41011308Santhony.gutierrez@amd.com if (numMappedWfs < numWfs) { 41111308Santhony.gutierrez@amd.com // count the WFs to be assigned per SIMD 41211308Santhony.gutierrez@amd.com numWfsPerSimd[i]++; 41311308Santhony.gutierrez@amd.com } 41411308Santhony.gutierrez@amd.com numMappedWfs++; 41511308Santhony.gutierrez@amd.com } 41611308Santhony.gutierrez@amd.com } 41711308Santhony.gutierrez@amd.com } 41811308Santhony.gutierrez@amd.com 41911308Santhony.gutierrez@amd.com // if there are enough free WF slots then find if there are enough 42011308Santhony.gutierrez@amd.com // free VGPRs per SIMD based on the WF->SIMD mapping 42111308Santhony.gutierrez@amd.com if (freeWfSlots >= numWfs) { 42211308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 42311308Santhony.gutierrez@amd.com // find if there are enough free VGPR regions in the SIMD's VRF 42411308Santhony.gutierrez@amd.com // to accommodate the WFs of the new WG that would be mapped to 42511308Santhony.gutierrez@amd.com // this SIMD unit 42611308Santhony.gutierrez@amd.com vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j], 42711308Santhony.gutierrez@amd.com vregDemandPerWI); 42811308Santhony.gutierrez@amd.com 42911308Santhony.gutierrez@amd.com // stop searching if there is at least one SIMD 43011308Santhony.gutierrez@amd.com // whose VRF does not have enough free VGPR pools. 43111308Santhony.gutierrez@amd.com // This is because a WG is scheduled only if ALL 43211308Santhony.gutierrez@amd.com // of its WFs can be scheduled 43311308Santhony.gutierrez@amd.com if (!vregAvail) 43411308Santhony.gutierrez@amd.com break; 43511308Santhony.gutierrez@amd.com } 43611308Santhony.gutierrez@amd.com } 43711308Santhony.gutierrez@amd.com 43811308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Free WF slots = %d, VGPR Availability = %d\n", 43911308Santhony.gutierrez@amd.com freeWfSlots, vregAvail); 44011308Santhony.gutierrez@amd.com 44111308Santhony.gutierrez@amd.com if (!vregAvail) { 44211308Santhony.gutierrez@amd.com ++numTimesWgBlockedDueVgprAlloc; 44311308Santhony.gutierrez@amd.com } 44411308Santhony.gutierrez@amd.com 44511308Santhony.gutierrez@amd.com // Return true if enough WF slots to submit workgroup and if there are 44611308Santhony.gutierrez@amd.com // enough VGPRs to schedule all WFs to their SIMD units 44711308Santhony.gutierrez@amd.com if (!lds.canReserve(ndr->q.ldsSize)) { 44811308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation++; 44911308Santhony.gutierrez@amd.com } 45011308Santhony.gutierrez@amd.com 45111308Santhony.gutierrez@amd.com // Return true if (a) there are enough free WF slots to submit 45211308Santhony.gutierrez@amd.com // workgrounp and (b) if there are enough VGPRs to schedule all WFs to their 45311308Santhony.gutierrez@amd.com // SIMD units and (c) if there is enough space in LDS 45411308Santhony.gutierrez@amd.com return freeWfSlots >= numWfs && vregAvail && lds.canReserve(ndr->q.ldsSize); 45511308Santhony.gutierrez@amd.com} 45611308Santhony.gutierrez@amd.com 45711308Santhony.gutierrez@amd.comint 45811308Santhony.gutierrez@amd.comComputeUnit::AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots) 45911308Santhony.gutierrez@amd.com{ 46011308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id); 46111308Santhony.gutierrez@amd.com int ccnt = 0; 46211308Santhony.gutierrez@amd.com 46311308Santhony.gutierrez@amd.com for (int i_simd = 0; i_simd < numSIMDs; ++i_simd) { 46411308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf) { 46511308Santhony.gutierrez@amd.com Wavefront *w = wfList[i_simd][i_wf]; 46611308Santhony.gutierrez@amd.com 46711308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING) { 46811308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "Checking WF[%d][%d]\n", i_simd, i_wf); 46911308Santhony.gutierrez@amd.com 47011308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_id = %d, _barrier_id = %d\n", 47111639Salexandru.dutu@amd.com w->barrierId, _barrier_id); 47211308Santhony.gutierrez@amd.com 47311308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_cnt %d, bcnt = %d\n", 47411639Salexandru.dutu@amd.com w->barrierCnt, bcnt); 47511308Santhony.gutierrez@amd.com } 47611308Santhony.gutierrez@amd.com 47711308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING && 47811639Salexandru.dutu@amd.com w->barrierId == _barrier_id && w->barrierCnt == bcnt && 47911639Salexandru.dutu@amd.com !w->outstandingReqs) { 48011308Santhony.gutierrez@amd.com ++ccnt; 48111308Santhony.gutierrez@amd.com 48211308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "WF[%d][%d] at barrier, increment ccnt to " 48311308Santhony.gutierrez@amd.com "%d\n", i_simd, i_wf, ccnt); 48411308Santhony.gutierrez@amd.com } 48511308Santhony.gutierrez@amd.com } 48611308Santhony.gutierrez@amd.com } 48711308Santhony.gutierrez@amd.com 48811308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: returning allAtBarrier ccnt = %d, bslots = %d\n", 48911308Santhony.gutierrez@amd.com cu_id, ccnt, bslots); 49011308Santhony.gutierrez@amd.com 49111308Santhony.gutierrez@amd.com return ccnt == bslots; 49211308Santhony.gutierrez@amd.com} 49311308Santhony.gutierrez@amd.com 49411308Santhony.gutierrez@amd.com// Check if the current wavefront is blocked on additional resources. 49511308Santhony.gutierrez@amd.combool 49611308Santhony.gutierrez@amd.comComputeUnit::cedeSIMD(int simdId, int wfSlotId) 49711308Santhony.gutierrez@amd.com{ 49811308Santhony.gutierrez@amd.com bool cede = false; 49911308Santhony.gutierrez@amd.com 50011308Santhony.gutierrez@amd.com // If --xact-cas-mode option is enabled in run.py, then xact_cas_ld 50111308Santhony.gutierrez@amd.com // magic instructions will impact the scheduling of wavefronts 50211308Santhony.gutierrez@amd.com if (xact_cas_mode) { 50311308Santhony.gutierrez@amd.com /* 50411308Santhony.gutierrez@amd.com * When a wavefront calls xact_cas_ld, it adds itself to a per address 50511308Santhony.gutierrez@amd.com * queue. All per address queues are managed by the xactCasLoadMap. 50611308Santhony.gutierrez@amd.com * 50711308Santhony.gutierrez@amd.com * A wavefront is not blocked if: it is not in ANY per address queue or 50811308Santhony.gutierrez@amd.com * if it is at the head of a per address queue. 50911308Santhony.gutierrez@amd.com */ 51011308Santhony.gutierrez@amd.com for (auto itMap : xactCasLoadMap) { 51111308Santhony.gutierrez@amd.com std::list<waveIdentifier> curWaveIDQueue = itMap.second.waveIDQueue; 51211308Santhony.gutierrez@amd.com 51311308Santhony.gutierrez@amd.com if (!curWaveIDQueue.empty()) { 51411308Santhony.gutierrez@amd.com for (auto it : curWaveIDQueue) { 51511308Santhony.gutierrez@amd.com waveIdentifier cur_wave = it; 51611308Santhony.gutierrez@amd.com 51711308Santhony.gutierrez@amd.com if (cur_wave.simdId == simdId && 51811308Santhony.gutierrez@amd.com cur_wave.wfSlotId == wfSlotId) { 51911308Santhony.gutierrez@amd.com // 2 possibilities 52011308Santhony.gutierrez@amd.com // 1: this WF has a green light 52111308Santhony.gutierrez@amd.com // 2: another WF has a green light 52211308Santhony.gutierrez@amd.com waveIdentifier owner_wave = curWaveIDQueue.front(); 52311308Santhony.gutierrez@amd.com 52411308Santhony.gutierrez@amd.com if (owner_wave.simdId != cur_wave.simdId || 52511308Santhony.gutierrez@amd.com owner_wave.wfSlotId != cur_wave.wfSlotId) { 52611308Santhony.gutierrez@amd.com // possibility 2 52711308Santhony.gutierrez@amd.com cede = true; 52811308Santhony.gutierrez@amd.com break; 52911308Santhony.gutierrez@amd.com } else { 53011308Santhony.gutierrez@amd.com // possibility 1 53111308Santhony.gutierrez@amd.com break; 53211308Santhony.gutierrez@amd.com } 53311308Santhony.gutierrez@amd.com } 53411308Santhony.gutierrez@amd.com } 53511308Santhony.gutierrez@amd.com } 53611308Santhony.gutierrez@amd.com } 53711308Santhony.gutierrez@amd.com } 53811308Santhony.gutierrez@amd.com 53911308Santhony.gutierrez@amd.com return cede; 54011308Santhony.gutierrez@amd.com} 54111308Santhony.gutierrez@amd.com 54211308Santhony.gutierrez@amd.com// Execute one clock worth of work on the ComputeUnit. 54311308Santhony.gutierrez@amd.comvoid 54411308Santhony.gutierrez@amd.comComputeUnit::exec() 54511308Santhony.gutierrez@amd.com{ 54611308Santhony.gutierrez@amd.com updateEvents(); 54711308Santhony.gutierrez@amd.com // Execute pipeline stages in reverse order to simulate 54811308Santhony.gutierrez@amd.com // the pipeline latency 54911308Santhony.gutierrez@amd.com globalMemoryPipe.exec(); 55011308Santhony.gutierrez@amd.com localMemoryPipe.exec(); 55111308Santhony.gutierrez@amd.com execStage.exec(); 55211308Santhony.gutierrez@amd.com scheduleStage.exec(); 55311308Santhony.gutierrez@amd.com scoreboardCheckStage.exec(); 55411308Santhony.gutierrez@amd.com fetchStage.exec(); 55511308Santhony.gutierrez@amd.com 55611308Santhony.gutierrez@amd.com totalCycles++; 55711308Santhony.gutierrez@amd.com} 55811308Santhony.gutierrez@amd.com 55911308Santhony.gutierrez@amd.comvoid 56011308Santhony.gutierrez@amd.comComputeUnit::init() 56111308Santhony.gutierrez@amd.com{ 56211308Santhony.gutierrez@amd.com // Initialize CU Bus models 56311345Sjohn.kalamatianos@amd.com glbMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 56411345Sjohn.kalamatianos@amd.com locMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 56511308Santhony.gutierrez@amd.com nextGlbMemBus = 0; 56611308Santhony.gutierrez@amd.com nextLocMemBus = 0; 56711308Santhony.gutierrez@amd.com fatal_if(numGlbMemUnits > 1, 56811308Santhony.gutierrez@amd.com "No support for multiple Global Memory Pipelines exists!!!"); 56911308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus.resize(numGlbMemUnits); 57011308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 57111308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus[j] = WaitClass(); 57211345Sjohn.kalamatianos@amd.com vrfToGlobalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 57311308Santhony.gutierrez@amd.com } 57411308Santhony.gutierrez@amd.com 57511308Santhony.gutierrez@amd.com fatal_if(numLocMemUnits > 1, 57611308Santhony.gutierrez@amd.com "No support for multiple Local Memory Pipelines exists!!!"); 57711308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus.resize(numLocMemUnits); 57811308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 57911308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus[j] = WaitClass(); 58011345Sjohn.kalamatianos@amd.com vrfToLocalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 58111308Santhony.gutierrez@amd.com } 58211308Santhony.gutierrez@amd.com vectorRegsReserved.resize(numSIMDs, 0); 58311308Santhony.gutierrez@amd.com aluPipe.resize(numSIMDs); 58411308Santhony.gutierrez@amd.com wfWait.resize(numSIMDs + numLocMemUnits + numGlbMemUnits); 58511308Santhony.gutierrez@amd.com 58611308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs + numLocMemUnits + numGlbMemUnits; ++i) { 58711308Santhony.gutierrez@amd.com wfWait[i] = WaitClass(); 58811345Sjohn.kalamatianos@amd.com wfWait[i].init(&shader->tick_cnt, shader->ticks(1)); 58911308Santhony.gutierrez@amd.com } 59011308Santhony.gutierrez@amd.com 59111308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 59211308Santhony.gutierrez@amd.com aluPipe[i] = WaitClass(); 59311345Sjohn.kalamatianos@amd.com aluPipe[i].init(&shader->tick_cnt, shader->ticks(1)); 59411308Santhony.gutierrez@amd.com } 59511308Santhony.gutierrez@amd.com 59611308Santhony.gutierrez@amd.com // Setup space for call args 59711308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 59811308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 59911534Sjohn.kalamatianos@amd.com wfList[j][i]->initCallArgMem(shader->funcargs_size, wavefrontSize); 60011308Santhony.gutierrez@amd.com } 60111308Santhony.gutierrez@amd.com } 60211308Santhony.gutierrez@amd.com 60311308Santhony.gutierrez@amd.com // Initializing pipeline resources 60411308Santhony.gutierrez@amd.com readyList.resize(numSIMDs + numGlbMemUnits + numLocMemUnits); 60511308Santhony.gutierrez@amd.com waveStatusList.resize(numSIMDs); 60611308Santhony.gutierrez@amd.com 60711308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 60811308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 60911308Santhony.gutierrez@amd.com waveStatusList[j].push_back( 61011308Santhony.gutierrez@amd.com std::make_pair(wfList[j][i], BLOCKED)); 61111308Santhony.gutierrez@amd.com } 61211308Santhony.gutierrez@amd.com } 61311308Santhony.gutierrez@amd.com 61411308Santhony.gutierrez@amd.com for (int j = 0; j < (numSIMDs + numGlbMemUnits + numLocMemUnits); ++j) { 61511308Santhony.gutierrez@amd.com dispatchList.push_back(std::make_pair((Wavefront*)nullptr, EMPTY)); 61611308Santhony.gutierrez@amd.com } 61711308Santhony.gutierrez@amd.com 61811308Santhony.gutierrez@amd.com fetchStage.init(this); 61911308Santhony.gutierrez@amd.com scoreboardCheckStage.init(this); 62011308Santhony.gutierrez@amd.com scheduleStage.init(this); 62111308Santhony.gutierrez@amd.com execStage.init(this); 62211308Santhony.gutierrez@amd.com globalMemoryPipe.init(this); 62311308Santhony.gutierrez@amd.com localMemoryPipe.init(this); 62411308Santhony.gutierrez@amd.com // initialize state for statistics calculation 62511308Santhony.gutierrez@amd.com vectorAluInstAvail.resize(numSIMDs, false); 62611308Santhony.gutierrez@amd.com shrMemInstAvail = 0; 62711308Santhony.gutierrez@amd.com glbMemInstAvail = 0; 62811308Santhony.gutierrez@amd.com} 62911308Santhony.gutierrez@amd.com 63011308Santhony.gutierrez@amd.combool 63111308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvTimingResp(PacketPtr pkt) 63211308Santhony.gutierrez@amd.com{ 63311308Santhony.gutierrez@amd.com // Ruby has completed the memory op. Schedule the mem_resp_event at the 63411308Santhony.gutierrez@amd.com // appropriate cycle to process the timing memory response 63511308Santhony.gutierrez@amd.com // This delay represents the pipeline delay 63611308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 63711308Santhony.gutierrez@amd.com int index = sender_state->port_index; 63811308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 63911308Santhony.gutierrez@amd.com 64011308Santhony.gutierrez@amd.com // Is the packet returned a Kernel End or Barrier 64111308Santhony.gutierrez@amd.com if (pkt->req->isKernel() && pkt->req->isRelease()) { 64211308Santhony.gutierrez@amd.com Wavefront *w = 64311308Santhony.gutierrez@amd.com computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId]; 64411308Santhony.gutierrez@amd.com 64511308Santhony.gutierrez@amd.com // Check if we are waiting on Kernel End Release 64611308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RETURNING) { 64711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: WF[%d][%d][wv=%d]: WG id completed %d\n", 64811308Santhony.gutierrez@amd.com computeUnit->cu_id, w->simdId, w->wfSlotId, 64911639Salexandru.dutu@amd.com w->wfDynId, w->kernId); 65011308Santhony.gutierrez@amd.com 65111308Santhony.gutierrez@amd.com computeUnit->shader->dispatcher->notifyWgCompl(w); 65211308Santhony.gutierrez@amd.com w->status = Wavefront::S_STOPPED; 65311308Santhony.gutierrez@amd.com } else { 65411639Salexandru.dutu@amd.com w->outstandingReqs--; 65511308Santhony.gutierrez@amd.com } 65611308Santhony.gutierrez@amd.com 65711308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: WF[%d][%d]: barrier_cnt = %d\n", 65811308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 65911639Salexandru.dutu@amd.com gpuDynInst->wfSlotId, w->barrierCnt); 66011308Santhony.gutierrez@amd.com 66111308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 66211308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 66311308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 66411308Santhony.gutierrez@amd.com gpuDynInst); 66511308Santhony.gutierrez@amd.com } 66611308Santhony.gutierrez@amd.com 66711308Santhony.gutierrez@amd.com delete pkt->senderState; 66811308Santhony.gutierrez@amd.com delete pkt->req; 66911308Santhony.gutierrez@amd.com delete pkt; 67011308Santhony.gutierrez@amd.com return true; 67111308Santhony.gutierrez@amd.com } else if (pkt->req->isKernel() && pkt->req->isAcquire()) { 67211308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 67311308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 67411308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 67511308Santhony.gutierrez@amd.com gpuDynInst); 67611308Santhony.gutierrez@amd.com } 67711308Santhony.gutierrez@amd.com 67811308Santhony.gutierrez@amd.com delete pkt->senderState; 67911308Santhony.gutierrez@amd.com delete pkt->req; 68011308Santhony.gutierrez@amd.com delete pkt; 68111308Santhony.gutierrez@amd.com return true; 68211308Santhony.gutierrez@amd.com } 68311308Santhony.gutierrez@amd.com 68411308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemRespEvent *mem_resp_event = 68511308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemRespEvent(computeUnit->memPort[index], 68611308Santhony.gutierrez@amd.com pkt); 68711308Santhony.gutierrez@amd.com 68811308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n", 68911308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 69011308Santhony.gutierrez@amd.com index, pkt->req->getPaddr()); 69111308Santhony.gutierrez@amd.com 69211308Santhony.gutierrez@amd.com computeUnit->schedule(mem_resp_event, 69311308Santhony.gutierrez@amd.com curTick() + computeUnit->resp_tick_latency); 69411308Santhony.gutierrez@amd.com return true; 69511308Santhony.gutierrez@amd.com} 69611308Santhony.gutierrez@amd.com 69711308Santhony.gutierrez@amd.comvoid 69811308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvReqRetry() 69911308Santhony.gutierrez@amd.com{ 70011308Santhony.gutierrez@amd.com int len = retries.size(); 70111308Santhony.gutierrez@amd.com 70211308Santhony.gutierrez@amd.com assert(len > 0); 70311308Santhony.gutierrez@amd.com 70411308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 70511308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 70611308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second; 70711308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n", 70811308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 70911308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 71011308Santhony.gutierrez@amd.com 71111308Santhony.gutierrez@amd.com /** Currently Ruby can return false due to conflicts for the particular 71211308Santhony.gutierrez@amd.com * cache block or address. Thus other requests should be allowed to 71311308Santhony.gutierrez@amd.com * pass and the data port should expect multiple retries. */ 71411308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 71511308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "failed again!\n"); 71611308Santhony.gutierrez@amd.com break; 71711308Santhony.gutierrez@amd.com } else { 71811308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "successful!\n"); 71911308Santhony.gutierrez@amd.com retries.pop_front(); 72011308Santhony.gutierrez@amd.com } 72111308Santhony.gutierrez@amd.com } 72211308Santhony.gutierrez@amd.com} 72311308Santhony.gutierrez@amd.com 72411308Santhony.gutierrez@amd.combool 72511308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt) 72611308Santhony.gutierrez@amd.com{ 72711308Santhony.gutierrez@amd.com computeUnit->fetchStage.processFetchReturn(pkt); 72811308Santhony.gutierrez@amd.com 72911308Santhony.gutierrez@amd.com return true; 73011308Santhony.gutierrez@amd.com} 73111308Santhony.gutierrez@amd.com 73211308Santhony.gutierrez@amd.comvoid 73311308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvReqRetry() 73411308Santhony.gutierrez@amd.com{ 73511308Santhony.gutierrez@amd.com int len = retries.size(); 73611308Santhony.gutierrez@amd.com 73711308Santhony.gutierrez@amd.com assert(len > 0); 73811308Santhony.gutierrez@amd.com 73911308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 74011308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 74111308Santhony.gutierrez@amd.com Wavefront *wavefront M5_VAR_USED = retries.front().second; 74211308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n", 74311308Santhony.gutierrez@amd.com computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, 74411308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 74511308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 74611308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "failed again!\n"); 74711308Santhony.gutierrez@amd.com break; 74811308Santhony.gutierrez@amd.com } else { 74911308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "successful!\n"); 75011308Santhony.gutierrez@amd.com retries.pop_front(); 75111308Santhony.gutierrez@amd.com } 75211308Santhony.gutierrez@amd.com } 75311308Santhony.gutierrez@amd.com} 75411308Santhony.gutierrez@amd.com 75511308Santhony.gutierrez@amd.comvoid 75611308Santhony.gutierrez@amd.comComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 75711308Santhony.gutierrez@amd.com{ 75811308Santhony.gutierrez@amd.com // There must be a way around this check to do the globalMemStart... 75911308Santhony.gutierrez@amd.com Addr tmp_vaddr = pkt->req->getVaddr(); 76011308Santhony.gutierrez@amd.com 76111308Santhony.gutierrez@amd.com updatePageDivergenceDist(tmp_vaddr); 76211308Santhony.gutierrez@amd.com 76311308Santhony.gutierrez@amd.com pkt->req->setVirt(pkt->req->getAsid(), tmp_vaddr, pkt->req->getSize(), 76411308Santhony.gutierrez@amd.com pkt->req->getFlags(), pkt->req->masterId(), 76511308Santhony.gutierrez@amd.com pkt->req->getPC()); 76611308Santhony.gutierrez@amd.com 76711308Santhony.gutierrez@amd.com // figure out the type of the request to set read/write 76811308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode; 76911308Santhony.gutierrez@amd.com assert(pkt->isRead() || pkt->isWrite()); 77011308Santhony.gutierrez@amd.com 77111308Santhony.gutierrez@amd.com // Check write before read for atomic operations 77211308Santhony.gutierrez@amd.com // since atomic operations should use BaseTLB::Write 77311308Santhony.gutierrez@amd.com if (pkt->isWrite()){ 77411308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Write; 77511308Santhony.gutierrez@amd.com } else if (pkt->isRead()) { 77611308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Read; 77711308Santhony.gutierrez@amd.com } else { 77811308Santhony.gutierrez@amd.com fatal("pkt is not a read nor a write\n"); 77911308Santhony.gutierrez@amd.com } 78011308Santhony.gutierrez@amd.com 78111308Santhony.gutierrez@amd.com tlbCycles -= curTick(); 78211308Santhony.gutierrez@amd.com ++tlbRequests; 78311308Santhony.gutierrez@amd.com 78411308Santhony.gutierrez@amd.com int tlbPort_index = perLaneTLB ? index : 0; 78511308Santhony.gutierrez@amd.com 78611308Santhony.gutierrez@amd.com if (shader->timingSim) { 78711308Santhony.gutierrez@amd.com if (debugSegFault) { 78811308Santhony.gutierrez@amd.com Process *p = shader->gpuTc->getProcessPtr(); 78911308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 79011308Santhony.gutierrez@amd.com unsigned size = pkt->getSize(); 79111308Santhony.gutierrez@amd.com 79211308Santhony.gutierrez@amd.com if ((vaddr + size - 1) % 64 < vaddr % 64) { 79311308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Access to addr %#x is unaligned!\n", 79411308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr); 79511308Santhony.gutierrez@amd.com } 79611308Santhony.gutierrez@amd.com 79711308Santhony.gutierrez@amd.com Addr paddr; 79811308Santhony.gutierrez@amd.com 79911308Santhony.gutierrez@amd.com if (!p->pTable->translate(vaddr, paddr)) { 80011308Santhony.gutierrez@amd.com if (!p->fixupStackFault(vaddr)) { 80111308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Fault on addr %#x!\n", 80211308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 80311308Santhony.gutierrez@amd.com vaddr); 80411308Santhony.gutierrez@amd.com } 80511308Santhony.gutierrez@amd.com } 80611308Santhony.gutierrez@amd.com } 80711308Santhony.gutierrez@amd.com 80811308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 80911308Santhony.gutierrez@amd.com pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index); 81011308Santhony.gutierrez@amd.com 81111308Santhony.gutierrez@amd.com // This is the senderState needed by the TLB hierarchy to function 81211308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 81311308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false, 81411308Santhony.gutierrez@amd.com pkt->senderState); 81511308Santhony.gutierrez@amd.com 81611308Santhony.gutierrez@amd.com pkt->senderState = translation_state; 81711308Santhony.gutierrez@amd.com 81811308Santhony.gutierrez@amd.com if (functionalTLB) { 81911308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 82011308Santhony.gutierrez@amd.com 82111308Santhony.gutierrez@amd.com // update the hitLevel distribution 82211308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 82311308Santhony.gutierrez@amd.com assert(hit_level != -1); 82411308Santhony.gutierrez@amd.com hitsPerTLBLevel[hit_level]++; 82511308Santhony.gutierrez@amd.com 82611308Santhony.gutierrez@amd.com // New SenderState for the memory access 82711308Santhony.gutierrez@amd.com X86ISA::GpuTLB::TranslationState *sender_state = 82811308Santhony.gutierrez@amd.com safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState); 82911308Santhony.gutierrez@amd.com 83011308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 83111308Santhony.gutierrez@amd.com delete sender_state->saved; 83211308Santhony.gutierrez@amd.com delete sender_state; 83311308Santhony.gutierrez@amd.com 83411308Santhony.gutierrez@amd.com assert(pkt->req->hasPaddr()); 83511308Santhony.gutierrez@amd.com assert(pkt->req->hasSize()); 83611308Santhony.gutierrez@amd.com 83711308Santhony.gutierrez@amd.com uint8_t *tmpData = pkt->getPtr<uint8_t>(); 83811308Santhony.gutierrez@amd.com 83911308Santhony.gutierrez@amd.com // this is necessary because the GPU TLB receives packets instead 84011308Santhony.gutierrez@amd.com // of requests. when the translation is complete, all relevent 84111308Santhony.gutierrez@amd.com // fields in the request will be populated, but not in the packet. 84211308Santhony.gutierrez@amd.com // here we create the new packet so we can set the size, addr, 84311308Santhony.gutierrez@amd.com // and proper flags. 84411308Santhony.gutierrez@amd.com PacketPtr oldPkt = pkt; 84511308Santhony.gutierrez@amd.com pkt = new Packet(oldPkt->req, oldPkt->cmd); 84611308Santhony.gutierrez@amd.com delete oldPkt; 84711308Santhony.gutierrez@amd.com pkt->dataStatic(tmpData); 84811308Santhony.gutierrez@amd.com 84911308Santhony.gutierrez@amd.com 85011308Santhony.gutierrez@amd.com // New SenderState for the memory access 85111308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, 85211308Santhony.gutierrez@amd.com index, nullptr); 85311308Santhony.gutierrez@amd.com 85411308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index); 85511308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[index] = hit_level; 85611308Santhony.gutierrez@amd.com 85711308Santhony.gutierrez@amd.com 85811308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the 85911308Santhony.gutierrez@amd.com // appropriate cycle to send the timing memory request to ruby 86011308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 86111308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt); 86211308Santhony.gutierrez@amd.com 86311308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data " 86411308Santhony.gutierrez@amd.com "scheduled\n", cu_id, gpuDynInst->simdId, 86511308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, index, pkt->req->getPaddr()); 86611308Santhony.gutierrez@amd.com 86711308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 86811308Santhony.gutierrez@amd.com } else if (tlbPort[tlbPort_index]->isStalled()) { 86911308Santhony.gutierrez@amd.com assert(tlbPort[tlbPort_index]->retries.size() > 0); 87011308Santhony.gutierrez@amd.com 87111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 87211308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 87311308Santhony.gutierrez@amd.com tmp_vaddr); 87411308Santhony.gutierrez@amd.com 87511308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 87611308Santhony.gutierrez@amd.com } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) { 87711308Santhony.gutierrez@amd.com // Stall the data port; 87811308Santhony.gutierrez@amd.com // No more packet will be issued till 87911308Santhony.gutierrez@amd.com // ruby indicates resources are freed by 88011308Santhony.gutierrez@amd.com // a recvReqRetry() call back on this port. 88111308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->stallPort(); 88211308Santhony.gutierrez@amd.com 88311308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 88411308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 88511308Santhony.gutierrez@amd.com tmp_vaddr); 88611308Santhony.gutierrez@amd.com 88711308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 88811308Santhony.gutierrez@amd.com } else { 88911308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, 89011308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: Translation for addr %#x sent!\n", 89111308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, tmp_vaddr); 89211308Santhony.gutierrez@amd.com } 89311308Santhony.gutierrez@amd.com } else { 89411308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::MemFenceReq) { 89511308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 89611308Santhony.gutierrez@amd.com } else { 89711308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ll << index)); 89811308Santhony.gutierrez@amd.com } 89911308Santhony.gutierrez@amd.com 90011308Santhony.gutierrez@amd.com // New SenderState for the memory access 90111308Santhony.gutierrez@amd.com delete pkt->senderState; 90211308Santhony.gutierrez@amd.com 90311308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 90411308Santhony.gutierrez@amd.com pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode, 90511308Santhony.gutierrez@amd.com shader->gpuTc); 90611308Santhony.gutierrez@amd.com 90711308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 90811308Santhony.gutierrez@amd.com 90911308Santhony.gutierrez@amd.com // the addr of the packet is not modified, so we need to create a new 91011308Santhony.gutierrez@amd.com // packet, or otherwise the memory access will have the old virtual 91111308Santhony.gutierrez@amd.com // address sent in the translation packet, instead of the physical 91211308Santhony.gutierrez@amd.com // address returned by the translation. 91311308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd); 91411308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 91511308Santhony.gutierrez@amd.com 91611308Santhony.gutierrez@amd.com // Translation is done. It is safe to send the packet to memory. 91711308Santhony.gutierrez@amd.com memPort[0]->sendFunctional(new_pkt); 91811308Santhony.gutierrez@amd.com 91911308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: index %d: addr %#x\n", cu_id, 92011308Santhony.gutierrez@amd.com gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 92111308Santhony.gutierrez@amd.com new_pkt->req->getPaddr()); 92211308Santhony.gutierrez@amd.com 92311308Santhony.gutierrez@amd.com // safe_cast the senderState 92411308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *sender_state = 92511308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 92611308Santhony.gutierrez@amd.com 92711308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 92811308Santhony.gutierrez@amd.com delete new_pkt; 92911308Santhony.gutierrez@amd.com delete pkt->senderState; 93011308Santhony.gutierrez@amd.com delete pkt->req; 93111308Santhony.gutierrez@amd.com delete pkt; 93211308Santhony.gutierrez@amd.com } 93311308Santhony.gutierrez@amd.com} 93411308Santhony.gutierrez@amd.com 93511308Santhony.gutierrez@amd.comvoid 93611308Santhony.gutierrez@amd.comComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 93711308Santhony.gutierrez@amd.com{ 93811308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 93911308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt); 94011308Santhony.gutierrez@amd.com 94111308Santhony.gutierrez@amd.com 94211308Santhony.gutierrez@amd.com // New SenderState for the memory access 94311308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index, 94411308Santhony.gutierrez@amd.com nullptr); 94511308Santhony.gutierrez@amd.com 94611308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x sync scheduled\n", 94711308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 94811308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 94911308Santhony.gutierrez@amd.com 95011308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 95111308Santhony.gutierrez@amd.com} 95211308Santhony.gutierrez@amd.com 95311308Santhony.gutierrez@amd.comvoid 95411308Santhony.gutierrez@amd.comComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch, 95511308Santhony.gutierrez@amd.com Request* req) 95611308Santhony.gutierrez@amd.com{ 95711308Santhony.gutierrez@amd.com if (!req) { 95811435Smitch.hayenga@arm.com req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId); 95911308Santhony.gutierrez@amd.com } 96011308Santhony.gutierrez@amd.com req->setPaddr(0); 96111308Santhony.gutierrez@amd.com if (kernelLaunch) { 96211308Santhony.gutierrez@amd.com req->setFlags(Request::KERNEL); 96311308Santhony.gutierrez@amd.com } 96411308Santhony.gutierrez@amd.com 96511308Santhony.gutierrez@amd.com gpuDynInst->s_type = SEG_GLOBAL; 96611308Santhony.gutierrez@amd.com 96711308Santhony.gutierrez@amd.com // for non-kernel MemFence operations, memorder flags are set depending 96811308Santhony.gutierrez@amd.com // on which type of request is currently being sent, so this 96911308Santhony.gutierrez@amd.com // should be set by the caller (e.g. if an inst has acq-rel 97011308Santhony.gutierrez@amd.com // semantics, it will send one acquire req an one release req) 97111308Santhony.gutierrez@amd.com gpuDynInst->setRequestFlags(req, kernelLaunch); 97211308Santhony.gutierrez@amd.com 97311308Santhony.gutierrez@amd.com // a mem fence must correspond to an acquire/release request 97411308Santhony.gutierrez@amd.com assert(req->isAcquire() || req->isRelease()); 97511308Santhony.gutierrez@amd.com 97611308Santhony.gutierrez@amd.com // create packet 97711308Santhony.gutierrez@amd.com PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq); 97811308Santhony.gutierrez@amd.com 97911308Santhony.gutierrez@amd.com // set packet's sender state 98011308Santhony.gutierrez@amd.com pkt->senderState = 98111308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, 0, nullptr); 98211308Santhony.gutierrez@amd.com 98311308Santhony.gutierrez@amd.com // send the packet 98411308Santhony.gutierrez@amd.com sendSyncRequest(gpuDynInst, 0, pkt); 98511308Santhony.gutierrez@amd.com} 98611308Santhony.gutierrez@amd.com 98711308Santhony.gutierrez@amd.comconst char* 98811308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemRespEvent::description() const 98911308Santhony.gutierrez@amd.com{ 99011308Santhony.gutierrez@amd.com return "ComputeUnit memory response event"; 99111308Santhony.gutierrez@amd.com} 99211308Santhony.gutierrez@amd.com 99311308Santhony.gutierrez@amd.comvoid 99411308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemRespEvent::process() 99511308Santhony.gutierrez@amd.com{ 99611308Santhony.gutierrez@amd.com DataPort::SenderState *sender_state = 99711308Santhony.gutierrez@amd.com safe_cast<DataPort::SenderState*>(pkt->senderState); 99811308Santhony.gutierrez@amd.com 99911308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 100011308Santhony.gutierrez@amd.com ComputeUnit *compute_unit = dataPort->computeUnit; 100111308Santhony.gutierrez@amd.com 100211308Santhony.gutierrez@amd.com assert(gpuDynInst); 100311308Santhony.gutierrez@amd.com 100411308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n", 100511308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 100611308Santhony.gutierrez@amd.com pkt->req->getPaddr(), dataPort->index); 100711308Santhony.gutierrez@amd.com 100811308Santhony.gutierrez@amd.com Addr paddr = pkt->req->getPaddr(); 100911308Santhony.gutierrez@amd.com 101011308Santhony.gutierrez@amd.com if (pkt->cmd != MemCmd::MemFenceResp) { 101111308Santhony.gutierrez@amd.com int index = gpuDynInst->memStatusVector[paddr].back(); 101211308Santhony.gutierrez@amd.com 101311308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "Response for addr %#x, index %d\n", 101411308Santhony.gutierrez@amd.com pkt->req->getPaddr(), index); 101511308Santhony.gutierrez@amd.com 101611308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[paddr].pop_back(); 101711308Santhony.gutierrez@amd.com gpuDynInst->pAddr = pkt->req->getPaddr(); 101811308Santhony.gutierrez@amd.com 101911308Santhony.gutierrez@amd.com if (pkt->isRead() || pkt->isWrite()) { 102011308Santhony.gutierrez@amd.com 102111308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg <= MAX_REGS_FOR_NON_VEC_MEM_INST) { 102211308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 102311308Santhony.gutierrez@amd.com } else { 102411308Santhony.gutierrez@amd.com assert(gpuDynInst->statusVector[index] > 0); 102511308Santhony.gutierrez@amd.com gpuDynInst->statusVector[index]--; 102611308Santhony.gutierrez@amd.com 102711308Santhony.gutierrez@amd.com if (!gpuDynInst->statusVector[index]) 102811308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 102911308Santhony.gutierrez@amd.com } 103011308Santhony.gutierrez@amd.com 103111308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "bitvector is now %#x\n", 103211308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector); 103311308Santhony.gutierrez@amd.com 103411308Santhony.gutierrez@amd.com if (gpuDynInst->statusBitVector == VectorMask(0)) { 103511308Santhony.gutierrez@amd.com auto iter = gpuDynInst->memStatusVector.begin(); 103611308Santhony.gutierrez@amd.com auto end = gpuDynInst->memStatusVector.end(); 103711308Santhony.gutierrez@amd.com 103811308Santhony.gutierrez@amd.com while (iter != end) { 103911308Santhony.gutierrez@amd.com assert(iter->second.empty()); 104011308Santhony.gutierrez@amd.com ++iter; 104111308Santhony.gutierrez@amd.com } 104211308Santhony.gutierrez@amd.com 104311308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector.clear(); 104411308Santhony.gutierrez@amd.com 104511308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST) 104611308Santhony.gutierrez@amd.com gpuDynInst->statusVector.clear(); 104711308Santhony.gutierrez@amd.com 104811308Santhony.gutierrez@amd.com if (gpuDynInst->m_op == Enums::MO_LD || MO_A(gpuDynInst->m_op) 104911308Santhony.gutierrez@amd.com || MO_ANR(gpuDynInst->m_op)) { 105011308Santhony.gutierrez@amd.com assert(compute_unit->globalMemoryPipe.isGMLdRespFIFOWrRdy()); 105111308Santhony.gutierrez@amd.com 105211308Santhony.gutierrez@amd.com compute_unit->globalMemoryPipe.getGMLdRespFIFO() 105311308Santhony.gutierrez@amd.com .push(gpuDynInst); 105411308Santhony.gutierrez@amd.com } else { 105511308Santhony.gutierrez@amd.com assert(compute_unit->globalMemoryPipe.isGMStRespFIFOWrRdy()); 105611308Santhony.gutierrez@amd.com 105711308Santhony.gutierrez@amd.com compute_unit->globalMemoryPipe.getGMStRespFIFO() 105811308Santhony.gutierrez@amd.com .push(gpuDynInst); 105911308Santhony.gutierrez@amd.com } 106011308Santhony.gutierrez@amd.com 106111308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: packet totally complete\n", 106211308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 106311308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 106411308Santhony.gutierrez@amd.com 106511308Santhony.gutierrez@amd.com // after clearing the status vectors, 106611308Santhony.gutierrez@amd.com // see if there is a continuation to perform 106711308Santhony.gutierrez@amd.com // the continuation may generate more work for 106811308Santhony.gutierrez@amd.com // this memory request 106911308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 107011308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 107111308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 107211308Santhony.gutierrez@amd.com gpuDynInst); 107311308Santhony.gutierrez@amd.com } 107411308Santhony.gutierrez@amd.com } 107511308Santhony.gutierrez@amd.com } 107611308Santhony.gutierrez@amd.com } else { 107711308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 107811308Santhony.gutierrez@amd.com 107911308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 108011308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 108111308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 108211308Santhony.gutierrez@amd.com gpuDynInst); 108311308Santhony.gutierrez@amd.com } 108411308Santhony.gutierrez@amd.com } 108511308Santhony.gutierrez@amd.com 108611308Santhony.gutierrez@amd.com delete pkt->senderState; 108711308Santhony.gutierrez@amd.com delete pkt->req; 108811308Santhony.gutierrez@amd.com delete pkt; 108911308Santhony.gutierrez@amd.com} 109011308Santhony.gutierrez@amd.com 109111308Santhony.gutierrez@amd.comComputeUnit* 109211308Santhony.gutierrez@amd.comComputeUnitParams::create() 109311308Santhony.gutierrez@amd.com{ 109411308Santhony.gutierrez@amd.com return new ComputeUnit(this); 109511308Santhony.gutierrez@amd.com} 109611308Santhony.gutierrez@amd.com 109711308Santhony.gutierrez@amd.combool 109811308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) 109911308Santhony.gutierrez@amd.com{ 110011308Santhony.gutierrez@amd.com Addr line = pkt->req->getPaddr(); 110111308Santhony.gutierrez@amd.com 110211308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLBPort received %#x->%#x\n", computeUnit->cu_id, 110311308Santhony.gutierrez@amd.com pkt->req->getVaddr(), line); 110411308Santhony.gutierrez@amd.com 110511308Santhony.gutierrez@amd.com assert(pkt->senderState); 110611308Santhony.gutierrez@amd.com computeUnit->tlbCycles += curTick(); 110711308Santhony.gutierrez@amd.com 110811308Santhony.gutierrez@amd.com // pop off the TLB translation state 110911308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 111011308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 111111308Santhony.gutierrez@amd.com 111211308Santhony.gutierrez@amd.com // no PageFaults are permitted for data accesses 111311308Santhony.gutierrez@amd.com if (!translation_state->tlbEntry->valid) { 111411308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 111511308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(translation_state->saved); 111611308Santhony.gutierrez@amd.com 111711308Santhony.gutierrez@amd.com Wavefront *w M5_VAR_USED = 111811308Santhony.gutierrez@amd.com computeUnit->wfList[sender_state->_gpuDynInst->simdId] 111911308Santhony.gutierrez@amd.com [sender_state->_gpuDynInst->wfSlotId]; 112011308Santhony.gutierrez@amd.com 112111308Santhony.gutierrez@amd.com DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId, 112211308Santhony.gutierrez@amd.com pkt->req->getVaddr()); 112311308Santhony.gutierrez@amd.com } 112411308Santhony.gutierrez@amd.com 112511308Santhony.gutierrez@amd.com assert(translation_state->tlbEntry->valid); 112611308Santhony.gutierrez@amd.com 112711308Santhony.gutierrez@amd.com // update the hitLevel distribution 112811308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 112911308Santhony.gutierrez@amd.com computeUnit->hitsPerTLBLevel[hit_level]++; 113011308Santhony.gutierrez@amd.com 113111308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 113211308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 113311308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 113411308Santhony.gutierrez@amd.com 113511308Santhony.gutierrez@amd.com // for prefetch pkt 113611308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode = translation_state->tlbMode; 113711308Santhony.gutierrez@amd.com 113811308Santhony.gutierrez@amd.com delete translation_state; 113911308Santhony.gutierrez@amd.com 114011308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 114111308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 114211308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(pkt->senderState); 114311308Santhony.gutierrez@amd.com 114411308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 114511308Santhony.gutierrez@amd.com int mp_index = sender_state->portIndex; 114611308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 114711308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[line].push_back(mp_index); 114811308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[mp_index] = hit_level; 114911308Santhony.gutierrez@amd.com 115011308Santhony.gutierrez@amd.com MemCmd requestCmd; 115111308Santhony.gutierrez@amd.com 115211308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::ReadResp) { 115311308Santhony.gutierrez@amd.com requestCmd = MemCmd::ReadReq; 115411308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::WriteResp) { 115511308Santhony.gutierrez@amd.com requestCmd = MemCmd::WriteReq; 115611308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::SwapResp) { 115711308Santhony.gutierrez@amd.com requestCmd = MemCmd::SwapReq; 115811308Santhony.gutierrez@amd.com } else { 115911308Santhony.gutierrez@amd.com panic("unsupported response to request conversion %s\n", 116011308Santhony.gutierrez@amd.com pkt->cmd.toString()); 116111308Santhony.gutierrez@amd.com } 116211308Santhony.gutierrez@amd.com 116311308Santhony.gutierrez@amd.com if (computeUnit->prefetchDepth) { 116411308Santhony.gutierrez@amd.com int simdId = gpuDynInst->simdId; 116511308Santhony.gutierrez@amd.com int wfSlotId = gpuDynInst->wfSlotId; 116611308Santhony.gutierrez@amd.com Addr last = 0; 116711308Santhony.gutierrez@amd.com 116811308Santhony.gutierrez@amd.com switch(computeUnit->prefetchType) { 116911534Sjohn.kalamatianos@amd.com case Enums::PF_CU: 117011308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrCU[mp_index]; 117111308Santhony.gutierrez@amd.com break; 117211534Sjohn.kalamatianos@amd.com case Enums::PF_PHASE: 117311534Sjohn.kalamatianos@amd.com last = computeUnit->lastVaddrSimd[simdId][mp_index]; 117411308Santhony.gutierrez@amd.com break; 117511534Sjohn.kalamatianos@amd.com case Enums::PF_WF: 117611308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index]; 117711534Sjohn.kalamatianos@amd.com default: 117811308Santhony.gutierrez@amd.com break; 117911308Santhony.gutierrez@amd.com } 118011308Santhony.gutierrez@amd.com 118111308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n", 118211308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index, last); 118311308Santhony.gutierrez@amd.com 118411308Santhony.gutierrez@amd.com int stride = last ? (roundDown(vaddr, TheISA::PageBytes) - 118511308Santhony.gutierrez@amd.com roundDown(last, TheISA::PageBytes)) >> TheISA::PageShift 118611308Santhony.gutierrez@amd.com : 0; 118711308Santhony.gutierrez@amd.com 118811308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Stride is %d\n", stride); 118911308Santhony.gutierrez@amd.com 119011308Santhony.gutierrez@amd.com computeUnit->lastVaddrCU[mp_index] = vaddr; 119111534Sjohn.kalamatianos@amd.com computeUnit->lastVaddrSimd[simdId][mp_index] = vaddr; 119211308Santhony.gutierrez@amd.com computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr; 119311308Santhony.gutierrez@amd.com 119411308Santhony.gutierrez@amd.com stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ? 119511308Santhony.gutierrez@amd.com computeUnit->prefetchStride: stride; 119611308Santhony.gutierrez@amd.com 119711308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr, 119811308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index); 119911308Santhony.gutierrez@amd.com 120011308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Prefetching from %#x:", vaddr); 120111308Santhony.gutierrez@amd.com 120211308Santhony.gutierrez@amd.com // Prefetch Next few pages atomically 120311308Santhony.gutierrez@amd.com for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) { 120411308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride, 120511308Santhony.gutierrez@amd.com vaddr+stride*pf*TheISA::PageBytes); 120611308Santhony.gutierrez@amd.com 120711308Santhony.gutierrez@amd.com if (!stride) 120811308Santhony.gutierrez@amd.com break; 120911308Santhony.gutierrez@amd.com 121011308Santhony.gutierrez@amd.com Request *prefetch_req = new Request(0, vaddr + stride * pf * 121111308Santhony.gutierrez@amd.com TheISA::PageBytes, 121211308Santhony.gutierrez@amd.com sizeof(uint8_t), 0, 121311308Santhony.gutierrez@amd.com computeUnit->masterId(), 121411308Santhony.gutierrez@amd.com 0, 0, 0); 121511308Santhony.gutierrez@amd.com 121611308Santhony.gutierrez@amd.com PacketPtr prefetch_pkt = new Packet(prefetch_req, requestCmd); 121711308Santhony.gutierrez@amd.com uint8_t foo = 0; 121811308Santhony.gutierrez@amd.com prefetch_pkt->dataStatic(&foo); 121911308Santhony.gutierrez@amd.com 122011308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 122111308Santhony.gutierrez@amd.com prefetch_pkt->senderState = 122211308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, 122311308Santhony.gutierrez@amd.com computeUnit->shader->gpuTc, 122411308Santhony.gutierrez@amd.com true); 122511308Santhony.gutierrez@amd.com 122611308Santhony.gutierrez@amd.com // Currently prefetches are zero-latency, hence the sendFunctional 122711308Santhony.gutierrez@amd.com sendFunctional(prefetch_pkt); 122811308Santhony.gutierrez@amd.com 122911308Santhony.gutierrez@amd.com /* safe_cast the senderState */ 123011308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *tlb_state = 123111308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>( 123211308Santhony.gutierrez@amd.com prefetch_pkt->senderState); 123311308Santhony.gutierrez@amd.com 123411308Santhony.gutierrez@amd.com 123511308Santhony.gutierrez@amd.com delete tlb_state->tlbEntry; 123611308Santhony.gutierrez@amd.com delete tlb_state; 123711308Santhony.gutierrez@amd.com delete prefetch_pkt->req; 123811308Santhony.gutierrez@amd.com delete prefetch_pkt; 123911308Santhony.gutierrez@amd.com } 124011308Santhony.gutierrez@amd.com } 124111308Santhony.gutierrez@amd.com 124211308Santhony.gutierrez@amd.com // First we must convert the response cmd back to a request cmd so that 124311308Santhony.gutierrez@amd.com // the request can be sent through the cu's master port 124411308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, requestCmd); 124511308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 124611308Santhony.gutierrez@amd.com delete pkt->senderState; 124711308Santhony.gutierrez@amd.com delete pkt; 124811308Santhony.gutierrez@amd.com 124911308Santhony.gutierrez@amd.com // New SenderState for the memory access 125011308Santhony.gutierrez@amd.com new_pkt->senderState = 125111308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index, 125211308Santhony.gutierrez@amd.com nullptr); 125311308Santhony.gutierrez@amd.com 125411308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the appropriate 125511308Santhony.gutierrez@amd.com // cycle to send the timing memory request to ruby 125611308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 125711308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(computeUnit->memPort[mp_index], 125811308Santhony.gutierrez@amd.com new_pkt); 125911308Santhony.gutierrez@amd.com 126011308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data scheduled\n", 126111308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 126211308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, mp_index, new_pkt->req->getPaddr()); 126311308Santhony.gutierrez@amd.com 126411308Santhony.gutierrez@amd.com computeUnit->schedule(mem_req_event, curTick() + 126511308Santhony.gutierrez@amd.com computeUnit->req_tick_latency); 126611308Santhony.gutierrez@amd.com 126711308Santhony.gutierrez@amd.com return true; 126811308Santhony.gutierrez@amd.com} 126911308Santhony.gutierrez@amd.com 127011308Santhony.gutierrez@amd.comconst char* 127111308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemReqEvent::description() const 127211308Santhony.gutierrez@amd.com{ 127311308Santhony.gutierrez@amd.com return "ComputeUnit memory request event"; 127411308Santhony.gutierrez@amd.com} 127511308Santhony.gutierrez@amd.com 127611308Santhony.gutierrez@amd.comvoid 127711308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemReqEvent::process() 127811308Santhony.gutierrez@amd.com{ 127911308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 128011308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 128111308Santhony.gutierrez@amd.com ComputeUnit *compute_unit M5_VAR_USED = dataPort->computeUnit; 128211308Santhony.gutierrez@amd.com 128311308Santhony.gutierrez@amd.com if (!(dataPort->sendTimingReq(pkt))) { 128411308Santhony.gutierrez@amd.com dataPort->retries.push_back(std::make_pair(pkt, gpuDynInst)); 128511308Santhony.gutierrez@amd.com 128611308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 128711308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req failed!\n", 128811308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 128911308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, dataPort->index, 129011308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 129111308Santhony.gutierrez@amd.com } else { 129211308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 129311308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req sent!\n", 129411308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 129511308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, dataPort->index, 129611308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 129711308Santhony.gutierrez@amd.com } 129811308Santhony.gutierrez@amd.com} 129911308Santhony.gutierrez@amd.com 130011308Santhony.gutierrez@amd.com/* 130111308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, 130211308Santhony.gutierrez@amd.com * if <retries> queue is not Retry sending the translation 130311308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 130411308Santhony.gutierrez@amd.com * a translation completes. 130511308Santhony.gutierrez@amd.com */ 130611308Santhony.gutierrez@amd.comvoid 130711308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvReqRetry() 130811308Santhony.gutierrez@amd.com{ 130911308Santhony.gutierrez@amd.com int len = retries.size(); 131011308Santhony.gutierrez@amd.com 131111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLB recvReqRetry - %d pending requests\n", 131211308Santhony.gutierrez@amd.com computeUnit->cu_id, len); 131311308Santhony.gutierrez@amd.com 131411308Santhony.gutierrez@amd.com assert(len > 0); 131511308Santhony.gutierrez@amd.com assert(isStalled()); 131611308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 131711308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 131811308Santhony.gutierrez@amd.com unstallPort(); 131911308Santhony.gutierrez@amd.com 132011308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 132111308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 132211308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 132311308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr); 132411308Santhony.gutierrez@amd.com 132511308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 132611308Santhony.gutierrez@amd.com // Stall port 132711308Santhony.gutierrez@amd.com stallPort(); 132811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 132911308Santhony.gutierrez@amd.com break; 133011308Santhony.gutierrez@amd.com } else { 133111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 133211308Santhony.gutierrez@amd.com retries.pop_front(); 133311308Santhony.gutierrez@amd.com } 133411308Santhony.gutierrez@amd.com } 133511308Santhony.gutierrez@amd.com} 133611308Santhony.gutierrez@amd.com 133711308Santhony.gutierrez@amd.combool 133811308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt) 133911308Santhony.gutierrez@amd.com{ 134011308Santhony.gutierrez@amd.com Addr line M5_VAR_USED = pkt->req->getPaddr(); 134111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n", 134211308Santhony.gutierrez@amd.com computeUnit->cu_id, pkt->req->getVaddr(), line); 134311308Santhony.gutierrez@amd.com 134411308Santhony.gutierrez@amd.com assert(pkt->senderState); 134511308Santhony.gutierrez@amd.com 134611308Santhony.gutierrez@amd.com // pop off the TLB translation state 134711308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 134811308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 134911308Santhony.gutierrez@amd.com 135011308Santhony.gutierrez@amd.com bool success = translation_state->tlbEntry->valid; 135111308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 135211308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 135311308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 135411308Santhony.gutierrez@amd.com delete translation_state; 135511308Santhony.gutierrez@amd.com 135611308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 135711308Santhony.gutierrez@amd.com ITLBPort::SenderState *sender_state = 135811308Santhony.gutierrez@amd.com safe_cast<ITLBPort::SenderState*>(pkt->senderState); 135911308Santhony.gutierrez@amd.com 136011308Santhony.gutierrez@amd.com // get the wavefront associated with this translation request 136111308Santhony.gutierrez@amd.com Wavefront *wavefront = sender_state->wavefront; 136211308Santhony.gutierrez@amd.com delete pkt->senderState; 136311308Santhony.gutierrez@amd.com 136411308Santhony.gutierrez@amd.com if (success) { 136511308Santhony.gutierrez@amd.com // pkt is reused in fetch(), don't delete it here. However, we must 136611308Santhony.gutierrez@amd.com // reset the command to be a request so that it can be sent through 136711308Santhony.gutierrez@amd.com // the cu's master port 136811308Santhony.gutierrez@amd.com assert(pkt->cmd == MemCmd::ReadResp); 136911308Santhony.gutierrez@amd.com pkt->cmd = MemCmd::ReadReq; 137011308Santhony.gutierrez@amd.com 137111308Santhony.gutierrez@amd.com computeUnit->fetchStage.fetch(pkt, wavefront); 137211308Santhony.gutierrez@amd.com } else { 137311308Santhony.gutierrez@amd.com if (wavefront->dropFetch) { 137411308Santhony.gutierrez@amd.com assert(wavefront->instructionBuffer.empty()); 137511308Santhony.gutierrez@amd.com wavefront->dropFetch = false; 137611308Santhony.gutierrez@amd.com } 137711308Santhony.gutierrez@amd.com 137811308Santhony.gutierrez@amd.com wavefront->pendingFetch = 0; 137911308Santhony.gutierrez@amd.com } 138011308Santhony.gutierrez@amd.com 138111308Santhony.gutierrez@amd.com return true; 138211308Santhony.gutierrez@amd.com} 138311308Santhony.gutierrez@amd.com 138411308Santhony.gutierrez@amd.com/* 138511308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, if 138611308Santhony.gutierrez@amd.com * <retries> queue is not empty. Retry sending the translation 138711308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 138811308Santhony.gutierrez@amd.com * a translation completes. 138911308Santhony.gutierrez@amd.com */ 139011308Santhony.gutierrez@amd.comvoid 139111308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvReqRetry() 139211308Santhony.gutierrez@amd.com{ 139311308Santhony.gutierrez@amd.com 139411308Santhony.gutierrez@amd.com int len = retries.size(); 139511308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLB recvReqRetry - %d pending requests\n", len); 139611308Santhony.gutierrez@amd.com 139711308Santhony.gutierrez@amd.com assert(len > 0); 139811308Santhony.gutierrez@amd.com assert(isStalled()); 139911308Santhony.gutierrez@amd.com 140011308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 140111308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 140211308Santhony.gutierrez@amd.com unstallPort(); 140311308Santhony.gutierrez@amd.com 140411308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 140511308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 140611308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 140711308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr); 140811308Santhony.gutierrez@amd.com 140911308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 141011308Santhony.gutierrez@amd.com stallPort(); // Stall port 141111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 141211308Santhony.gutierrez@amd.com break; 141311308Santhony.gutierrez@amd.com } else { 141411308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 141511308Santhony.gutierrez@amd.com retries.pop_front(); 141611308Santhony.gutierrez@amd.com } 141711308Santhony.gutierrez@amd.com } 141811308Santhony.gutierrez@amd.com} 141911308Santhony.gutierrez@amd.com 142011308Santhony.gutierrez@amd.comvoid 142111308Santhony.gutierrez@amd.comComputeUnit::regStats() 142211308Santhony.gutierrez@amd.com{ 142311523Sdavid.guillen@arm.com MemObject::regStats(); 142411523Sdavid.guillen@arm.com 142511308Santhony.gutierrez@amd.com tlbCycles 142611308Santhony.gutierrez@amd.com .name(name() + ".tlb_cycles") 142711308Santhony.gutierrez@amd.com .desc("total number of cycles for all uncoalesced requests") 142811308Santhony.gutierrez@amd.com ; 142911308Santhony.gutierrez@amd.com 143011308Santhony.gutierrez@amd.com tlbRequests 143111308Santhony.gutierrez@amd.com .name(name() + ".tlb_requests") 143211308Santhony.gutierrez@amd.com .desc("number of uncoalesced requests") 143311308Santhony.gutierrez@amd.com ; 143411308Santhony.gutierrez@amd.com 143511308Santhony.gutierrez@amd.com tlbLatency 143611308Santhony.gutierrez@amd.com .name(name() + ".avg_translation_latency") 143711308Santhony.gutierrez@amd.com .desc("Avg. translation latency for data translations") 143811308Santhony.gutierrez@amd.com ; 143911308Santhony.gutierrez@amd.com 144011308Santhony.gutierrez@amd.com tlbLatency = tlbCycles / tlbRequests; 144111308Santhony.gutierrez@amd.com 144211308Santhony.gutierrez@amd.com hitsPerTLBLevel 144311308Santhony.gutierrez@amd.com .init(4) 144411308Santhony.gutierrez@amd.com .name(name() + ".TLB_hits_distribution") 144511308Santhony.gutierrez@amd.com .desc("TLB hits distribution (0 for page table, x for Lx-TLB") 144611308Santhony.gutierrez@amd.com ; 144711308Santhony.gutierrez@amd.com 144811308Santhony.gutierrez@amd.com // fixed number of TLB levels 144911308Santhony.gutierrez@amd.com for (int i = 0; i < 4; ++i) { 145011308Santhony.gutierrez@amd.com if (!i) 145111308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i,"page_table"); 145211308Santhony.gutierrez@amd.com else 145311308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i, csprintf("L%d_TLB",i)); 145411308Santhony.gutierrez@amd.com } 145511308Santhony.gutierrez@amd.com 145611308Santhony.gutierrez@amd.com execRateDist 145711308Santhony.gutierrez@amd.com .init(0, 10, 2) 145811308Santhony.gutierrez@amd.com .name(name() + ".inst_exec_rate") 145911308Santhony.gutierrez@amd.com .desc("Instruction Execution Rate: Number of executed vector " 146011308Santhony.gutierrez@amd.com "instructions per cycle") 146111308Santhony.gutierrez@amd.com ; 146211308Santhony.gutierrez@amd.com 146311308Santhony.gutierrez@amd.com ldsBankConflictDist 146411534Sjohn.kalamatianos@amd.com .init(0, wfSize(), 2) 146511308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_conflicts") 146611308Santhony.gutierrez@amd.com .desc("Number of bank conflicts per LDS memory packet") 146711308Santhony.gutierrez@amd.com ; 146811308Santhony.gutierrez@amd.com 146911308Santhony.gutierrez@amd.com ldsBankAccesses 147011308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_access_cnt") 147111308Santhony.gutierrez@amd.com .desc("Total number of LDS bank accesses") 147211308Santhony.gutierrez@amd.com ; 147311308Santhony.gutierrez@amd.com 147411308Santhony.gutierrez@amd.com pageDivergenceDist 147511534Sjohn.kalamatianos@amd.com // A wavefront can touch up to N pages per memory instruction where 147611534Sjohn.kalamatianos@amd.com // N is equal to the wavefront size 147711534Sjohn.kalamatianos@amd.com // The number of pages per bin can be configured (here it's 4). 147811534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 147911308Santhony.gutierrez@amd.com .name(name() + ".page_divergence_dist") 148011308Santhony.gutierrez@amd.com .desc("pages touched per wf (over all mem. instr.)") 148111308Santhony.gutierrez@amd.com ; 148211308Santhony.gutierrez@amd.com 148311308Santhony.gutierrez@amd.com controlFlowDivergenceDist 148411534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 148511308Santhony.gutierrez@amd.com .name(name() + ".warp_execution_dist") 148611308Santhony.gutierrez@amd.com .desc("number of lanes active per instruction (oval all instructions)") 148711308Santhony.gutierrez@amd.com ; 148811308Santhony.gutierrez@amd.com 148911308Santhony.gutierrez@amd.com activeLanesPerGMemInstrDist 149011534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 149111308Santhony.gutierrez@amd.com .name(name() + ".gmem_lanes_execution_dist") 149211308Santhony.gutierrez@amd.com .desc("number of active lanes per global memory instruction") 149311308Santhony.gutierrez@amd.com ; 149411308Santhony.gutierrez@amd.com 149511308Santhony.gutierrez@amd.com activeLanesPerLMemInstrDist 149611534Sjohn.kalamatianos@amd.com .init(1, wfSize(), 4) 149711308Santhony.gutierrez@amd.com .name(name() + ".lmem_lanes_execution_dist") 149811308Santhony.gutierrez@amd.com .desc("number of active lanes per local memory instruction") 149911308Santhony.gutierrez@amd.com ; 150011308Santhony.gutierrez@amd.com 150111308Santhony.gutierrez@amd.com numInstrExecuted 150211308Santhony.gutierrez@amd.com .name(name() + ".num_instr_executed") 150311308Santhony.gutierrez@amd.com .desc("number of instructions executed") 150411308Santhony.gutierrez@amd.com ; 150511308Santhony.gutierrez@amd.com 150611308Santhony.gutierrez@amd.com numVecOpsExecuted 150711308Santhony.gutierrez@amd.com .name(name() + ".num_vec_ops_executed") 150811534Sjohn.kalamatianos@amd.com .desc("number of vec ops executed (e.g. WF size/inst)") 150911308Santhony.gutierrez@amd.com ; 151011308Santhony.gutierrez@amd.com 151111308Santhony.gutierrez@amd.com totalCycles 151211308Santhony.gutierrez@amd.com .name(name() + ".num_total_cycles") 151311308Santhony.gutierrez@amd.com .desc("number of cycles the CU ran for") 151411308Santhony.gutierrez@amd.com ; 151511308Santhony.gutierrez@amd.com 151611308Santhony.gutierrez@amd.com ipc 151711308Santhony.gutierrez@amd.com .name(name() + ".ipc") 151811308Santhony.gutierrez@amd.com .desc("Instructions per cycle (this CU only)") 151911308Santhony.gutierrez@amd.com ; 152011308Santhony.gutierrez@amd.com 152111308Santhony.gutierrez@amd.com vpc 152211308Santhony.gutierrez@amd.com .name(name() + ".vpc") 152311308Santhony.gutierrez@amd.com .desc("Vector Operations per cycle (this CU only)") 152411308Santhony.gutierrez@amd.com ; 152511308Santhony.gutierrez@amd.com 152611308Santhony.gutierrez@amd.com numALUInstsExecuted 152711308Santhony.gutierrez@amd.com .name(name() + ".num_alu_insts_executed") 152811308Santhony.gutierrez@amd.com .desc("Number of dynamic non-GM memory insts executed") 152911308Santhony.gutierrez@amd.com ; 153011308Santhony.gutierrez@amd.com 153111308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation 153211308Santhony.gutierrez@amd.com .name(name() + ".wg_blocked_due_lds_alloc") 153311308Santhony.gutierrez@amd.com .desc("Workgroup blocked due to LDS capacity") 153411308Santhony.gutierrez@amd.com ; 153511308Santhony.gutierrez@amd.com 153611308Santhony.gutierrez@amd.com ipc = numInstrExecuted / totalCycles; 153711308Santhony.gutierrez@amd.com vpc = numVecOpsExecuted / totalCycles; 153811308Santhony.gutierrez@amd.com 153911308Santhony.gutierrez@amd.com numTimesWgBlockedDueVgprAlloc 154011308Santhony.gutierrez@amd.com .name(name() + ".times_wg_blocked_due_vgpr_alloc") 154111308Santhony.gutierrez@amd.com .desc("Number of times WGs are blocked due to VGPR allocation per SIMD") 154211308Santhony.gutierrez@amd.com ; 154311308Santhony.gutierrez@amd.com 154411308Santhony.gutierrez@amd.com dynamicGMemInstrCnt 154511308Santhony.gutierrez@amd.com .name(name() + ".global_mem_instr_cnt") 154611308Santhony.gutierrez@amd.com .desc("dynamic global memory instructions count") 154711308Santhony.gutierrez@amd.com ; 154811308Santhony.gutierrez@amd.com 154911308Santhony.gutierrez@amd.com dynamicLMemInstrCnt 155011308Santhony.gutierrez@amd.com .name(name() + ".local_mem_instr_cnt") 155111308Santhony.gutierrez@amd.com .desc("dynamic local memory intruction count") 155211308Santhony.gutierrez@amd.com ; 155311308Santhony.gutierrez@amd.com 155411308Santhony.gutierrez@amd.com numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt - 155511308Santhony.gutierrez@amd.com dynamicLMemInstrCnt; 155611308Santhony.gutierrez@amd.com 155711308Santhony.gutierrez@amd.com completedWfs 155811308Santhony.gutierrez@amd.com .name(name() + ".num_completed_wfs") 155911308Santhony.gutierrez@amd.com .desc("number of completed wavefronts") 156011308Santhony.gutierrez@amd.com ; 156111308Santhony.gutierrez@amd.com 156211308Santhony.gutierrez@amd.com numCASOps 156311308Santhony.gutierrez@amd.com .name(name() + ".num_CAS_ops") 156411308Santhony.gutierrez@amd.com .desc("number of compare and swap operations") 156511308Santhony.gutierrez@amd.com ; 156611308Santhony.gutierrez@amd.com 156711308Santhony.gutierrez@amd.com numFailedCASOps 156811308Santhony.gutierrez@amd.com .name(name() + ".num_failed_CAS_ops") 156911308Santhony.gutierrez@amd.com .desc("number of compare and swap operations that failed") 157011308Santhony.gutierrez@amd.com ; 157111308Santhony.gutierrez@amd.com 157211308Santhony.gutierrez@amd.com // register stats of pipeline stages 157311308Santhony.gutierrez@amd.com fetchStage.regStats(); 157411308Santhony.gutierrez@amd.com scoreboardCheckStage.regStats(); 157511308Santhony.gutierrez@amd.com scheduleStage.regStats(); 157611308Santhony.gutierrez@amd.com execStage.regStats(); 157711308Santhony.gutierrez@amd.com 157811308Santhony.gutierrez@amd.com // register stats of memory pipeline 157911308Santhony.gutierrez@amd.com globalMemoryPipe.regStats(); 158011308Santhony.gutierrez@amd.com localMemoryPipe.regStats(); 158111308Santhony.gutierrez@amd.com} 158211308Santhony.gutierrez@amd.com 158311308Santhony.gutierrez@amd.comvoid 158411308Santhony.gutierrez@amd.comComputeUnit::updatePageDivergenceDist(Addr addr) 158511308Santhony.gutierrez@amd.com{ 158611308Santhony.gutierrez@amd.com Addr virt_page_addr = roundDown(addr, TheISA::PageBytes); 158711308Santhony.gutierrez@amd.com 158811308Santhony.gutierrez@amd.com if (!pagesTouched.count(virt_page_addr)) 158911308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr] = 1; 159011308Santhony.gutierrez@amd.com else 159111308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr]++; 159211308Santhony.gutierrez@amd.com} 159311308Santhony.gutierrez@amd.com 159411308Santhony.gutierrez@amd.comvoid 159511308Santhony.gutierrez@amd.comComputeUnit::CUExitCallback::process() 159611308Santhony.gutierrez@amd.com{ 159711308Santhony.gutierrez@amd.com if (computeUnit->countPages) { 159811308Santhony.gutierrez@amd.com std::ostream *page_stat_file = 159911364Sandreas.hansson@arm.com simout.create(computeUnit->name().c_str())->stream(); 160011308Santhony.gutierrez@amd.com 160111308Santhony.gutierrez@amd.com *page_stat_file << "page, wavefront accesses, workitem accesses" << 160211308Santhony.gutierrez@amd.com std::endl; 160311308Santhony.gutierrez@amd.com 160411308Santhony.gutierrez@amd.com for (auto iter : computeUnit->pageAccesses) { 160511308Santhony.gutierrez@amd.com *page_stat_file << std::hex << iter.first << ","; 160611308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.first << ","; 160711308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.second << std::endl; 160811308Santhony.gutierrez@amd.com } 160911308Santhony.gutierrez@amd.com } 161011308Santhony.gutierrez@amd.com } 161111308Santhony.gutierrez@amd.com 161211308Santhony.gutierrez@amd.combool 161311308Santhony.gutierrez@amd.comComputeUnit::isDone() const 161411308Santhony.gutierrez@amd.com{ 161511308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 161611308Santhony.gutierrez@amd.com if (!isSimdDone(i)) { 161711308Santhony.gutierrez@amd.com return false; 161811308Santhony.gutierrez@amd.com } 161911308Santhony.gutierrez@amd.com } 162011308Santhony.gutierrez@amd.com 162111308Santhony.gutierrez@amd.com bool glbMemBusRdy = true; 162211308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 162311308Santhony.gutierrez@amd.com glbMemBusRdy &= vrfToGlobalMemPipeBus[j].rdy(); 162411308Santhony.gutierrez@amd.com } 162511308Santhony.gutierrez@amd.com bool locMemBusRdy = true; 162611308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 162711308Santhony.gutierrez@amd.com locMemBusRdy &= vrfToLocalMemPipeBus[j].rdy(); 162811308Santhony.gutierrez@amd.com } 162911308Santhony.gutierrez@amd.com 163011308Santhony.gutierrez@amd.com if (!globalMemoryPipe.isGMLdRespFIFOWrRdy() || 163111308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMStRespFIFOWrRdy() || 163211308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMReqFIFOWrRdy() || !localMemoryPipe.isLMReqFIFOWrRdy() 163311308Santhony.gutierrez@amd.com || !localMemoryPipe.isLMRespFIFOWrRdy() || !locMemToVrfBus.rdy() || 163411308Santhony.gutierrez@amd.com !glbMemToVrfBus.rdy() || !locMemBusRdy || !glbMemBusRdy) { 163511308Santhony.gutierrez@amd.com return false; 163611308Santhony.gutierrez@amd.com } 163711308Santhony.gutierrez@amd.com 163811308Santhony.gutierrez@amd.com return true; 163911308Santhony.gutierrez@amd.com} 164011308Santhony.gutierrez@amd.com 164111308Santhony.gutierrez@amd.comint32_t 164211308Santhony.gutierrez@amd.comComputeUnit::getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const 164311308Santhony.gutierrez@amd.com{ 164411308Santhony.gutierrez@amd.com return lds.getRefCounter(dispatchId, wgId); 164511308Santhony.gutierrez@amd.com} 164611308Santhony.gutierrez@amd.com 164711308Santhony.gutierrez@amd.combool 164811308Santhony.gutierrez@amd.comComputeUnit::isSimdDone(uint32_t simdId) const 164911308Santhony.gutierrez@amd.com{ 165011308Santhony.gutierrez@amd.com assert(simdId < numSIMDs); 165111308Santhony.gutierrez@amd.com 165211308Santhony.gutierrez@amd.com for (int i=0; i < numGlbMemUnits; ++i) { 165311308Santhony.gutierrez@amd.com if (!vrfToGlobalMemPipeBus[i].rdy()) 165411308Santhony.gutierrez@amd.com return false; 165511308Santhony.gutierrez@amd.com } 165611308Santhony.gutierrez@amd.com for (int i=0; i < numLocMemUnits; ++i) { 165711308Santhony.gutierrez@amd.com if (!vrfToLocalMemPipeBus[i].rdy()) 165811308Santhony.gutierrez@amd.com return false; 165911308Santhony.gutierrez@amd.com } 166011308Santhony.gutierrez@amd.com if (!aluPipe[simdId].rdy()) { 166111308Santhony.gutierrez@amd.com return false; 166211308Santhony.gutierrez@amd.com } 166311308Santhony.gutierrez@amd.com 166411308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf){ 166511308Santhony.gutierrez@amd.com if (wfList[simdId][i_wf]->status != Wavefront::S_STOPPED) { 166611308Santhony.gutierrez@amd.com return false; 166711308Santhony.gutierrez@amd.com } 166811308Santhony.gutierrez@amd.com } 166911308Santhony.gutierrez@amd.com 167011308Santhony.gutierrez@amd.com return true; 167111308Santhony.gutierrez@amd.com} 167211308Santhony.gutierrez@amd.com 167311308Santhony.gutierrez@amd.com/** 167411308Santhony.gutierrez@amd.com * send a general request to the LDS 167511308Santhony.gutierrez@amd.com * make sure to look at the return value here as your request might be 167611308Santhony.gutierrez@amd.com * NACK'd and returning false means that you have to have some backup plan 167711308Santhony.gutierrez@amd.com */ 167811308Santhony.gutierrez@amd.combool 167911308Santhony.gutierrez@amd.comComputeUnit::sendToLds(GPUDynInstPtr gpuDynInst) 168011308Santhony.gutierrez@amd.com{ 168111308Santhony.gutierrez@amd.com // this is just a request to carry the GPUDynInstPtr 168211308Santhony.gutierrez@amd.com // back and forth 168311308Santhony.gutierrez@amd.com Request *newRequest = new Request(); 168411308Santhony.gutierrez@amd.com newRequest->setPaddr(0x0); 168511308Santhony.gutierrez@amd.com 168611308Santhony.gutierrez@amd.com // ReadReq is not evaluted by the LDS but the Packet ctor requires this 168711308Santhony.gutierrez@amd.com PacketPtr newPacket = new Packet(newRequest, MemCmd::ReadReq); 168811308Santhony.gutierrez@amd.com 168911308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 169011308Santhony.gutierrez@amd.com newPacket->senderState = new LDSPort::SenderState(gpuDynInst); 169111308Santhony.gutierrez@amd.com 169211308Santhony.gutierrez@amd.com return ldsPort->sendTimingReq(newPacket); 169311308Santhony.gutierrez@amd.com} 169411308Santhony.gutierrez@amd.com 169511308Santhony.gutierrez@amd.com/** 169611308Santhony.gutierrez@amd.com * get the result of packets sent to the LDS when they return 169711308Santhony.gutierrez@amd.com */ 169811308Santhony.gutierrez@amd.combool 169911308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvTimingResp(PacketPtr packet) 170011308Santhony.gutierrez@amd.com{ 170111308Santhony.gutierrez@amd.com const ComputeUnit::LDSPort::SenderState *senderState = 170211308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState *>(packet->senderState); 170311308Santhony.gutierrez@amd.com 170411308Santhony.gutierrez@amd.com fatal_if(!senderState, "did not get the right sort of sender state"); 170511308Santhony.gutierrez@amd.com 170611308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = senderState->getMemInst(); 170711308Santhony.gutierrez@amd.com 170811308Santhony.gutierrez@amd.com delete packet->senderState; 170911308Santhony.gutierrez@amd.com delete packet->req; 171011308Santhony.gutierrez@amd.com delete packet; 171111308Santhony.gutierrez@amd.com 171211308Santhony.gutierrez@amd.com computeUnit->localMemoryPipe.getLMRespFIFO().push(gpuDynInst); 171311308Santhony.gutierrez@amd.com return true; 171411308Santhony.gutierrez@amd.com} 171511308Santhony.gutierrez@amd.com 171611308Santhony.gutierrez@amd.com/** 171711308Santhony.gutierrez@amd.com * attempt to send this packet, either the port is already stalled, the request 171811308Santhony.gutierrez@amd.com * is nack'd and must stall or the request goes through 171911308Santhony.gutierrez@amd.com * when a request cannot be sent, add it to the retries queue 172011308Santhony.gutierrez@amd.com */ 172111308Santhony.gutierrez@amd.combool 172211308Santhony.gutierrez@amd.comComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt) 172311308Santhony.gutierrez@amd.com{ 172411308Santhony.gutierrez@amd.com ComputeUnit::LDSPort::SenderState *sender_state = 172511308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState); 172611308Santhony.gutierrez@amd.com fatal_if(!sender_state, "packet without a valid sender state"); 172711308Santhony.gutierrez@amd.com 172811308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = sender_state->getMemInst(); 172911308Santhony.gutierrez@amd.com 173011308Santhony.gutierrez@amd.com if (isStalled()) { 173111308Santhony.gutierrez@amd.com fatal_if(retries.empty(), "must have retries waiting to be stalled"); 173211308Santhony.gutierrez@amd.com 173311308Santhony.gutierrez@amd.com retries.push(pkt); 173411308Santhony.gutierrez@amd.com 173511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: LDS send failed!\n", 173611308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 173711308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 173811308Santhony.gutierrez@amd.com return false; 173911308Santhony.gutierrez@amd.com } else if (!MasterPort::sendTimingReq(pkt)) { 174011308Santhony.gutierrez@amd.com // need to stall the LDS port until a recvReqRetry() is received 174111308Santhony.gutierrez@amd.com // this indicates that there is more space 174211308Santhony.gutierrez@amd.com stallPort(); 174311308Santhony.gutierrez@amd.com retries.push(pkt); 174411308Santhony.gutierrez@amd.com 174511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req failed!\n", 174611308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 174711308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 174811308Santhony.gutierrez@amd.com return false; 174911308Santhony.gutierrez@amd.com } else { 175011308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req sent!\n", 175111308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 175211308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 175311308Santhony.gutierrez@amd.com return true; 175411308Santhony.gutierrez@amd.com } 175511308Santhony.gutierrez@amd.com} 175611308Santhony.gutierrez@amd.com 175711308Santhony.gutierrez@amd.com/** 175811308Santhony.gutierrez@amd.com * the bus is telling the port that there is now space so retrying stalled 175911308Santhony.gutierrez@amd.com * requests should work now 176011308Santhony.gutierrez@amd.com * this allows the port to have a request be nack'd and then have the receiver 176111308Santhony.gutierrez@amd.com * say when there is space, rather than simply retrying the send every cycle 176211308Santhony.gutierrez@amd.com */ 176311308Santhony.gutierrez@amd.comvoid 176411308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvReqRetry() 176511308Santhony.gutierrez@amd.com{ 176611308Santhony.gutierrez@amd.com auto queueSize = retries.size(); 176711308Santhony.gutierrez@amd.com 176811308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: LDSPort recvReqRetry - %d pending requests\n", 176911308Santhony.gutierrez@amd.com computeUnit->cu_id, queueSize); 177011308Santhony.gutierrez@amd.com 177111308Santhony.gutierrez@amd.com fatal_if(queueSize < 1, 177211308Santhony.gutierrez@amd.com "why was there a recvReqRetry() with no pending reqs?"); 177311308Santhony.gutierrez@amd.com fatal_if(!isStalled(), 177411308Santhony.gutierrez@amd.com "recvReqRetry() happened when the port was not stalled"); 177511308Santhony.gutierrez@amd.com 177611308Santhony.gutierrez@amd.com unstallPort(); 177711308Santhony.gutierrez@amd.com 177811308Santhony.gutierrez@amd.com while (!retries.empty()) { 177911308Santhony.gutierrez@amd.com PacketPtr packet = retries.front(); 178011308Santhony.gutierrez@amd.com 178111308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id); 178211308Santhony.gutierrez@amd.com 178311308Santhony.gutierrez@amd.com if (!MasterPort::sendTimingReq(packet)) { 178411308Santhony.gutierrez@amd.com // Stall port 178511308Santhony.gutierrez@amd.com stallPort(); 178611308Santhony.gutierrez@amd.com DPRINTF(GPUPort, ": LDS send failed again\n"); 178711308Santhony.gutierrez@amd.com break; 178811308Santhony.gutierrez@amd.com } else { 178911308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": LDS send successful\n"); 179011308Santhony.gutierrez@amd.com retries.pop(); 179111308Santhony.gutierrez@amd.com } 179211308Santhony.gutierrez@amd.com } 179311308Santhony.gutierrez@amd.com} 1794