compute_unit.cc revision 11435
111308Santhony.gutierrez@amd.com/* 211308Santhony.gutierrez@amd.com * Copyright (c) 2011-2015 Advanced Micro Devices, Inc. 311308Santhony.gutierrez@amd.com * All rights reserved. 411308Santhony.gutierrez@amd.com * 511308Santhony.gutierrez@amd.com * For use for simulation and test purposes only 611308Santhony.gutierrez@amd.com * 711308Santhony.gutierrez@amd.com * Redistribution and use in source and binary forms, with or without 811308Santhony.gutierrez@amd.com * modification, are permitted provided that the following conditions are met: 911308Santhony.gutierrez@amd.com * 1011308Santhony.gutierrez@amd.com * 1. Redistributions of source code must retain the above copyright notice, 1111308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer. 1211308Santhony.gutierrez@amd.com * 1311308Santhony.gutierrez@amd.com * 2. Redistributions in binary form must reproduce the above copyright notice, 1411308Santhony.gutierrez@amd.com * this list of conditions and the following disclaimer in the documentation 1511308Santhony.gutierrez@amd.com * and/or other materials provided with the distribution. 1611308Santhony.gutierrez@amd.com * 1711308Santhony.gutierrez@amd.com * 3. Neither the name of the copyright holder nor the names of its contributors 1811308Santhony.gutierrez@amd.com * may be used to endorse or promote products derived from this software 1911308Santhony.gutierrez@amd.com * without specific prior written permission. 2011308Santhony.gutierrez@amd.com * 2111308Santhony.gutierrez@amd.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2211308Santhony.gutierrez@amd.com * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2311308Santhony.gutierrez@amd.com * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2411308Santhony.gutierrez@amd.com * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 2511308Santhony.gutierrez@amd.com * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2611308Santhony.gutierrez@amd.com * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2711308Santhony.gutierrez@amd.com * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2811308Santhony.gutierrez@amd.com * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2911308Santhony.gutierrez@amd.com * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3011308Santhony.gutierrez@amd.com * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3111308Santhony.gutierrez@amd.com * POSSIBILITY OF SUCH DAMAGE. 3211308Santhony.gutierrez@amd.com * 3311308Santhony.gutierrez@amd.com * Author: John Kalamatianos, Anthony Gutierrez 3411308Santhony.gutierrez@amd.com */ 3511308Santhony.gutierrez@amd.com 3611308Santhony.gutierrez@amd.com#include "gpu-compute/compute_unit.hh" 3711308Santhony.gutierrez@amd.com 3811308Santhony.gutierrez@amd.com#include "base/output.hh" 3911308Santhony.gutierrez@amd.com#include "debug/GPUDisp.hh" 4011308Santhony.gutierrez@amd.com#include "debug/GPUExec.hh" 4111308Santhony.gutierrez@amd.com#include "debug/GPUFetch.hh" 4211308Santhony.gutierrez@amd.com#include "debug/GPUMem.hh" 4311308Santhony.gutierrez@amd.com#include "debug/GPUPort.hh" 4411308Santhony.gutierrez@amd.com#include "debug/GPUPrefetch.hh" 4511308Santhony.gutierrez@amd.com#include "debug/GPUSync.hh" 4611308Santhony.gutierrez@amd.com#include "debug/GPUTLB.hh" 4711308Santhony.gutierrez@amd.com#include "gpu-compute/dispatcher.hh" 4811308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_dyn_inst.hh" 4911308Santhony.gutierrez@amd.com#include "gpu-compute/gpu_static_inst.hh" 5011308Santhony.gutierrez@amd.com#include "gpu-compute/ndrange.hh" 5111308Santhony.gutierrez@amd.com#include "gpu-compute/shader.hh" 5211308Santhony.gutierrez@amd.com#include "gpu-compute/simple_pool_manager.hh" 5311308Santhony.gutierrez@amd.com#include "gpu-compute/vector_register_file.hh" 5411308Santhony.gutierrez@amd.com#include "gpu-compute/wavefront.hh" 5511308Santhony.gutierrez@amd.com#include "mem/page_table.hh" 5611308Santhony.gutierrez@amd.com#include "sim/process.hh" 5711308Santhony.gutierrez@amd.com 5811308Santhony.gutierrez@amd.comComputeUnit::ComputeUnit(const Params *p) : MemObject(p), fetchStage(p), 5911308Santhony.gutierrez@amd.com scoreboardCheckStage(p), scheduleStage(p), execStage(p), 6011308Santhony.gutierrez@amd.com globalMemoryPipe(p), localMemoryPipe(p), rrNextMemID(0), rrNextALUWp(0), 6111308Santhony.gutierrez@amd.com cu_id(p->cu_id), vrf(p->vector_register_file), numSIMDs(p->num_SIMDs), 6211308Santhony.gutierrez@amd.com spBypassPipeLength(p->spbypass_pipe_length), 6311308Santhony.gutierrez@amd.com dpBypassPipeLength(p->dpbypass_pipe_length), 6411308Santhony.gutierrez@amd.com issuePeriod(p->issue_period), 6511308Santhony.gutierrez@amd.com numGlbMemUnits(p->num_global_mem_pipes), 6611308Santhony.gutierrez@amd.com numLocMemUnits(p->num_shared_mem_pipes), 6711308Santhony.gutierrez@amd.com perLaneTLB(p->perLaneTLB), prefetchDepth(p->prefetch_depth), 6811308Santhony.gutierrez@amd.com prefetchStride(p->prefetch_stride), prefetchType(p->prefetch_prev_type), 6911308Santhony.gutierrez@amd.com xact_cas_mode(p->xactCasMode), debugSegFault(p->debugSegFault), 7011308Santhony.gutierrez@amd.com functionalTLB(p->functionalTLB), localMemBarrier(p->localMemBarrier), 7111308Santhony.gutierrez@amd.com countPages(p->countPages), barrier_id(0), 7211308Santhony.gutierrez@amd.com vrfToCoalescerBusWidth(p->vrf_to_coalescer_bus_width), 7311308Santhony.gutierrez@amd.com coalescerToVrfBusWidth(p->coalescer_to_vrf_bus_width), 7411308Santhony.gutierrez@amd.com req_tick_latency(p->mem_req_latency * p->clk_domain->clockPeriod()), 7511308Santhony.gutierrez@amd.com resp_tick_latency(p->mem_resp_latency * p->clk_domain->clockPeriod()), 7611308Santhony.gutierrez@amd.com _masterId(p->system->getMasterId(name() + ".ComputeUnit")), 7711308Santhony.gutierrez@amd.com lds(*p->localDataStore), globalSeqNum(0), wavefrontSize(p->wfSize) 7811308Santhony.gutierrez@amd.com{ 7911308Santhony.gutierrez@amd.com // this check will be eliminated once we have wavefront size support added 8011308Santhony.gutierrez@amd.com fatal_if(p->wfSize != VSZ, "Wavefront size parameter does not match VSZ"); 8111308Santhony.gutierrez@amd.com // calculate how many cycles a vector load or store will need to transfer 8211308Santhony.gutierrez@amd.com // its data over the corresponding buses 8311308Santhony.gutierrez@amd.com numCyclesPerStoreTransfer = (uint32_t)ceil((double)(VSZ * sizeof(uint32_t)) 8411308Santhony.gutierrez@amd.com / (double)vrfToCoalescerBusWidth); 8511308Santhony.gutierrez@amd.com 8611308Santhony.gutierrez@amd.com numCyclesPerLoadTransfer = (VSZ * sizeof(uint32_t)) 8711308Santhony.gutierrez@amd.com / coalescerToVrfBusWidth; 8811308Santhony.gutierrez@amd.com 8911308Santhony.gutierrez@amd.com lastVaddrWF.resize(numSIMDs); 9011308Santhony.gutierrez@amd.com wfList.resize(numSIMDs); 9111308Santhony.gutierrez@amd.com 9211308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 9311308Santhony.gutierrez@amd.com lastVaddrWF[j].resize(p->n_wf); 9411308Santhony.gutierrez@amd.com 9511308Santhony.gutierrez@amd.com for (int i = 0; i < p->n_wf; ++i) { 9611308Santhony.gutierrez@amd.com lastVaddrWF[j][i].resize(VSZ); 9711308Santhony.gutierrez@amd.com 9811308Santhony.gutierrez@amd.com wfList[j].push_back(p->wavefronts[j * p->n_wf + i]); 9911308Santhony.gutierrez@amd.com wfList[j][i]->setParent(this); 10011308Santhony.gutierrez@amd.com 10111308Santhony.gutierrez@amd.com for (int k = 0; k < VSZ; ++k) { 10211308Santhony.gutierrez@amd.com lastVaddrWF[j][i][k] = 0; 10311308Santhony.gutierrez@amd.com } 10411308Santhony.gutierrez@amd.com } 10511308Santhony.gutierrez@amd.com } 10611308Santhony.gutierrez@amd.com 10711308Santhony.gutierrez@amd.com lastVaddrPhase.resize(numSIMDs); 10811308Santhony.gutierrez@amd.com 10911308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 11011308Santhony.gutierrez@amd.com lastVaddrPhase[i] = LastVaddrWave(); 11111308Santhony.gutierrez@amd.com } 11211308Santhony.gutierrez@amd.com 11311308Santhony.gutierrez@amd.com lastVaddrCU = LastVaddrWave(); 11411308Santhony.gutierrez@amd.com 11511308Santhony.gutierrez@amd.com lds.setParent(this); 11611308Santhony.gutierrez@amd.com 11711308Santhony.gutierrez@amd.com if (p->execPolicy == "OLDEST-FIRST") { 11811308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::OLDEST; 11911308Santhony.gutierrez@amd.com } else if (p->execPolicy == "ROUND-ROBIN") { 12011308Santhony.gutierrez@amd.com exec_policy = EXEC_POLICY::RR; 12111308Santhony.gutierrez@amd.com } else { 12211308Santhony.gutierrez@amd.com fatal("Invalid WF execution policy (CU)\n"); 12311308Santhony.gutierrez@amd.com } 12411308Santhony.gutierrez@amd.com 12511308Santhony.gutierrez@amd.com memPort.resize(VSZ); 12611308Santhony.gutierrez@amd.com 12711308Santhony.gutierrez@amd.com // resize the tlbPort vectorArray 12811308Santhony.gutierrez@amd.com int tlbPort_width = perLaneTLB ? VSZ : 1; 12911308Santhony.gutierrez@amd.com tlbPort.resize(tlbPort_width); 13011308Santhony.gutierrez@amd.com 13111308Santhony.gutierrez@amd.com cuExitCallback = new CUExitCallback(this); 13211308Santhony.gutierrez@amd.com registerExitCallback(cuExitCallback); 13311308Santhony.gutierrez@amd.com 13411308Santhony.gutierrez@amd.com xactCasLoadMap.clear(); 13511308Santhony.gutierrez@amd.com lastExecCycle.resize(numSIMDs, 0); 13611308Santhony.gutierrez@amd.com 13711308Santhony.gutierrez@amd.com for (int i = 0; i < vrf.size(); ++i) { 13811308Santhony.gutierrez@amd.com vrf[i]->setParent(this); 13911308Santhony.gutierrez@amd.com } 14011308Santhony.gutierrez@amd.com 14111308Santhony.gutierrez@amd.com numVecRegsPerSimd = vrf[0]->numRegs(); 14211308Santhony.gutierrez@amd.com} 14311308Santhony.gutierrez@amd.com 14411308Santhony.gutierrez@amd.comComputeUnit::~ComputeUnit() 14511308Santhony.gutierrez@amd.com{ 14611308Santhony.gutierrez@amd.com // Delete wavefront slots 14711308Santhony.gutierrez@amd.com 14811308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) 14911308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 15011308Santhony.gutierrez@amd.com delete wfList[j][i]; 15111308Santhony.gutierrez@amd.com } 15211308Santhony.gutierrez@amd.com 15311308Santhony.gutierrez@amd.com readyList.clear(); 15411308Santhony.gutierrez@amd.com waveStatusList.clear(); 15511308Santhony.gutierrez@amd.com dispatchList.clear(); 15611308Santhony.gutierrez@amd.com vectorAluInstAvail.clear(); 15711308Santhony.gutierrez@amd.com delete cuExitCallback; 15811308Santhony.gutierrez@amd.com delete ldsPort; 15911308Santhony.gutierrez@amd.com} 16011308Santhony.gutierrez@amd.com 16111308Santhony.gutierrez@amd.comvoid 16211308Santhony.gutierrez@amd.comComputeUnit::FillKernelState(Wavefront *w, NDRange *ndr) 16311308Santhony.gutierrez@amd.com{ 16411308Santhony.gutierrez@amd.com w->resizeRegFiles(ndr->q.cRegCount, ndr->q.sRegCount, ndr->q.dRegCount); 16511308Santhony.gutierrez@amd.com 16611308Santhony.gutierrez@amd.com w->workgroupsz[0] = ndr->q.wgSize[0]; 16711308Santhony.gutierrez@amd.com w->workgroupsz[1] = ndr->q.wgSize[1]; 16811308Santhony.gutierrez@amd.com w->workgroupsz[2] = ndr->q.wgSize[2]; 16911308Santhony.gutierrez@amd.com w->wg_sz = w->workgroupsz[0] * w->workgroupsz[1] * w->workgroupsz[2]; 17011308Santhony.gutierrez@amd.com w->gridsz[0] = ndr->q.gdSize[0]; 17111308Santhony.gutierrez@amd.com w->gridsz[1] = ndr->q.gdSize[1]; 17211308Santhony.gutierrez@amd.com w->gridsz[2] = ndr->q.gdSize[2]; 17311308Santhony.gutierrez@amd.com w->kernelArgs = ndr->q.args; 17411308Santhony.gutierrez@amd.com w->privSizePerItem = ndr->q.privMemPerItem; 17511308Santhony.gutierrez@amd.com w->spillSizePerItem = ndr->q.spillMemPerItem; 17611308Santhony.gutierrez@amd.com w->roBase = ndr->q.roMemStart; 17711308Santhony.gutierrez@amd.com w->roSize = ndr->q.roMemTotal; 17811308Santhony.gutierrez@amd.com} 17911308Santhony.gutierrez@amd.com 18011308Santhony.gutierrez@amd.comvoid 18111308Santhony.gutierrez@amd.comComputeUnit::InitializeWFContext(WFContext *wfCtx, NDRange *ndr, int cnt, 18211308Santhony.gutierrez@amd.com int trueWgSize[], int trueWgSizeTotal, 18311308Santhony.gutierrez@amd.com LdsChunk *ldsChunk, uint64_t origSpillMemStart) 18411308Santhony.gutierrez@amd.com{ 18511308Santhony.gutierrez@amd.com wfCtx->cnt = cnt; 18611308Santhony.gutierrez@amd.com 18711308Santhony.gutierrez@amd.com VectorMask init_mask; 18811308Santhony.gutierrez@amd.com init_mask.reset(); 18911308Santhony.gutierrez@amd.com 19011308Santhony.gutierrez@amd.com for (int k = 0; k < VSZ; ++k) { 19111308Santhony.gutierrez@amd.com if (k + cnt * VSZ < trueWgSizeTotal) 19211308Santhony.gutierrez@amd.com init_mask[k] = 1; 19311308Santhony.gutierrez@amd.com } 19411308Santhony.gutierrez@amd.com 19511308Santhony.gutierrez@amd.com wfCtx->init_mask = init_mask.to_ullong(); 19611308Santhony.gutierrez@amd.com wfCtx->exec_mask = init_mask.to_ullong(); 19711308Santhony.gutierrez@amd.com 19811308Santhony.gutierrez@amd.com for (int i = 0; i < VSZ; ++i) { 19911308Santhony.gutierrez@amd.com wfCtx->bar_cnt[i] = 0; 20011308Santhony.gutierrez@amd.com } 20111308Santhony.gutierrez@amd.com 20211308Santhony.gutierrez@amd.com wfCtx->max_bar_cnt = 0; 20311308Santhony.gutierrez@amd.com wfCtx->old_barrier_cnt = 0; 20411308Santhony.gutierrez@amd.com wfCtx->barrier_cnt = 0; 20511308Santhony.gutierrez@amd.com 20611308Santhony.gutierrez@amd.com wfCtx->privBase = ndr->q.privMemStart; 20711308Santhony.gutierrez@amd.com ndr->q.privMemStart += ndr->q.privMemPerItem * VSZ; 20811308Santhony.gutierrez@amd.com 20911308Santhony.gutierrez@amd.com wfCtx->spillBase = ndr->q.spillMemStart; 21011308Santhony.gutierrez@amd.com ndr->q.spillMemStart += ndr->q.spillMemPerItem * VSZ; 21111308Santhony.gutierrez@amd.com 21211308Santhony.gutierrez@amd.com wfCtx->pc = 0; 21311308Santhony.gutierrez@amd.com wfCtx->rpc = UINT32_MAX; 21411308Santhony.gutierrez@amd.com 21511308Santhony.gutierrez@amd.com // set the wavefront context to have a pointer to this section of the LDS 21611308Santhony.gutierrez@amd.com wfCtx->ldsChunk = ldsChunk; 21711308Santhony.gutierrez@amd.com 21811308Santhony.gutierrez@amd.com // WG state 21911308Santhony.gutierrez@amd.com wfCtx->wg_id = ndr->globalWgId; 22011308Santhony.gutierrez@amd.com wfCtx->barrier_id = barrier_id; 22111308Santhony.gutierrez@amd.com 22211308Santhony.gutierrez@amd.com // Kernel wide state 22311308Santhony.gutierrez@amd.com wfCtx->ndr = ndr; 22411308Santhony.gutierrez@amd.com} 22511308Santhony.gutierrez@amd.com 22611308Santhony.gutierrez@amd.comvoid 22711308Santhony.gutierrez@amd.comComputeUnit::updateEvents() { 22811308Santhony.gutierrez@amd.com 22911308Santhony.gutierrez@amd.com if (!timestampVec.empty()) { 23011308Santhony.gutierrez@amd.com uint32_t vecSize = timestampVec.size(); 23111308Santhony.gutierrez@amd.com uint32_t i = 0; 23211308Santhony.gutierrez@amd.com while (i < vecSize) { 23311308Santhony.gutierrez@amd.com if (timestampVec[i] <= shader->tick_cnt) { 23411308Santhony.gutierrez@amd.com std::pair<uint32_t, uint32_t> regInfo = regIdxVec[i]; 23511308Santhony.gutierrez@amd.com vrf[regInfo.first]->markReg(regInfo.second, sizeof(uint32_t), 23611308Santhony.gutierrez@amd.com statusVec[i]); 23711308Santhony.gutierrez@amd.com timestampVec.erase(timestampVec.begin() + i); 23811308Santhony.gutierrez@amd.com regIdxVec.erase(regIdxVec.begin() + i); 23911308Santhony.gutierrez@amd.com statusVec.erase(statusVec.begin() + i); 24011308Santhony.gutierrez@amd.com --vecSize; 24111308Santhony.gutierrez@amd.com --i; 24211308Santhony.gutierrez@amd.com } 24311308Santhony.gutierrez@amd.com ++i; 24411308Santhony.gutierrez@amd.com } 24511308Santhony.gutierrez@amd.com } 24611308Santhony.gutierrez@amd.com 24711308Santhony.gutierrez@amd.com for (int i = 0; i< numSIMDs; ++i) { 24811308Santhony.gutierrez@amd.com vrf[i]->updateEvents(); 24911308Santhony.gutierrez@amd.com } 25011308Santhony.gutierrez@amd.com} 25111308Santhony.gutierrez@amd.com 25211308Santhony.gutierrez@amd.com 25311308Santhony.gutierrez@amd.comvoid 25411308Santhony.gutierrez@amd.comComputeUnit::StartWF(Wavefront *w, WFContext *wfCtx, int trueWgSize[], 25511308Santhony.gutierrez@amd.com int trueWgSizeTotal) 25611308Santhony.gutierrez@amd.com{ 25711308Santhony.gutierrez@amd.com static int _n_wave = 0; 25811308Santhony.gutierrez@amd.com int cnt = wfCtx->cnt; 25911308Santhony.gutierrez@amd.com NDRange *ndr = wfCtx->ndr; 26011308Santhony.gutierrez@amd.com 26111308Santhony.gutierrez@amd.com // Fill in Kernel state 26211308Santhony.gutierrez@amd.com FillKernelState(w, ndr); 26311308Santhony.gutierrez@amd.com 26411308Santhony.gutierrez@amd.com w->kern_id = ndr->dispatchId; 26511308Santhony.gutierrez@amd.com w->dynwaveid = cnt; 26611308Santhony.gutierrez@amd.com w->init_mask = wfCtx->init_mask; 26711308Santhony.gutierrez@amd.com 26811308Santhony.gutierrez@amd.com for (int k = 0; k < VSZ; ++k) { 26911308Santhony.gutierrez@amd.com w->workitemid[0][k] = (k+cnt*VSZ) % trueWgSize[0]; 27011308Santhony.gutierrez@amd.com w->workitemid[1][k] = ((k + cnt * VSZ) / trueWgSize[0]) % trueWgSize[1]; 27111308Santhony.gutierrez@amd.com w->workitemid[2][k] = (k + cnt * VSZ) / (trueWgSize[0] * trueWgSize[1]); 27211308Santhony.gutierrez@amd.com 27311308Santhony.gutierrez@amd.com w->workitemFlatId[k] = w->workitemid[2][k] * trueWgSize[0] * 27411308Santhony.gutierrez@amd.com trueWgSize[1] + w->workitemid[1][k] * trueWgSize[0] + 27511308Santhony.gutierrez@amd.com w->workitemid[0][k]; 27611308Santhony.gutierrez@amd.com } 27711308Santhony.gutierrez@amd.com 27811308Santhony.gutierrez@amd.com w->old_barrier_cnt = wfCtx->old_barrier_cnt; 27911308Santhony.gutierrez@amd.com w->barrier_cnt = wfCtx->barrier_cnt; 28011308Santhony.gutierrez@amd.com w->barrier_slots = divCeil(trueWgSizeTotal, VSZ); 28111308Santhony.gutierrez@amd.com 28211308Santhony.gutierrez@amd.com for (int i = 0; i < VSZ; ++i) { 28311308Santhony.gutierrez@amd.com w->bar_cnt[i] = wfCtx->bar_cnt[i]; 28411308Santhony.gutierrez@amd.com } 28511308Santhony.gutierrez@amd.com 28611308Santhony.gutierrez@amd.com w->max_bar_cnt = wfCtx->max_bar_cnt; 28711308Santhony.gutierrez@amd.com w->privBase = wfCtx->privBase; 28811308Santhony.gutierrez@amd.com w->spillBase = wfCtx->spillBase; 28911308Santhony.gutierrez@amd.com 29011308Santhony.gutierrez@amd.com w->pushToReconvergenceStack(wfCtx->pc, wfCtx->rpc, wfCtx->exec_mask); 29111308Santhony.gutierrez@amd.com 29211308Santhony.gutierrez@amd.com // WG state 29311308Santhony.gutierrez@amd.com w->wg_id = wfCtx->wg_id; 29411308Santhony.gutierrez@amd.com w->dispatchid = wfCtx->ndr->dispatchId; 29511308Santhony.gutierrez@amd.com w->workgroupid[0] = w->wg_id % ndr->numWg[0]; 29611308Santhony.gutierrez@amd.com w->workgroupid[1] = (w->wg_id / ndr->numWg[0]) % ndr->numWg[1]; 29711308Santhony.gutierrez@amd.com w->workgroupid[2] = w->wg_id / (ndr->numWg[0] * ndr->numWg[1]); 29811308Santhony.gutierrez@amd.com 29911308Santhony.gutierrez@amd.com w->barrier_id = wfCtx->barrier_id; 30011308Santhony.gutierrez@amd.com w->stalledAtBarrier = false; 30111308Santhony.gutierrez@amd.com 30211308Santhony.gutierrez@amd.com // move this from the context into the actual wavefront 30311308Santhony.gutierrez@amd.com w->ldsChunk = wfCtx->ldsChunk; 30411308Santhony.gutierrez@amd.com 30511308Santhony.gutierrez@amd.com int32_t refCount M5_VAR_USED = 30611308Santhony.gutierrez@amd.com lds.increaseRefCounter(w->dispatchid, w->wg_id); 30711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: increase ref ctr wg[%d] to [%d]\n", 30811308Santhony.gutierrez@amd.com cu_id, w->wg_id, refCount); 30911308Santhony.gutierrez@amd.com 31011308Santhony.gutierrez@amd.com w->instructionBuffer.clear(); 31111308Santhony.gutierrez@amd.com 31211308Santhony.gutierrez@amd.com if (w->pendingFetch) 31311308Santhony.gutierrez@amd.com w->dropFetch = true; 31411308Santhony.gutierrez@amd.com 31511308Santhony.gutierrez@amd.com // is this the last wavefront in the workgroup 31611308Santhony.gutierrez@amd.com // if set the spillWidth to be the remaining work-items 31711308Santhony.gutierrez@amd.com // so that the vector access is correct 31811308Santhony.gutierrez@amd.com if ((cnt + 1) * VSZ >= trueWgSizeTotal) { 31911308Santhony.gutierrez@amd.com w->spillWidth = trueWgSizeTotal - (cnt * VSZ); 32011308Santhony.gutierrez@amd.com } else { 32111308Santhony.gutierrez@amd.com w->spillWidth = VSZ; 32211308Santhony.gutierrez@amd.com } 32311308Santhony.gutierrez@amd.com 32411308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Scheduling wfDynId/barrier_id %d/%d on CU%d: " 32511308Santhony.gutierrez@amd.com "WF[%d][%d]\n", _n_wave, barrier_id, cu_id, w->simdId, w->wfSlotId); 32611308Santhony.gutierrez@amd.com 32711308Santhony.gutierrez@amd.com w->start(++_n_wave, ndr->q.code_ptr); 32811308Santhony.gutierrez@amd.com} 32911308Santhony.gutierrez@amd.com 33011308Santhony.gutierrez@amd.comvoid 33111308Santhony.gutierrez@amd.comComputeUnit::StartWorkgroup(NDRange *ndr) 33211308Santhony.gutierrez@amd.com{ 33311308Santhony.gutierrez@amd.com // reserve the LDS capacity allocated to the work group 33411308Santhony.gutierrez@amd.com // disambiguated by the dispatch ID and workgroup ID, which should be 33511308Santhony.gutierrez@amd.com // globally unique 33611308Santhony.gutierrez@amd.com LdsChunk *ldsChunk = lds.reserveSpace(ndr->dispatchId, ndr->globalWgId, 33711308Santhony.gutierrez@amd.com ndr->q.ldsSize); 33811308Santhony.gutierrez@amd.com 33911308Santhony.gutierrez@amd.com // Send L1 cache acquire 34011308Santhony.gutierrez@amd.com // isKernel + isAcquire = Kernel Begin 34111308Santhony.gutierrez@amd.com if (shader->impl_kern_boundary_sync) { 34211308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = std::make_shared<GPUDynInst>(nullptr, 34311308Santhony.gutierrez@amd.com nullptr, 34411308Santhony.gutierrez@amd.com nullptr, 0); 34511308Santhony.gutierrez@amd.com 34611308Santhony.gutierrez@amd.com gpuDynInst->useContinuation = false; 34711308Santhony.gutierrez@amd.com gpuDynInst->memoryOrder = Enums::MEMORY_ORDER_SC_ACQUIRE; 34811308Santhony.gutierrez@amd.com gpuDynInst->scope = Enums::MEMORY_SCOPE_SYSTEM; 34911308Santhony.gutierrez@amd.com injectGlobalMemFence(gpuDynInst, true); 35011308Santhony.gutierrez@amd.com } 35111308Santhony.gutierrez@amd.com 35211308Santhony.gutierrez@amd.com // Get true size of workgroup (after clamping to grid size) 35311308Santhony.gutierrez@amd.com int trueWgSize[3]; 35411308Santhony.gutierrez@amd.com int trueWgSizeTotal = 1; 35511308Santhony.gutierrez@amd.com 35611308Santhony.gutierrez@amd.com for (int d = 0; d < 3; ++d) { 35711308Santhony.gutierrez@amd.com trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] - 35811308Santhony.gutierrez@amd.com ndr->wgId[d] * ndr->q.wgSize[d]); 35911308Santhony.gutierrez@amd.com 36011308Santhony.gutierrez@amd.com trueWgSizeTotal *= trueWgSize[d]; 36111308Santhony.gutierrez@amd.com } 36211308Santhony.gutierrez@amd.com 36311308Santhony.gutierrez@amd.com uint64_t origSpillMemStart = ndr->q.spillMemStart; 36411308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by wavefront 36511308Santhony.gutierrez@amd.com int vregDemand = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 36611308Santhony.gutierrez@amd.com int cnt = 0; 36711308Santhony.gutierrez@amd.com 36811308Santhony.gutierrez@amd.com // Assign WFs by spreading them across SIMDs, 1 WF per SIMD at a time 36911308Santhony.gutierrez@amd.com for (int m = 0; m < shader->n_wf * numSIMDs; ++m) { 37011308Santhony.gutierrez@amd.com Wavefront *w = wfList[m % numSIMDs][m / numSIMDs]; 37111308Santhony.gutierrez@amd.com // Check if this wavefront slot is available: 37211308Santhony.gutierrez@amd.com // It must be stopped and not waiting 37311308Santhony.gutierrez@amd.com // for a release to complete S_RETURNING 37411308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_STOPPED) { 37511308Santhony.gutierrez@amd.com // if we have scheduled all work items then stop 37611308Santhony.gutierrez@amd.com // scheduling wavefronts 37711308Santhony.gutierrez@amd.com if (cnt * VSZ >= trueWgSizeTotal) 37811308Santhony.gutierrez@amd.com break; 37911308Santhony.gutierrez@amd.com 38011308Santhony.gutierrez@amd.com // reserve vector registers for the scheduled wavefront 38111308Santhony.gutierrez@amd.com assert(vectorRegsReserved[m % numSIMDs] <= numVecRegsPerSimd); 38211308Santhony.gutierrez@amd.com uint32_t normSize = 0; 38311308Santhony.gutierrez@amd.com 38411308Santhony.gutierrez@amd.com w->startVgprIndex = vrf[m % numSIMDs]->manager-> 38511308Santhony.gutierrez@amd.com allocateRegion(vregDemand, &normSize); 38611308Santhony.gutierrez@amd.com 38711308Santhony.gutierrez@amd.com w->reservedVectorRegs = normSize; 38811308Santhony.gutierrez@amd.com vectorRegsReserved[m % numSIMDs] += w->reservedVectorRegs; 38911308Santhony.gutierrez@amd.com 39011308Santhony.gutierrez@amd.com WFContext wfCtx; 39111308Santhony.gutierrez@amd.com 39211308Santhony.gutierrez@amd.com InitializeWFContext(&wfCtx, ndr, cnt, trueWgSize, trueWgSizeTotal, 39311308Santhony.gutierrez@amd.com ldsChunk, origSpillMemStart); 39411308Santhony.gutierrez@amd.com 39511308Santhony.gutierrez@amd.com StartWF(w, &wfCtx, trueWgSize, trueWgSizeTotal); 39611308Santhony.gutierrez@amd.com ++cnt; 39711308Santhony.gutierrez@amd.com } 39811308Santhony.gutierrez@amd.com } 39911308Santhony.gutierrez@amd.com ++barrier_id; 40011308Santhony.gutierrez@amd.com} 40111308Santhony.gutierrez@amd.com 40211308Santhony.gutierrez@amd.comint 40311308Santhony.gutierrez@amd.comComputeUnit::ReadyWorkgroup(NDRange *ndr) 40411308Santhony.gutierrez@amd.com{ 40511308Santhony.gutierrez@amd.com // Get true size of workgroup (after clamping to grid size) 40611308Santhony.gutierrez@amd.com int trueWgSize[3]; 40711308Santhony.gutierrez@amd.com int trueWgSizeTotal = 1; 40811308Santhony.gutierrez@amd.com 40911308Santhony.gutierrez@amd.com for (int d = 0; d < 3; ++d) { 41011308Santhony.gutierrez@amd.com trueWgSize[d] = std::min(ndr->q.wgSize[d], ndr->q.gdSize[d] - 41111308Santhony.gutierrez@amd.com ndr->wgId[d] * ndr->q.wgSize[d]); 41211308Santhony.gutierrez@amd.com 41311308Santhony.gutierrez@amd.com trueWgSizeTotal *= trueWgSize[d]; 41411308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSize[%d] = %d\n", d, trueWgSize[d]); 41511308Santhony.gutierrez@amd.com } 41611308Santhony.gutierrez@amd.com 41711308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "trueWgSizeTotal = %d\n", trueWgSizeTotal); 41811308Santhony.gutierrez@amd.com 41911308Santhony.gutierrez@amd.com // calculate the number of 32-bit vector registers required by each 42011308Santhony.gutierrez@amd.com // work item of the work group 42111308Santhony.gutierrez@amd.com int vregDemandPerWI = ndr->q.sRegCount + (2 * ndr->q.dRegCount); 42211308Santhony.gutierrez@amd.com bool vregAvail = true; 42311308Santhony.gutierrez@amd.com int numWfs = (trueWgSizeTotal + VSZ - 1) / VSZ; 42411308Santhony.gutierrez@amd.com int freeWfSlots = 0; 42511308Santhony.gutierrez@amd.com // check if the total number of VGPRs required by all WFs of the WG 42611308Santhony.gutierrez@amd.com // fit in the VRFs of all SIMD units 42711308Santhony.gutierrez@amd.com assert((numWfs * vregDemandPerWI) <= (numSIMDs * numVecRegsPerSimd)); 42811308Santhony.gutierrez@amd.com int numMappedWfs = 0; 42911308Santhony.gutierrez@amd.com std::vector<int> numWfsPerSimd; 43011308Santhony.gutierrez@amd.com numWfsPerSimd.resize(numSIMDs, 0); 43111308Santhony.gutierrez@amd.com // find how many free WF slots we have across all SIMDs 43211308Santhony.gutierrez@amd.com for (int j = 0; j < shader->n_wf; ++j) { 43311308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 43411308Santhony.gutierrez@amd.com if (wfList[i][j]->status == Wavefront::S_STOPPED) { 43511308Santhony.gutierrez@amd.com // count the number of free WF slots 43611308Santhony.gutierrez@amd.com ++freeWfSlots; 43711308Santhony.gutierrez@amd.com if (numMappedWfs < numWfs) { 43811308Santhony.gutierrez@amd.com // count the WFs to be assigned per SIMD 43911308Santhony.gutierrez@amd.com numWfsPerSimd[i]++; 44011308Santhony.gutierrez@amd.com } 44111308Santhony.gutierrez@amd.com numMappedWfs++; 44211308Santhony.gutierrez@amd.com } 44311308Santhony.gutierrez@amd.com } 44411308Santhony.gutierrez@amd.com } 44511308Santhony.gutierrez@amd.com 44611308Santhony.gutierrez@amd.com // if there are enough free WF slots then find if there are enough 44711308Santhony.gutierrez@amd.com // free VGPRs per SIMD based on the WF->SIMD mapping 44811308Santhony.gutierrez@amd.com if (freeWfSlots >= numWfs) { 44911308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 45011308Santhony.gutierrez@amd.com // find if there are enough free VGPR regions in the SIMD's VRF 45111308Santhony.gutierrez@amd.com // to accommodate the WFs of the new WG that would be mapped to 45211308Santhony.gutierrez@amd.com // this SIMD unit 45311308Santhony.gutierrez@amd.com vregAvail = vrf[j]->manager->canAllocate(numWfsPerSimd[j], 45411308Santhony.gutierrez@amd.com vregDemandPerWI); 45511308Santhony.gutierrez@amd.com 45611308Santhony.gutierrez@amd.com // stop searching if there is at least one SIMD 45711308Santhony.gutierrez@amd.com // whose VRF does not have enough free VGPR pools. 45811308Santhony.gutierrez@amd.com // This is because a WG is scheduled only if ALL 45911308Santhony.gutierrez@amd.com // of its WFs can be scheduled 46011308Santhony.gutierrez@amd.com if (!vregAvail) 46111308Santhony.gutierrez@amd.com break; 46211308Santhony.gutierrez@amd.com } 46311308Santhony.gutierrez@amd.com } 46411308Santhony.gutierrez@amd.com 46511308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "Free WF slots = %d, VGPR Availability = %d\n", 46611308Santhony.gutierrez@amd.com freeWfSlots, vregAvail); 46711308Santhony.gutierrez@amd.com 46811308Santhony.gutierrez@amd.com if (!vregAvail) { 46911308Santhony.gutierrez@amd.com ++numTimesWgBlockedDueVgprAlloc; 47011308Santhony.gutierrez@amd.com } 47111308Santhony.gutierrez@amd.com 47211308Santhony.gutierrez@amd.com // Return true if enough WF slots to submit workgroup and if there are 47311308Santhony.gutierrez@amd.com // enough VGPRs to schedule all WFs to their SIMD units 47411308Santhony.gutierrez@amd.com if (!lds.canReserve(ndr->q.ldsSize)) { 47511308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation++; 47611308Santhony.gutierrez@amd.com } 47711308Santhony.gutierrez@amd.com 47811308Santhony.gutierrez@amd.com // Return true if (a) there are enough free WF slots to submit 47911308Santhony.gutierrez@amd.com // workgrounp and (b) if there are enough VGPRs to schedule all WFs to their 48011308Santhony.gutierrez@amd.com // SIMD units and (c) if there is enough space in LDS 48111308Santhony.gutierrez@amd.com return freeWfSlots >= numWfs && vregAvail && lds.canReserve(ndr->q.ldsSize); 48211308Santhony.gutierrez@amd.com} 48311308Santhony.gutierrez@amd.com 48411308Santhony.gutierrez@amd.comint 48511308Santhony.gutierrez@amd.comComputeUnit::AllAtBarrier(uint32_t _barrier_id, uint32_t bcnt, uint32_t bslots) 48611308Santhony.gutierrez@amd.com{ 48711308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: Checking for All At Barrier\n", cu_id); 48811308Santhony.gutierrez@amd.com int ccnt = 0; 48911308Santhony.gutierrez@amd.com 49011308Santhony.gutierrez@amd.com for (int i_simd = 0; i_simd < numSIMDs; ++i_simd) { 49111308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf) { 49211308Santhony.gutierrez@amd.com Wavefront *w = wfList[i_simd][i_wf]; 49311308Santhony.gutierrez@amd.com 49411308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING) { 49511308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "Checking WF[%d][%d]\n", i_simd, i_wf); 49611308Santhony.gutierrez@amd.com 49711308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_id = %d, _barrier_id = %d\n", 49811308Santhony.gutierrez@amd.com w->barrier_id, _barrier_id); 49911308Santhony.gutierrez@amd.com 50011308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "wf->barrier_cnt %d, bcnt = %d\n", 50111308Santhony.gutierrez@amd.com w->barrier_cnt, bcnt); 50211308Santhony.gutierrez@amd.com } 50311308Santhony.gutierrez@amd.com 50411308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RUNNING && 50511308Santhony.gutierrez@amd.com w->barrier_id == _barrier_id && w->barrier_cnt == bcnt && 50611308Santhony.gutierrez@amd.com !w->outstanding_reqs) { 50711308Santhony.gutierrez@amd.com ++ccnt; 50811308Santhony.gutierrez@amd.com 50911308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "WF[%d][%d] at barrier, increment ccnt to " 51011308Santhony.gutierrez@amd.com "%d\n", i_simd, i_wf, ccnt); 51111308Santhony.gutierrez@amd.com } 51211308Santhony.gutierrez@amd.com } 51311308Santhony.gutierrez@amd.com } 51411308Santhony.gutierrez@amd.com 51511308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: returning allAtBarrier ccnt = %d, bslots = %d\n", 51611308Santhony.gutierrez@amd.com cu_id, ccnt, bslots); 51711308Santhony.gutierrez@amd.com 51811308Santhony.gutierrez@amd.com return ccnt == bslots; 51911308Santhony.gutierrez@amd.com} 52011308Santhony.gutierrez@amd.com 52111308Santhony.gutierrez@amd.com// Check if the current wavefront is blocked on additional resources. 52211308Santhony.gutierrez@amd.combool 52311308Santhony.gutierrez@amd.comComputeUnit::cedeSIMD(int simdId, int wfSlotId) 52411308Santhony.gutierrez@amd.com{ 52511308Santhony.gutierrez@amd.com bool cede = false; 52611308Santhony.gutierrez@amd.com 52711308Santhony.gutierrez@amd.com // If --xact-cas-mode option is enabled in run.py, then xact_cas_ld 52811308Santhony.gutierrez@amd.com // magic instructions will impact the scheduling of wavefronts 52911308Santhony.gutierrez@amd.com if (xact_cas_mode) { 53011308Santhony.gutierrez@amd.com /* 53111308Santhony.gutierrez@amd.com * When a wavefront calls xact_cas_ld, it adds itself to a per address 53211308Santhony.gutierrez@amd.com * queue. All per address queues are managed by the xactCasLoadMap. 53311308Santhony.gutierrez@amd.com * 53411308Santhony.gutierrez@amd.com * A wavefront is not blocked if: it is not in ANY per address queue or 53511308Santhony.gutierrez@amd.com * if it is at the head of a per address queue. 53611308Santhony.gutierrez@amd.com */ 53711308Santhony.gutierrez@amd.com for (auto itMap : xactCasLoadMap) { 53811308Santhony.gutierrez@amd.com std::list<waveIdentifier> curWaveIDQueue = itMap.second.waveIDQueue; 53911308Santhony.gutierrez@amd.com 54011308Santhony.gutierrez@amd.com if (!curWaveIDQueue.empty()) { 54111308Santhony.gutierrez@amd.com for (auto it : curWaveIDQueue) { 54211308Santhony.gutierrez@amd.com waveIdentifier cur_wave = it; 54311308Santhony.gutierrez@amd.com 54411308Santhony.gutierrez@amd.com if (cur_wave.simdId == simdId && 54511308Santhony.gutierrez@amd.com cur_wave.wfSlotId == wfSlotId) { 54611308Santhony.gutierrez@amd.com // 2 possibilities 54711308Santhony.gutierrez@amd.com // 1: this WF has a green light 54811308Santhony.gutierrez@amd.com // 2: another WF has a green light 54911308Santhony.gutierrez@amd.com waveIdentifier owner_wave = curWaveIDQueue.front(); 55011308Santhony.gutierrez@amd.com 55111308Santhony.gutierrez@amd.com if (owner_wave.simdId != cur_wave.simdId || 55211308Santhony.gutierrez@amd.com owner_wave.wfSlotId != cur_wave.wfSlotId) { 55311308Santhony.gutierrez@amd.com // possibility 2 55411308Santhony.gutierrez@amd.com cede = true; 55511308Santhony.gutierrez@amd.com break; 55611308Santhony.gutierrez@amd.com } else { 55711308Santhony.gutierrez@amd.com // possibility 1 55811308Santhony.gutierrez@amd.com break; 55911308Santhony.gutierrez@amd.com } 56011308Santhony.gutierrez@amd.com } 56111308Santhony.gutierrez@amd.com } 56211308Santhony.gutierrez@amd.com } 56311308Santhony.gutierrez@amd.com } 56411308Santhony.gutierrez@amd.com } 56511308Santhony.gutierrez@amd.com 56611308Santhony.gutierrez@amd.com return cede; 56711308Santhony.gutierrez@amd.com} 56811308Santhony.gutierrez@amd.com 56911308Santhony.gutierrez@amd.com// Execute one clock worth of work on the ComputeUnit. 57011308Santhony.gutierrez@amd.comvoid 57111308Santhony.gutierrez@amd.comComputeUnit::exec() 57211308Santhony.gutierrez@amd.com{ 57311308Santhony.gutierrez@amd.com updateEvents(); 57411308Santhony.gutierrez@amd.com // Execute pipeline stages in reverse order to simulate 57511308Santhony.gutierrez@amd.com // the pipeline latency 57611308Santhony.gutierrez@amd.com globalMemoryPipe.exec(); 57711308Santhony.gutierrez@amd.com localMemoryPipe.exec(); 57811308Santhony.gutierrez@amd.com execStage.exec(); 57911308Santhony.gutierrez@amd.com scheduleStage.exec(); 58011308Santhony.gutierrez@amd.com scoreboardCheckStage.exec(); 58111308Santhony.gutierrez@amd.com fetchStage.exec(); 58211308Santhony.gutierrez@amd.com 58311308Santhony.gutierrez@amd.com totalCycles++; 58411308Santhony.gutierrez@amd.com} 58511308Santhony.gutierrez@amd.com 58611308Santhony.gutierrez@amd.comvoid 58711308Santhony.gutierrez@amd.comComputeUnit::init() 58811308Santhony.gutierrez@amd.com{ 58911308Santhony.gutierrez@amd.com // Initialize CU Bus models 59011345Sjohn.kalamatianos@amd.com glbMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 59111345Sjohn.kalamatianos@amd.com locMemToVrfBus.init(&shader->tick_cnt, shader->ticks(1)); 59211308Santhony.gutierrez@amd.com nextGlbMemBus = 0; 59311308Santhony.gutierrez@amd.com nextLocMemBus = 0; 59411308Santhony.gutierrez@amd.com fatal_if(numGlbMemUnits > 1, 59511308Santhony.gutierrez@amd.com "No support for multiple Global Memory Pipelines exists!!!"); 59611308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus.resize(numGlbMemUnits); 59711308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 59811308Santhony.gutierrez@amd.com vrfToGlobalMemPipeBus[j] = WaitClass(); 59911345Sjohn.kalamatianos@amd.com vrfToGlobalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 60011308Santhony.gutierrez@amd.com } 60111308Santhony.gutierrez@amd.com 60211308Santhony.gutierrez@amd.com fatal_if(numLocMemUnits > 1, 60311308Santhony.gutierrez@amd.com "No support for multiple Local Memory Pipelines exists!!!"); 60411308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus.resize(numLocMemUnits); 60511308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 60611308Santhony.gutierrez@amd.com vrfToLocalMemPipeBus[j] = WaitClass(); 60711345Sjohn.kalamatianos@amd.com vrfToLocalMemPipeBus[j].init(&shader->tick_cnt, shader->ticks(1)); 60811308Santhony.gutierrez@amd.com } 60911308Santhony.gutierrez@amd.com vectorRegsReserved.resize(numSIMDs, 0); 61011308Santhony.gutierrez@amd.com aluPipe.resize(numSIMDs); 61111308Santhony.gutierrez@amd.com wfWait.resize(numSIMDs + numLocMemUnits + numGlbMemUnits); 61211308Santhony.gutierrez@amd.com 61311308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs + numLocMemUnits + numGlbMemUnits; ++i) { 61411308Santhony.gutierrez@amd.com wfWait[i] = WaitClass(); 61511345Sjohn.kalamatianos@amd.com wfWait[i].init(&shader->tick_cnt, shader->ticks(1)); 61611308Santhony.gutierrez@amd.com } 61711308Santhony.gutierrez@amd.com 61811308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 61911308Santhony.gutierrez@amd.com aluPipe[i] = WaitClass(); 62011345Sjohn.kalamatianos@amd.com aluPipe[i].init(&shader->tick_cnt, shader->ticks(1)); 62111308Santhony.gutierrez@amd.com } 62211308Santhony.gutierrez@amd.com 62311308Santhony.gutierrez@amd.com // Setup space for call args 62411308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 62511308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 62611308Santhony.gutierrez@amd.com wfList[j][i]->initCallArgMem(shader->funcargs_size); 62711308Santhony.gutierrez@amd.com } 62811308Santhony.gutierrez@amd.com } 62911308Santhony.gutierrez@amd.com 63011308Santhony.gutierrez@amd.com // Initializing pipeline resources 63111308Santhony.gutierrez@amd.com readyList.resize(numSIMDs + numGlbMemUnits + numLocMemUnits); 63211308Santhony.gutierrez@amd.com waveStatusList.resize(numSIMDs); 63311308Santhony.gutierrez@amd.com 63411308Santhony.gutierrez@amd.com for (int j = 0; j < numSIMDs; ++j) { 63511308Santhony.gutierrez@amd.com for (int i = 0; i < shader->n_wf; ++i) { 63611308Santhony.gutierrez@amd.com waveStatusList[j].push_back( 63711308Santhony.gutierrez@amd.com std::make_pair(wfList[j][i], BLOCKED)); 63811308Santhony.gutierrez@amd.com } 63911308Santhony.gutierrez@amd.com } 64011308Santhony.gutierrez@amd.com 64111308Santhony.gutierrez@amd.com for (int j = 0; j < (numSIMDs + numGlbMemUnits + numLocMemUnits); ++j) { 64211308Santhony.gutierrez@amd.com dispatchList.push_back(std::make_pair((Wavefront*)nullptr, EMPTY)); 64311308Santhony.gutierrez@amd.com } 64411308Santhony.gutierrez@amd.com 64511308Santhony.gutierrez@amd.com fetchStage.init(this); 64611308Santhony.gutierrez@amd.com scoreboardCheckStage.init(this); 64711308Santhony.gutierrez@amd.com scheduleStage.init(this); 64811308Santhony.gutierrez@amd.com execStage.init(this); 64911308Santhony.gutierrez@amd.com globalMemoryPipe.init(this); 65011308Santhony.gutierrez@amd.com localMemoryPipe.init(this); 65111308Santhony.gutierrez@amd.com // initialize state for statistics calculation 65211308Santhony.gutierrez@amd.com vectorAluInstAvail.resize(numSIMDs, false); 65311308Santhony.gutierrez@amd.com shrMemInstAvail = 0; 65411308Santhony.gutierrez@amd.com glbMemInstAvail = 0; 65511308Santhony.gutierrez@amd.com} 65611308Santhony.gutierrez@amd.com 65711308Santhony.gutierrez@amd.combool 65811308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvTimingResp(PacketPtr pkt) 65911308Santhony.gutierrez@amd.com{ 66011308Santhony.gutierrez@amd.com // Ruby has completed the memory op. Schedule the mem_resp_event at the 66111308Santhony.gutierrez@amd.com // appropriate cycle to process the timing memory response 66211308Santhony.gutierrez@amd.com // This delay represents the pipeline delay 66311308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 66411308Santhony.gutierrez@amd.com int index = sender_state->port_index; 66511308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 66611308Santhony.gutierrez@amd.com 66711308Santhony.gutierrez@amd.com // Is the packet returned a Kernel End or Barrier 66811308Santhony.gutierrez@amd.com if (pkt->req->isKernel() && pkt->req->isRelease()) { 66911308Santhony.gutierrez@amd.com Wavefront *w = 67011308Santhony.gutierrez@amd.com computeUnit->wfList[gpuDynInst->simdId][gpuDynInst->wfSlotId]; 67111308Santhony.gutierrez@amd.com 67211308Santhony.gutierrez@amd.com // Check if we are waiting on Kernel End Release 67311308Santhony.gutierrez@amd.com if (w->status == Wavefront::S_RETURNING) { 67411308Santhony.gutierrez@amd.com DPRINTF(GPUDisp, "CU%d: WF[%d][%d][wv=%d]: WG id completed %d\n", 67511308Santhony.gutierrez@amd.com computeUnit->cu_id, w->simdId, w->wfSlotId, 67611308Santhony.gutierrez@amd.com w->wfDynId, w->kern_id); 67711308Santhony.gutierrez@amd.com 67811308Santhony.gutierrez@amd.com computeUnit->shader->dispatcher->notifyWgCompl(w); 67911308Santhony.gutierrez@amd.com w->status = Wavefront::S_STOPPED; 68011308Santhony.gutierrez@amd.com } else { 68111308Santhony.gutierrez@amd.com w->outstanding_reqs--; 68211308Santhony.gutierrez@amd.com } 68311308Santhony.gutierrez@amd.com 68411308Santhony.gutierrez@amd.com DPRINTF(GPUSync, "CU%d: WF[%d][%d]: barrier_cnt = %d\n", 68511308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 68611308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, w->barrier_cnt); 68711308Santhony.gutierrez@amd.com 68811308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 68911308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 69011308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 69111308Santhony.gutierrez@amd.com gpuDynInst); 69211308Santhony.gutierrez@amd.com } 69311308Santhony.gutierrez@amd.com 69411308Santhony.gutierrez@amd.com delete pkt->senderState; 69511308Santhony.gutierrez@amd.com delete pkt->req; 69611308Santhony.gutierrez@amd.com delete pkt; 69711308Santhony.gutierrez@amd.com return true; 69811308Santhony.gutierrez@amd.com } else if (pkt->req->isKernel() && pkt->req->isAcquire()) { 69911308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 70011308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 70111308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 70211308Santhony.gutierrez@amd.com gpuDynInst); 70311308Santhony.gutierrez@amd.com } 70411308Santhony.gutierrez@amd.com 70511308Santhony.gutierrez@amd.com delete pkt->senderState; 70611308Santhony.gutierrez@amd.com delete pkt->req; 70711308Santhony.gutierrez@amd.com delete pkt; 70811308Santhony.gutierrez@amd.com return true; 70911308Santhony.gutierrez@amd.com } 71011308Santhony.gutierrez@amd.com 71111308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemRespEvent *mem_resp_event = 71211308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemRespEvent(computeUnit->memPort[index], 71311308Santhony.gutierrez@amd.com pkt); 71411308Santhony.gutierrez@amd.com 71511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x received!\n", 71611308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 71711308Santhony.gutierrez@amd.com index, pkt->req->getPaddr()); 71811308Santhony.gutierrez@amd.com 71911308Santhony.gutierrez@amd.com computeUnit->schedule(mem_resp_event, 72011308Santhony.gutierrez@amd.com curTick() + computeUnit->resp_tick_latency); 72111308Santhony.gutierrez@amd.com return true; 72211308Santhony.gutierrez@amd.com} 72311308Santhony.gutierrez@amd.com 72411308Santhony.gutierrez@amd.comvoid 72511308Santhony.gutierrez@amd.comComputeUnit::DataPort::recvReqRetry() 72611308Santhony.gutierrez@amd.com{ 72711308Santhony.gutierrez@amd.com int len = retries.size(); 72811308Santhony.gutierrez@amd.com 72911308Santhony.gutierrez@amd.com assert(len > 0); 73011308Santhony.gutierrez@amd.com 73111308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 73211308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 73311308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = retries.front().second; 73411308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: retry mem inst addr %#x\n", 73511308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 73611308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 73711308Santhony.gutierrez@amd.com 73811308Santhony.gutierrez@amd.com /** Currently Ruby can return false due to conflicts for the particular 73911308Santhony.gutierrez@amd.com * cache block or address. Thus other requests should be allowed to 74011308Santhony.gutierrez@amd.com * pass and the data port should expect multiple retries. */ 74111308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 74211308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "failed again!\n"); 74311308Santhony.gutierrez@amd.com break; 74411308Santhony.gutierrez@amd.com } else { 74511308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "successful!\n"); 74611308Santhony.gutierrez@amd.com retries.pop_front(); 74711308Santhony.gutierrez@amd.com } 74811308Santhony.gutierrez@amd.com } 74911308Santhony.gutierrez@amd.com} 75011308Santhony.gutierrez@amd.com 75111308Santhony.gutierrez@amd.combool 75211308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvTimingResp(PacketPtr pkt) 75311308Santhony.gutierrez@amd.com{ 75411308Santhony.gutierrez@amd.com computeUnit->fetchStage.processFetchReturn(pkt); 75511308Santhony.gutierrez@amd.com 75611308Santhony.gutierrez@amd.com return true; 75711308Santhony.gutierrez@amd.com} 75811308Santhony.gutierrez@amd.com 75911308Santhony.gutierrez@amd.comvoid 76011308Santhony.gutierrez@amd.comComputeUnit::SQCPort::recvReqRetry() 76111308Santhony.gutierrez@amd.com{ 76211308Santhony.gutierrez@amd.com int len = retries.size(); 76311308Santhony.gutierrez@amd.com 76411308Santhony.gutierrez@amd.com assert(len > 0); 76511308Santhony.gutierrez@amd.com 76611308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 76711308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front().first; 76811308Santhony.gutierrez@amd.com Wavefront *wavefront M5_VAR_USED = retries.front().second; 76911308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "CU%d: WF[%d][%d]: retrying FETCH addr %#x\n", 77011308Santhony.gutierrez@amd.com computeUnit->cu_id, wavefront->simdId, wavefront->wfSlotId, 77111308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 77211308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 77311308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "failed again!\n"); 77411308Santhony.gutierrez@amd.com break; 77511308Santhony.gutierrez@amd.com } else { 77611308Santhony.gutierrez@amd.com DPRINTF(GPUFetch, "successful!\n"); 77711308Santhony.gutierrez@amd.com retries.pop_front(); 77811308Santhony.gutierrez@amd.com } 77911308Santhony.gutierrez@amd.com } 78011308Santhony.gutierrez@amd.com} 78111308Santhony.gutierrez@amd.com 78211308Santhony.gutierrez@amd.comvoid 78311308Santhony.gutierrez@amd.comComputeUnit::sendRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 78411308Santhony.gutierrez@amd.com{ 78511308Santhony.gutierrez@amd.com // There must be a way around this check to do the globalMemStart... 78611308Santhony.gutierrez@amd.com Addr tmp_vaddr = pkt->req->getVaddr(); 78711308Santhony.gutierrez@amd.com 78811308Santhony.gutierrez@amd.com updatePageDivergenceDist(tmp_vaddr); 78911308Santhony.gutierrez@amd.com 79011308Santhony.gutierrez@amd.com pkt->req->setVirt(pkt->req->getAsid(), tmp_vaddr, pkt->req->getSize(), 79111308Santhony.gutierrez@amd.com pkt->req->getFlags(), pkt->req->masterId(), 79211308Santhony.gutierrez@amd.com pkt->req->getPC()); 79311308Santhony.gutierrez@amd.com 79411308Santhony.gutierrez@amd.com // figure out the type of the request to set read/write 79511308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode; 79611308Santhony.gutierrez@amd.com assert(pkt->isRead() || pkt->isWrite()); 79711308Santhony.gutierrez@amd.com 79811308Santhony.gutierrez@amd.com // Check write before read for atomic operations 79911308Santhony.gutierrez@amd.com // since atomic operations should use BaseTLB::Write 80011308Santhony.gutierrez@amd.com if (pkt->isWrite()){ 80111308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Write; 80211308Santhony.gutierrez@amd.com } else if (pkt->isRead()) { 80311308Santhony.gutierrez@amd.com TLB_mode = BaseTLB::Read; 80411308Santhony.gutierrez@amd.com } else { 80511308Santhony.gutierrez@amd.com fatal("pkt is not a read nor a write\n"); 80611308Santhony.gutierrez@amd.com } 80711308Santhony.gutierrez@amd.com 80811308Santhony.gutierrez@amd.com tlbCycles -= curTick(); 80911308Santhony.gutierrez@amd.com ++tlbRequests; 81011308Santhony.gutierrez@amd.com 81111308Santhony.gutierrez@amd.com int tlbPort_index = perLaneTLB ? index : 0; 81211308Santhony.gutierrez@amd.com 81311308Santhony.gutierrez@amd.com if (shader->timingSim) { 81411308Santhony.gutierrez@amd.com if (debugSegFault) { 81511308Santhony.gutierrez@amd.com Process *p = shader->gpuTc->getProcessPtr(); 81611308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 81711308Santhony.gutierrez@amd.com unsigned size = pkt->getSize(); 81811308Santhony.gutierrez@amd.com 81911308Santhony.gutierrez@amd.com if ((vaddr + size - 1) % 64 < vaddr % 64) { 82011308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Access to addr %#x is unaligned!\n", 82111308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, vaddr); 82211308Santhony.gutierrez@amd.com } 82311308Santhony.gutierrez@amd.com 82411308Santhony.gutierrez@amd.com Addr paddr; 82511308Santhony.gutierrez@amd.com 82611308Santhony.gutierrez@amd.com if (!p->pTable->translate(vaddr, paddr)) { 82711308Santhony.gutierrez@amd.com if (!p->fixupStackFault(vaddr)) { 82811308Santhony.gutierrez@amd.com panic("CU%d: WF[%d][%d]: Fault on addr %#x!\n", 82911308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 83011308Santhony.gutierrez@amd.com vaddr); 83111308Santhony.gutierrez@amd.com } 83211308Santhony.gutierrez@amd.com } 83311308Santhony.gutierrez@amd.com } 83411308Santhony.gutierrez@amd.com 83511308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 83611308Santhony.gutierrez@amd.com pkt->senderState = new DTLBPort::SenderState(gpuDynInst, index); 83711308Santhony.gutierrez@amd.com 83811308Santhony.gutierrez@amd.com // This is the senderState needed by the TLB hierarchy to function 83911308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 84011308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, shader->gpuTc, false, 84111308Santhony.gutierrez@amd.com pkt->senderState); 84211308Santhony.gutierrez@amd.com 84311308Santhony.gutierrez@amd.com pkt->senderState = translation_state; 84411308Santhony.gutierrez@amd.com 84511308Santhony.gutierrez@amd.com if (functionalTLB) { 84611308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 84711308Santhony.gutierrez@amd.com 84811308Santhony.gutierrez@amd.com // update the hitLevel distribution 84911308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 85011308Santhony.gutierrez@amd.com assert(hit_level != -1); 85111308Santhony.gutierrez@amd.com hitsPerTLBLevel[hit_level]++; 85211308Santhony.gutierrez@amd.com 85311308Santhony.gutierrez@amd.com // New SenderState for the memory access 85411308Santhony.gutierrez@amd.com X86ISA::GpuTLB::TranslationState *sender_state = 85511308Santhony.gutierrez@amd.com safe_cast<X86ISA::GpuTLB::TranslationState*>(pkt->senderState); 85611308Santhony.gutierrez@amd.com 85711308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 85811308Santhony.gutierrez@amd.com delete sender_state->saved; 85911308Santhony.gutierrez@amd.com delete sender_state; 86011308Santhony.gutierrez@amd.com 86111308Santhony.gutierrez@amd.com assert(pkt->req->hasPaddr()); 86211308Santhony.gutierrez@amd.com assert(pkt->req->hasSize()); 86311308Santhony.gutierrez@amd.com 86411308Santhony.gutierrez@amd.com uint8_t *tmpData = pkt->getPtr<uint8_t>(); 86511308Santhony.gutierrez@amd.com 86611308Santhony.gutierrez@amd.com // this is necessary because the GPU TLB receives packets instead 86711308Santhony.gutierrez@amd.com // of requests. when the translation is complete, all relevent 86811308Santhony.gutierrez@amd.com // fields in the request will be populated, but not in the packet. 86911308Santhony.gutierrez@amd.com // here we create the new packet so we can set the size, addr, 87011308Santhony.gutierrez@amd.com // and proper flags. 87111308Santhony.gutierrez@amd.com PacketPtr oldPkt = pkt; 87211308Santhony.gutierrez@amd.com pkt = new Packet(oldPkt->req, oldPkt->cmd); 87311308Santhony.gutierrez@amd.com delete oldPkt; 87411308Santhony.gutierrez@amd.com pkt->dataStatic(tmpData); 87511308Santhony.gutierrez@amd.com 87611308Santhony.gutierrez@amd.com 87711308Santhony.gutierrez@amd.com // New SenderState for the memory access 87811308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, 87911308Santhony.gutierrez@amd.com index, nullptr); 88011308Santhony.gutierrez@amd.com 88111308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[pkt->getAddr()].push_back(index); 88211308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[index] = hit_level; 88311308Santhony.gutierrez@amd.com 88411308Santhony.gutierrez@amd.com 88511308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the 88611308Santhony.gutierrez@amd.com // appropriate cycle to send the timing memory request to ruby 88711308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 88811308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt); 88911308Santhony.gutierrez@amd.com 89011308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data " 89111308Santhony.gutierrez@amd.com "scheduled\n", cu_id, gpuDynInst->simdId, 89211308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, index, pkt->req->getPaddr()); 89311308Santhony.gutierrez@amd.com 89411308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 89511308Santhony.gutierrez@amd.com } else if (tlbPort[tlbPort_index]->isStalled()) { 89611308Santhony.gutierrez@amd.com assert(tlbPort[tlbPort_index]->retries.size() > 0); 89711308Santhony.gutierrez@amd.com 89811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 89911308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 90011308Santhony.gutierrez@amd.com tmp_vaddr); 90111308Santhony.gutierrez@amd.com 90211308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 90311308Santhony.gutierrez@amd.com } else if (!tlbPort[tlbPort_index]->sendTimingReq(pkt)) { 90411308Santhony.gutierrez@amd.com // Stall the data port; 90511308Santhony.gutierrez@amd.com // No more packet will be issued till 90611308Santhony.gutierrez@amd.com // ruby indicates resources are freed by 90711308Santhony.gutierrez@amd.com // a recvReqRetry() call back on this port. 90811308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->stallPort(); 90911308Santhony.gutierrez@amd.com 91011308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: WF[%d][%d]: Translation for addr %#x " 91111308Santhony.gutierrez@amd.com "failed!\n", cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 91211308Santhony.gutierrez@amd.com tmp_vaddr); 91311308Santhony.gutierrez@amd.com 91411308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->retries.push_back(pkt); 91511308Santhony.gutierrez@amd.com } else { 91611308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, 91711308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: Translation for addr %#x sent!\n", 91811308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, tmp_vaddr); 91911308Santhony.gutierrez@amd.com } 92011308Santhony.gutierrez@amd.com } else { 92111308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::MemFenceReq) { 92211308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 92311308Santhony.gutierrez@amd.com } else { 92411308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ll << index)); 92511308Santhony.gutierrez@amd.com } 92611308Santhony.gutierrez@amd.com 92711308Santhony.gutierrez@amd.com // New SenderState for the memory access 92811308Santhony.gutierrez@amd.com delete pkt->senderState; 92911308Santhony.gutierrez@amd.com 93011308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 93111308Santhony.gutierrez@amd.com pkt->senderState = new TheISA::GpuTLB::TranslationState(TLB_mode, 93211308Santhony.gutierrez@amd.com shader->gpuTc); 93311308Santhony.gutierrez@amd.com 93411308Santhony.gutierrez@amd.com tlbPort[tlbPort_index]->sendFunctional(pkt); 93511308Santhony.gutierrez@amd.com 93611308Santhony.gutierrez@amd.com // the addr of the packet is not modified, so we need to create a new 93711308Santhony.gutierrez@amd.com // packet, or otherwise the memory access will have the old virtual 93811308Santhony.gutierrez@amd.com // address sent in the translation packet, instead of the physical 93911308Santhony.gutierrez@amd.com // address returned by the translation. 94011308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, pkt->cmd); 94111308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 94211308Santhony.gutierrez@amd.com 94311308Santhony.gutierrez@amd.com // Translation is done. It is safe to send the packet to memory. 94411308Santhony.gutierrez@amd.com memPort[0]->sendFunctional(new_pkt); 94511308Santhony.gutierrez@amd.com 94611308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: index %d: addr %#x\n", cu_id, 94711308Santhony.gutierrez@amd.com gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 94811308Santhony.gutierrez@amd.com new_pkt->req->getPaddr()); 94911308Santhony.gutierrez@amd.com 95011308Santhony.gutierrez@amd.com // safe_cast the senderState 95111308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *sender_state = 95211308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 95311308Santhony.gutierrez@amd.com 95411308Santhony.gutierrez@amd.com delete sender_state->tlbEntry; 95511308Santhony.gutierrez@amd.com delete new_pkt; 95611308Santhony.gutierrez@amd.com delete pkt->senderState; 95711308Santhony.gutierrez@amd.com delete pkt->req; 95811308Santhony.gutierrez@amd.com delete pkt; 95911308Santhony.gutierrez@amd.com } 96011308Santhony.gutierrez@amd.com} 96111308Santhony.gutierrez@amd.com 96211308Santhony.gutierrez@amd.comvoid 96311308Santhony.gutierrez@amd.comComputeUnit::sendSyncRequest(GPUDynInstPtr gpuDynInst, int index, PacketPtr pkt) 96411308Santhony.gutierrez@amd.com{ 96511308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 96611308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(memPort[index], pkt); 96711308Santhony.gutierrez@amd.com 96811308Santhony.gutierrez@amd.com 96911308Santhony.gutierrez@amd.com // New SenderState for the memory access 97011308Santhony.gutierrez@amd.com pkt->senderState = new ComputeUnit::DataPort::SenderState(gpuDynInst, index, 97111308Santhony.gutierrez@amd.com nullptr); 97211308Santhony.gutierrez@amd.com 97311308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x sync scheduled\n", 97411308Santhony.gutierrez@amd.com cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, index, 97511308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 97611308Santhony.gutierrez@amd.com 97711308Santhony.gutierrez@amd.com schedule(mem_req_event, curTick() + req_tick_latency); 97811308Santhony.gutierrez@amd.com} 97911308Santhony.gutierrez@amd.com 98011308Santhony.gutierrez@amd.comvoid 98111308Santhony.gutierrez@amd.comComputeUnit::injectGlobalMemFence(GPUDynInstPtr gpuDynInst, bool kernelLaunch, 98211308Santhony.gutierrez@amd.com Request* req) 98311308Santhony.gutierrez@amd.com{ 98411308Santhony.gutierrez@amd.com if (!req) { 98511435Smitch.hayenga@arm.com req = new Request(0, 0, 0, 0, masterId(), 0, gpuDynInst->wfDynId); 98611308Santhony.gutierrez@amd.com } 98711308Santhony.gutierrez@amd.com req->setPaddr(0); 98811308Santhony.gutierrez@amd.com if (kernelLaunch) { 98911308Santhony.gutierrez@amd.com req->setFlags(Request::KERNEL); 99011308Santhony.gutierrez@amd.com } 99111308Santhony.gutierrez@amd.com 99211308Santhony.gutierrez@amd.com gpuDynInst->s_type = SEG_GLOBAL; 99311308Santhony.gutierrez@amd.com 99411308Santhony.gutierrez@amd.com // for non-kernel MemFence operations, memorder flags are set depending 99511308Santhony.gutierrez@amd.com // on which type of request is currently being sent, so this 99611308Santhony.gutierrez@amd.com // should be set by the caller (e.g. if an inst has acq-rel 99711308Santhony.gutierrez@amd.com // semantics, it will send one acquire req an one release req) 99811308Santhony.gutierrez@amd.com gpuDynInst->setRequestFlags(req, kernelLaunch); 99911308Santhony.gutierrez@amd.com 100011308Santhony.gutierrez@amd.com // a mem fence must correspond to an acquire/release request 100111308Santhony.gutierrez@amd.com assert(req->isAcquire() || req->isRelease()); 100211308Santhony.gutierrez@amd.com 100311308Santhony.gutierrez@amd.com // create packet 100411308Santhony.gutierrez@amd.com PacketPtr pkt = new Packet(req, MemCmd::MemFenceReq); 100511308Santhony.gutierrez@amd.com 100611308Santhony.gutierrez@amd.com // set packet's sender state 100711308Santhony.gutierrez@amd.com pkt->senderState = 100811308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, 0, nullptr); 100911308Santhony.gutierrez@amd.com 101011308Santhony.gutierrez@amd.com // send the packet 101111308Santhony.gutierrez@amd.com sendSyncRequest(gpuDynInst, 0, pkt); 101211308Santhony.gutierrez@amd.com} 101311308Santhony.gutierrez@amd.com 101411308Santhony.gutierrez@amd.comconst char* 101511308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemRespEvent::description() const 101611308Santhony.gutierrez@amd.com{ 101711308Santhony.gutierrez@amd.com return "ComputeUnit memory response event"; 101811308Santhony.gutierrez@amd.com} 101911308Santhony.gutierrez@amd.com 102011308Santhony.gutierrez@amd.comvoid 102111308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemRespEvent::process() 102211308Santhony.gutierrez@amd.com{ 102311308Santhony.gutierrez@amd.com DataPort::SenderState *sender_state = 102411308Santhony.gutierrez@amd.com safe_cast<DataPort::SenderState*>(pkt->senderState); 102511308Santhony.gutierrez@amd.com 102611308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 102711308Santhony.gutierrez@amd.com ComputeUnit *compute_unit = dataPort->computeUnit; 102811308Santhony.gutierrez@amd.com 102911308Santhony.gutierrez@amd.com assert(gpuDynInst); 103011308Santhony.gutierrez@amd.com 103111308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: Response for addr %#x, index %d\n", 103211308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, gpuDynInst->wfSlotId, 103311308Santhony.gutierrez@amd.com pkt->req->getPaddr(), dataPort->index); 103411308Santhony.gutierrez@amd.com 103511308Santhony.gutierrez@amd.com Addr paddr = pkt->req->getPaddr(); 103611308Santhony.gutierrez@amd.com 103711308Santhony.gutierrez@amd.com if (pkt->cmd != MemCmd::MemFenceResp) { 103811308Santhony.gutierrez@amd.com int index = gpuDynInst->memStatusVector[paddr].back(); 103911308Santhony.gutierrez@amd.com 104011308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "Response for addr %#x, index %d\n", 104111308Santhony.gutierrez@amd.com pkt->req->getPaddr(), index); 104211308Santhony.gutierrez@amd.com 104311308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[paddr].pop_back(); 104411308Santhony.gutierrez@amd.com gpuDynInst->pAddr = pkt->req->getPaddr(); 104511308Santhony.gutierrez@amd.com 104611308Santhony.gutierrez@amd.com if (pkt->isRead() || pkt->isWrite()) { 104711308Santhony.gutierrez@amd.com 104811308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg <= MAX_REGS_FOR_NON_VEC_MEM_INST) { 104911308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 105011308Santhony.gutierrez@amd.com } else { 105111308Santhony.gutierrez@amd.com assert(gpuDynInst->statusVector[index] > 0); 105211308Santhony.gutierrez@amd.com gpuDynInst->statusVector[index]--; 105311308Santhony.gutierrez@amd.com 105411308Santhony.gutierrez@amd.com if (!gpuDynInst->statusVector[index]) 105511308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector &= (~(1ULL << index)); 105611308Santhony.gutierrez@amd.com } 105711308Santhony.gutierrez@amd.com 105811308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "bitvector is now %#x\n", 105911308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector); 106011308Santhony.gutierrez@amd.com 106111308Santhony.gutierrez@amd.com if (gpuDynInst->statusBitVector == VectorMask(0)) { 106211308Santhony.gutierrez@amd.com auto iter = gpuDynInst->memStatusVector.begin(); 106311308Santhony.gutierrez@amd.com auto end = gpuDynInst->memStatusVector.end(); 106411308Santhony.gutierrez@amd.com 106511308Santhony.gutierrez@amd.com while (iter != end) { 106611308Santhony.gutierrez@amd.com assert(iter->second.empty()); 106711308Santhony.gutierrez@amd.com ++iter; 106811308Santhony.gutierrez@amd.com } 106911308Santhony.gutierrez@amd.com 107011308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector.clear(); 107111308Santhony.gutierrez@amd.com 107211308Santhony.gutierrez@amd.com if (gpuDynInst->n_reg > MAX_REGS_FOR_NON_VEC_MEM_INST) 107311308Santhony.gutierrez@amd.com gpuDynInst->statusVector.clear(); 107411308Santhony.gutierrez@amd.com 107511308Santhony.gutierrez@amd.com if (gpuDynInst->m_op == Enums::MO_LD || MO_A(gpuDynInst->m_op) 107611308Santhony.gutierrez@amd.com || MO_ANR(gpuDynInst->m_op)) { 107711308Santhony.gutierrez@amd.com assert(compute_unit->globalMemoryPipe.isGMLdRespFIFOWrRdy()); 107811308Santhony.gutierrez@amd.com 107911308Santhony.gutierrez@amd.com compute_unit->globalMemoryPipe.getGMLdRespFIFO() 108011308Santhony.gutierrez@amd.com .push(gpuDynInst); 108111308Santhony.gutierrez@amd.com } else { 108211308Santhony.gutierrez@amd.com assert(compute_unit->globalMemoryPipe.isGMStRespFIFOWrRdy()); 108311308Santhony.gutierrez@amd.com 108411308Santhony.gutierrez@amd.com compute_unit->globalMemoryPipe.getGMStRespFIFO() 108511308Santhony.gutierrez@amd.com .push(gpuDynInst); 108611308Santhony.gutierrez@amd.com } 108711308Santhony.gutierrez@amd.com 108811308Santhony.gutierrez@amd.com DPRINTF(GPUMem, "CU%d: WF[%d][%d]: packet totally complete\n", 108911308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 109011308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 109111308Santhony.gutierrez@amd.com 109211308Santhony.gutierrez@amd.com // after clearing the status vectors, 109311308Santhony.gutierrez@amd.com // see if there is a continuation to perform 109411308Santhony.gutierrez@amd.com // the continuation may generate more work for 109511308Santhony.gutierrez@amd.com // this memory request 109611308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 109711308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 109811308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 109911308Santhony.gutierrez@amd.com gpuDynInst); 110011308Santhony.gutierrez@amd.com } 110111308Santhony.gutierrez@amd.com } 110211308Santhony.gutierrez@amd.com } 110311308Santhony.gutierrez@amd.com } else { 110411308Santhony.gutierrez@amd.com gpuDynInst->statusBitVector = VectorMask(0); 110511308Santhony.gutierrez@amd.com 110611308Santhony.gutierrez@amd.com if (gpuDynInst->useContinuation) { 110711308Santhony.gutierrez@amd.com assert(gpuDynInst->scope != Enums::MEMORY_SCOPE_NONE); 110811308Santhony.gutierrez@amd.com gpuDynInst->execContinuation(gpuDynInst->staticInstruction(), 110911308Santhony.gutierrez@amd.com gpuDynInst); 111011308Santhony.gutierrez@amd.com } 111111308Santhony.gutierrez@amd.com } 111211308Santhony.gutierrez@amd.com 111311308Santhony.gutierrez@amd.com delete pkt->senderState; 111411308Santhony.gutierrez@amd.com delete pkt->req; 111511308Santhony.gutierrez@amd.com delete pkt; 111611308Santhony.gutierrez@amd.com} 111711308Santhony.gutierrez@amd.com 111811308Santhony.gutierrez@amd.comComputeUnit* 111911308Santhony.gutierrez@amd.comComputeUnitParams::create() 112011308Santhony.gutierrez@amd.com{ 112111308Santhony.gutierrez@amd.com return new ComputeUnit(this); 112211308Santhony.gutierrez@amd.com} 112311308Santhony.gutierrez@amd.com 112411308Santhony.gutierrez@amd.combool 112511308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvTimingResp(PacketPtr pkt) 112611308Santhony.gutierrez@amd.com{ 112711308Santhony.gutierrez@amd.com Addr line = pkt->req->getPaddr(); 112811308Santhony.gutierrez@amd.com 112911308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLBPort received %#x->%#x\n", computeUnit->cu_id, 113011308Santhony.gutierrez@amd.com pkt->req->getVaddr(), line); 113111308Santhony.gutierrez@amd.com 113211308Santhony.gutierrez@amd.com assert(pkt->senderState); 113311308Santhony.gutierrez@amd.com computeUnit->tlbCycles += curTick(); 113411308Santhony.gutierrez@amd.com 113511308Santhony.gutierrez@amd.com // pop off the TLB translation state 113611308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 113711308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 113811308Santhony.gutierrez@amd.com 113911308Santhony.gutierrez@amd.com // no PageFaults are permitted for data accesses 114011308Santhony.gutierrez@amd.com if (!translation_state->tlbEntry->valid) { 114111308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 114211308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(translation_state->saved); 114311308Santhony.gutierrez@amd.com 114411308Santhony.gutierrez@amd.com Wavefront *w M5_VAR_USED = 114511308Santhony.gutierrez@amd.com computeUnit->wfList[sender_state->_gpuDynInst->simdId] 114611308Santhony.gutierrez@amd.com [sender_state->_gpuDynInst->wfSlotId]; 114711308Santhony.gutierrez@amd.com 114811308Santhony.gutierrez@amd.com DPRINTFN("Wave %d couldn't tranlate vaddr %#x\n", w->wfDynId, 114911308Santhony.gutierrez@amd.com pkt->req->getVaddr()); 115011308Santhony.gutierrez@amd.com } 115111308Santhony.gutierrez@amd.com 115211308Santhony.gutierrez@amd.com assert(translation_state->tlbEntry->valid); 115311308Santhony.gutierrez@amd.com 115411308Santhony.gutierrez@amd.com // update the hitLevel distribution 115511308Santhony.gutierrez@amd.com int hit_level = translation_state->hitLevel; 115611308Santhony.gutierrez@amd.com computeUnit->hitsPerTLBLevel[hit_level]++; 115711308Santhony.gutierrez@amd.com 115811308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 115911308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 116011308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 116111308Santhony.gutierrez@amd.com 116211308Santhony.gutierrez@amd.com // for prefetch pkt 116311308Santhony.gutierrez@amd.com BaseTLB::Mode TLB_mode = translation_state->tlbMode; 116411308Santhony.gutierrez@amd.com 116511308Santhony.gutierrez@amd.com delete translation_state; 116611308Santhony.gutierrez@amd.com 116711308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 116811308Santhony.gutierrez@amd.com DTLBPort::SenderState *sender_state = 116911308Santhony.gutierrez@amd.com safe_cast<DTLBPort::SenderState*>(pkt->senderState); 117011308Santhony.gutierrez@amd.com 117111308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 117211308Santhony.gutierrez@amd.com int mp_index = sender_state->portIndex; 117311308Santhony.gutierrez@amd.com Addr vaddr = pkt->req->getVaddr(); 117411308Santhony.gutierrez@amd.com gpuDynInst->memStatusVector[line].push_back(mp_index); 117511308Santhony.gutierrez@amd.com gpuDynInst->tlbHitLevel[mp_index] = hit_level; 117611308Santhony.gutierrez@amd.com 117711308Santhony.gutierrez@amd.com MemCmd requestCmd; 117811308Santhony.gutierrez@amd.com 117911308Santhony.gutierrez@amd.com if (pkt->cmd == MemCmd::ReadResp) { 118011308Santhony.gutierrez@amd.com requestCmd = MemCmd::ReadReq; 118111308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::WriteResp) { 118211308Santhony.gutierrez@amd.com requestCmd = MemCmd::WriteReq; 118311308Santhony.gutierrez@amd.com } else if (pkt->cmd == MemCmd::SwapResp) { 118411308Santhony.gutierrez@amd.com requestCmd = MemCmd::SwapReq; 118511308Santhony.gutierrez@amd.com } else { 118611308Santhony.gutierrez@amd.com panic("unsupported response to request conversion %s\n", 118711308Santhony.gutierrez@amd.com pkt->cmd.toString()); 118811308Santhony.gutierrez@amd.com } 118911308Santhony.gutierrez@amd.com 119011308Santhony.gutierrez@amd.com if (computeUnit->prefetchDepth) { 119111308Santhony.gutierrez@amd.com int simdId = gpuDynInst->simdId; 119211308Santhony.gutierrez@amd.com int wfSlotId = gpuDynInst->wfSlotId; 119311308Santhony.gutierrez@amd.com Addr last = 0; 119411308Santhony.gutierrez@amd.com 119511308Santhony.gutierrez@amd.com switch(computeUnit->prefetchType) { 119611308Santhony.gutierrez@amd.com case Enums::PF_CU: 119711308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrCU[mp_index]; 119811308Santhony.gutierrez@amd.com break; 119911308Santhony.gutierrez@amd.com case Enums::PF_PHASE: 120011308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrPhase[simdId][mp_index]; 120111308Santhony.gutierrez@amd.com break; 120211308Santhony.gutierrez@amd.com case Enums::PF_WF: 120311308Santhony.gutierrez@amd.com last = computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index]; 120411308Santhony.gutierrez@amd.com default: 120511308Santhony.gutierrez@amd.com break; 120611308Santhony.gutierrez@amd.com } 120711308Santhony.gutierrez@amd.com 120811308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "CU[%d][%d][%d][%d]: %#x was last\n", 120911308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index, last); 121011308Santhony.gutierrez@amd.com 121111308Santhony.gutierrez@amd.com int stride = last ? (roundDown(vaddr, TheISA::PageBytes) - 121211308Santhony.gutierrez@amd.com roundDown(last, TheISA::PageBytes)) >> TheISA::PageShift 121311308Santhony.gutierrez@amd.com : 0; 121411308Santhony.gutierrez@amd.com 121511308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Stride is %d\n", stride); 121611308Santhony.gutierrez@amd.com 121711308Santhony.gutierrez@amd.com computeUnit->lastVaddrCU[mp_index] = vaddr; 121811308Santhony.gutierrez@amd.com computeUnit->lastVaddrPhase[simdId][mp_index] = vaddr; 121911308Santhony.gutierrez@amd.com computeUnit->lastVaddrWF[simdId][wfSlotId][mp_index] = vaddr; 122011308Santhony.gutierrez@amd.com 122111308Santhony.gutierrez@amd.com stride = (computeUnit->prefetchType == Enums::PF_STRIDE) ? 122211308Santhony.gutierrez@amd.com computeUnit->prefetchStride: stride; 122311308Santhony.gutierrez@amd.com 122411308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%#x to: CU[%d][%d][%d][%d]\n", vaddr, 122511308Santhony.gutierrez@amd.com computeUnit->cu_id, simdId, wfSlotId, mp_index); 122611308Santhony.gutierrez@amd.com 122711308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "Prefetching from %#x:", vaddr); 122811308Santhony.gutierrez@amd.com 122911308Santhony.gutierrez@amd.com // Prefetch Next few pages atomically 123011308Santhony.gutierrez@amd.com for (int pf = 1; pf <= computeUnit->prefetchDepth; ++pf) { 123111308Santhony.gutierrez@amd.com DPRINTF(GPUPrefetch, "%d * %d: %#x\n", pf, stride, 123211308Santhony.gutierrez@amd.com vaddr+stride*pf*TheISA::PageBytes); 123311308Santhony.gutierrez@amd.com 123411308Santhony.gutierrez@amd.com if (!stride) 123511308Santhony.gutierrez@amd.com break; 123611308Santhony.gutierrez@amd.com 123711308Santhony.gutierrez@amd.com Request *prefetch_req = new Request(0, vaddr + stride * pf * 123811308Santhony.gutierrez@amd.com TheISA::PageBytes, 123911308Santhony.gutierrez@amd.com sizeof(uint8_t), 0, 124011308Santhony.gutierrez@amd.com computeUnit->masterId(), 124111308Santhony.gutierrez@amd.com 0, 0, 0); 124211308Santhony.gutierrez@amd.com 124311308Santhony.gutierrez@amd.com PacketPtr prefetch_pkt = new Packet(prefetch_req, requestCmd); 124411308Santhony.gutierrez@amd.com uint8_t foo = 0; 124511308Santhony.gutierrez@amd.com prefetch_pkt->dataStatic(&foo); 124611308Santhony.gutierrez@amd.com 124711308Santhony.gutierrez@amd.com // Because it's atomic operation, only need TLB translation state 124811308Santhony.gutierrez@amd.com prefetch_pkt->senderState = 124911308Santhony.gutierrez@amd.com new TheISA::GpuTLB::TranslationState(TLB_mode, 125011308Santhony.gutierrez@amd.com computeUnit->shader->gpuTc, 125111308Santhony.gutierrez@amd.com true); 125211308Santhony.gutierrez@amd.com 125311308Santhony.gutierrez@amd.com // Currently prefetches are zero-latency, hence the sendFunctional 125411308Santhony.gutierrez@amd.com sendFunctional(prefetch_pkt); 125511308Santhony.gutierrez@amd.com 125611308Santhony.gutierrez@amd.com /* safe_cast the senderState */ 125711308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *tlb_state = 125811308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>( 125911308Santhony.gutierrez@amd.com prefetch_pkt->senderState); 126011308Santhony.gutierrez@amd.com 126111308Santhony.gutierrez@amd.com 126211308Santhony.gutierrez@amd.com delete tlb_state->tlbEntry; 126311308Santhony.gutierrez@amd.com delete tlb_state; 126411308Santhony.gutierrez@amd.com delete prefetch_pkt->req; 126511308Santhony.gutierrez@amd.com delete prefetch_pkt; 126611308Santhony.gutierrez@amd.com } 126711308Santhony.gutierrez@amd.com } 126811308Santhony.gutierrez@amd.com 126911308Santhony.gutierrez@amd.com // First we must convert the response cmd back to a request cmd so that 127011308Santhony.gutierrez@amd.com // the request can be sent through the cu's master port 127111308Santhony.gutierrez@amd.com PacketPtr new_pkt = new Packet(pkt->req, requestCmd); 127211308Santhony.gutierrez@amd.com new_pkt->dataStatic(pkt->getPtr<uint8_t>()); 127311308Santhony.gutierrez@amd.com delete pkt->senderState; 127411308Santhony.gutierrez@amd.com delete pkt; 127511308Santhony.gutierrez@amd.com 127611308Santhony.gutierrez@amd.com // New SenderState for the memory access 127711308Santhony.gutierrez@amd.com new_pkt->senderState = 127811308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::SenderState(gpuDynInst, mp_index, 127911308Santhony.gutierrez@amd.com nullptr); 128011308Santhony.gutierrez@amd.com 128111308Santhony.gutierrez@amd.com // translation is done. Schedule the mem_req_event at the appropriate 128211308Santhony.gutierrez@amd.com // cycle to send the timing memory request to ruby 128311308Santhony.gutierrez@amd.com ComputeUnit::DataPort::MemReqEvent *mem_req_event = 128411308Santhony.gutierrez@amd.com new ComputeUnit::DataPort::MemReqEvent(computeUnit->memPort[mp_index], 128511308Santhony.gutierrez@amd.com new_pkt); 128611308Santhony.gutierrez@amd.com 128711308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: index %d, addr %#x data scheduled\n", 128811308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 128911308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, mp_index, new_pkt->req->getPaddr()); 129011308Santhony.gutierrez@amd.com 129111308Santhony.gutierrez@amd.com computeUnit->schedule(mem_req_event, curTick() + 129211308Santhony.gutierrez@amd.com computeUnit->req_tick_latency); 129311308Santhony.gutierrez@amd.com 129411308Santhony.gutierrez@amd.com return true; 129511308Santhony.gutierrez@amd.com} 129611308Santhony.gutierrez@amd.com 129711308Santhony.gutierrez@amd.comconst char* 129811308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemReqEvent::description() const 129911308Santhony.gutierrez@amd.com{ 130011308Santhony.gutierrez@amd.com return "ComputeUnit memory request event"; 130111308Santhony.gutierrez@amd.com} 130211308Santhony.gutierrez@amd.com 130311308Santhony.gutierrez@amd.comvoid 130411308Santhony.gutierrez@amd.comComputeUnit::DataPort::MemReqEvent::process() 130511308Santhony.gutierrez@amd.com{ 130611308Santhony.gutierrez@amd.com SenderState *sender_state = safe_cast<SenderState*>(pkt->senderState); 130711308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = sender_state->_gpuDynInst; 130811308Santhony.gutierrez@amd.com ComputeUnit *compute_unit M5_VAR_USED = dataPort->computeUnit; 130911308Santhony.gutierrez@amd.com 131011308Santhony.gutierrez@amd.com if (!(dataPort->sendTimingReq(pkt))) { 131111308Santhony.gutierrez@amd.com dataPort->retries.push_back(std::make_pair(pkt, gpuDynInst)); 131211308Santhony.gutierrez@amd.com 131311308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 131411308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req failed!\n", 131511308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 131611308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, dataPort->index, 131711308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 131811308Santhony.gutierrez@amd.com } else { 131911308Santhony.gutierrez@amd.com DPRINTF(GPUPort, 132011308Santhony.gutierrez@amd.com "CU%d: WF[%d][%d]: index %d, addr %#x data req sent!\n", 132111308Santhony.gutierrez@amd.com compute_unit->cu_id, gpuDynInst->simdId, 132211308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, dataPort->index, 132311308Santhony.gutierrez@amd.com pkt->req->getPaddr()); 132411308Santhony.gutierrez@amd.com } 132511308Santhony.gutierrez@amd.com} 132611308Santhony.gutierrez@amd.com 132711308Santhony.gutierrez@amd.com/* 132811308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, 132911308Santhony.gutierrez@amd.com * if <retries> queue is not Retry sending the translation 133011308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 133111308Santhony.gutierrez@amd.com * a translation completes. 133211308Santhony.gutierrez@amd.com */ 133311308Santhony.gutierrez@amd.comvoid 133411308Santhony.gutierrez@amd.comComputeUnit::DTLBPort::recvReqRetry() 133511308Santhony.gutierrez@amd.com{ 133611308Santhony.gutierrez@amd.com int len = retries.size(); 133711308Santhony.gutierrez@amd.com 133811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: DTLB recvReqRetry - %d pending requests\n", 133911308Santhony.gutierrez@amd.com computeUnit->cu_id, len); 134011308Santhony.gutierrez@amd.com 134111308Santhony.gutierrez@amd.com assert(len > 0); 134211308Santhony.gutierrez@amd.com assert(isStalled()); 134311308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 134411308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 134511308Santhony.gutierrez@amd.com unstallPort(); 134611308Santhony.gutierrez@amd.com 134711308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 134811308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 134911308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 135011308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying D-translaton for address%#x", vaddr); 135111308Santhony.gutierrez@amd.com 135211308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 135311308Santhony.gutierrez@amd.com // Stall port 135411308Santhony.gutierrez@amd.com stallPort(); 135511308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 135611308Santhony.gutierrez@amd.com break; 135711308Santhony.gutierrez@amd.com } else { 135811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 135911308Santhony.gutierrez@amd.com retries.pop_front(); 136011308Santhony.gutierrez@amd.com } 136111308Santhony.gutierrez@amd.com } 136211308Santhony.gutierrez@amd.com} 136311308Santhony.gutierrez@amd.com 136411308Santhony.gutierrez@amd.combool 136511308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvTimingResp(PacketPtr pkt) 136611308Santhony.gutierrez@amd.com{ 136711308Santhony.gutierrez@amd.com Addr line M5_VAR_USED = pkt->req->getPaddr(); 136811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLBPort received %#x->%#x\n", 136911308Santhony.gutierrez@amd.com computeUnit->cu_id, pkt->req->getVaddr(), line); 137011308Santhony.gutierrez@amd.com 137111308Santhony.gutierrez@amd.com assert(pkt->senderState); 137211308Santhony.gutierrez@amd.com 137311308Santhony.gutierrez@amd.com // pop off the TLB translation state 137411308Santhony.gutierrez@amd.com TheISA::GpuTLB::TranslationState *translation_state = 137511308Santhony.gutierrez@amd.com safe_cast<TheISA::GpuTLB::TranslationState*>(pkt->senderState); 137611308Santhony.gutierrez@amd.com 137711308Santhony.gutierrez@amd.com bool success = translation_state->tlbEntry->valid; 137811308Santhony.gutierrez@amd.com delete translation_state->tlbEntry; 137911308Santhony.gutierrez@amd.com assert(!translation_state->ports.size()); 138011308Santhony.gutierrez@amd.com pkt->senderState = translation_state->saved; 138111308Santhony.gutierrez@amd.com delete translation_state; 138211308Santhony.gutierrez@amd.com 138311308Santhony.gutierrez@amd.com // use the original sender state to know how to close this transaction 138411308Santhony.gutierrez@amd.com ITLBPort::SenderState *sender_state = 138511308Santhony.gutierrez@amd.com safe_cast<ITLBPort::SenderState*>(pkt->senderState); 138611308Santhony.gutierrez@amd.com 138711308Santhony.gutierrez@amd.com // get the wavefront associated with this translation request 138811308Santhony.gutierrez@amd.com Wavefront *wavefront = sender_state->wavefront; 138911308Santhony.gutierrez@amd.com delete pkt->senderState; 139011308Santhony.gutierrez@amd.com 139111308Santhony.gutierrez@amd.com if (success) { 139211308Santhony.gutierrez@amd.com // pkt is reused in fetch(), don't delete it here. However, we must 139311308Santhony.gutierrez@amd.com // reset the command to be a request so that it can be sent through 139411308Santhony.gutierrez@amd.com // the cu's master port 139511308Santhony.gutierrez@amd.com assert(pkt->cmd == MemCmd::ReadResp); 139611308Santhony.gutierrez@amd.com pkt->cmd = MemCmd::ReadReq; 139711308Santhony.gutierrez@amd.com 139811308Santhony.gutierrez@amd.com computeUnit->fetchStage.fetch(pkt, wavefront); 139911308Santhony.gutierrez@amd.com } else { 140011308Santhony.gutierrez@amd.com if (wavefront->dropFetch) { 140111308Santhony.gutierrez@amd.com assert(wavefront->instructionBuffer.empty()); 140211308Santhony.gutierrez@amd.com wavefront->dropFetch = false; 140311308Santhony.gutierrez@amd.com } 140411308Santhony.gutierrez@amd.com 140511308Santhony.gutierrez@amd.com wavefront->pendingFetch = 0; 140611308Santhony.gutierrez@amd.com } 140711308Santhony.gutierrez@amd.com 140811308Santhony.gutierrez@amd.com return true; 140911308Santhony.gutierrez@amd.com} 141011308Santhony.gutierrez@amd.com 141111308Santhony.gutierrez@amd.com/* 141211308Santhony.gutierrez@amd.com * The initial translation request could have been rejected, if 141311308Santhony.gutierrez@amd.com * <retries> queue is not empty. Retry sending the translation 141411308Santhony.gutierrez@amd.com * request. sendRetry() is called from the peer port whenever 141511308Santhony.gutierrez@amd.com * a translation completes. 141611308Santhony.gutierrez@amd.com */ 141711308Santhony.gutierrez@amd.comvoid 141811308Santhony.gutierrez@amd.comComputeUnit::ITLBPort::recvReqRetry() 141911308Santhony.gutierrez@amd.com{ 142011308Santhony.gutierrez@amd.com 142111308Santhony.gutierrez@amd.com int len = retries.size(); 142211308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: ITLB recvReqRetry - %d pending requests\n", len); 142311308Santhony.gutierrez@amd.com 142411308Santhony.gutierrez@amd.com assert(len > 0); 142511308Santhony.gutierrez@amd.com assert(isStalled()); 142611308Santhony.gutierrez@amd.com 142711308Santhony.gutierrez@amd.com // recvReqRetry is an indication that the resource on which this 142811308Santhony.gutierrez@amd.com // port was stalling on is freed. So, remove the stall first 142911308Santhony.gutierrez@amd.com unstallPort(); 143011308Santhony.gutierrez@amd.com 143111308Santhony.gutierrez@amd.com for (int i = 0; i < len; ++i) { 143211308Santhony.gutierrez@amd.com PacketPtr pkt = retries.front(); 143311308Santhony.gutierrez@amd.com Addr vaddr M5_VAR_USED = pkt->req->getVaddr(); 143411308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, "CU%d: retrying I-translaton for address%#x", vaddr); 143511308Santhony.gutierrez@amd.com 143611308Santhony.gutierrez@amd.com if (!sendTimingReq(pkt)) { 143711308Santhony.gutierrez@amd.com stallPort(); // Stall port 143811308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": failed again\n"); 143911308Santhony.gutierrez@amd.com break; 144011308Santhony.gutierrez@amd.com } else { 144111308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": successful\n"); 144211308Santhony.gutierrez@amd.com retries.pop_front(); 144311308Santhony.gutierrez@amd.com } 144411308Santhony.gutierrez@amd.com } 144511308Santhony.gutierrez@amd.com} 144611308Santhony.gutierrez@amd.com 144711308Santhony.gutierrez@amd.comvoid 144811308Santhony.gutierrez@amd.comComputeUnit::regStats() 144911308Santhony.gutierrez@amd.com{ 145011308Santhony.gutierrez@amd.com tlbCycles 145111308Santhony.gutierrez@amd.com .name(name() + ".tlb_cycles") 145211308Santhony.gutierrez@amd.com .desc("total number of cycles for all uncoalesced requests") 145311308Santhony.gutierrez@amd.com ; 145411308Santhony.gutierrez@amd.com 145511308Santhony.gutierrez@amd.com tlbRequests 145611308Santhony.gutierrez@amd.com .name(name() + ".tlb_requests") 145711308Santhony.gutierrez@amd.com .desc("number of uncoalesced requests") 145811308Santhony.gutierrez@amd.com ; 145911308Santhony.gutierrez@amd.com 146011308Santhony.gutierrez@amd.com tlbLatency 146111308Santhony.gutierrez@amd.com .name(name() + ".avg_translation_latency") 146211308Santhony.gutierrez@amd.com .desc("Avg. translation latency for data translations") 146311308Santhony.gutierrez@amd.com ; 146411308Santhony.gutierrez@amd.com 146511308Santhony.gutierrez@amd.com tlbLatency = tlbCycles / tlbRequests; 146611308Santhony.gutierrez@amd.com 146711308Santhony.gutierrez@amd.com hitsPerTLBLevel 146811308Santhony.gutierrez@amd.com .init(4) 146911308Santhony.gutierrez@amd.com .name(name() + ".TLB_hits_distribution") 147011308Santhony.gutierrez@amd.com .desc("TLB hits distribution (0 for page table, x for Lx-TLB") 147111308Santhony.gutierrez@amd.com ; 147211308Santhony.gutierrez@amd.com 147311308Santhony.gutierrez@amd.com // fixed number of TLB levels 147411308Santhony.gutierrez@amd.com for (int i = 0; i < 4; ++i) { 147511308Santhony.gutierrez@amd.com if (!i) 147611308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i,"page_table"); 147711308Santhony.gutierrez@amd.com else 147811308Santhony.gutierrez@amd.com hitsPerTLBLevel.subname(i, csprintf("L%d_TLB",i)); 147911308Santhony.gutierrez@amd.com } 148011308Santhony.gutierrez@amd.com 148111308Santhony.gutierrez@amd.com execRateDist 148211308Santhony.gutierrez@amd.com .init(0, 10, 2) 148311308Santhony.gutierrez@amd.com .name(name() + ".inst_exec_rate") 148411308Santhony.gutierrez@amd.com .desc("Instruction Execution Rate: Number of executed vector " 148511308Santhony.gutierrez@amd.com "instructions per cycle") 148611308Santhony.gutierrez@amd.com ; 148711308Santhony.gutierrez@amd.com 148811308Santhony.gutierrez@amd.com ldsBankConflictDist 148911308Santhony.gutierrez@amd.com .init(0, VSZ, 2) 149011308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_conflicts") 149111308Santhony.gutierrez@amd.com .desc("Number of bank conflicts per LDS memory packet") 149211308Santhony.gutierrez@amd.com ; 149311308Santhony.gutierrez@amd.com 149411308Santhony.gutierrez@amd.com ldsBankAccesses 149511308Santhony.gutierrez@amd.com .name(name() + ".lds_bank_access_cnt") 149611308Santhony.gutierrez@amd.com .desc("Total number of LDS bank accesses") 149711308Santhony.gutierrez@amd.com ; 149811308Santhony.gutierrez@amd.com 149911308Santhony.gutierrez@amd.com pageDivergenceDist 150011308Santhony.gutierrez@amd.com // A wavefront can touch 1 to VSZ pages per memory instruction. 150111308Santhony.gutierrez@amd.com // The number of pages per bin can be configured (here it's 4). 150211308Santhony.gutierrez@amd.com .init(1, VSZ, 4) 150311308Santhony.gutierrez@amd.com .name(name() + ".page_divergence_dist") 150411308Santhony.gutierrez@amd.com .desc("pages touched per wf (over all mem. instr.)") 150511308Santhony.gutierrez@amd.com ; 150611308Santhony.gutierrez@amd.com 150711308Santhony.gutierrez@amd.com controlFlowDivergenceDist 150811308Santhony.gutierrez@amd.com .init(1, VSZ, 4) 150911308Santhony.gutierrez@amd.com .name(name() + ".warp_execution_dist") 151011308Santhony.gutierrez@amd.com .desc("number of lanes active per instruction (oval all instructions)") 151111308Santhony.gutierrez@amd.com ; 151211308Santhony.gutierrez@amd.com 151311308Santhony.gutierrez@amd.com activeLanesPerGMemInstrDist 151411308Santhony.gutierrez@amd.com .init(1, VSZ, 4) 151511308Santhony.gutierrez@amd.com .name(name() + ".gmem_lanes_execution_dist") 151611308Santhony.gutierrez@amd.com .desc("number of active lanes per global memory instruction") 151711308Santhony.gutierrez@amd.com ; 151811308Santhony.gutierrez@amd.com 151911308Santhony.gutierrez@amd.com activeLanesPerLMemInstrDist 152011308Santhony.gutierrez@amd.com .init(1, VSZ, 4) 152111308Santhony.gutierrez@amd.com .name(name() + ".lmem_lanes_execution_dist") 152211308Santhony.gutierrez@amd.com .desc("number of active lanes per local memory instruction") 152311308Santhony.gutierrez@amd.com ; 152411308Santhony.gutierrez@amd.com 152511308Santhony.gutierrez@amd.com numInstrExecuted 152611308Santhony.gutierrez@amd.com .name(name() + ".num_instr_executed") 152711308Santhony.gutierrez@amd.com .desc("number of instructions executed") 152811308Santhony.gutierrez@amd.com ; 152911308Santhony.gutierrez@amd.com 153011308Santhony.gutierrez@amd.com numVecOpsExecuted 153111308Santhony.gutierrez@amd.com .name(name() + ".num_vec_ops_executed") 153211308Santhony.gutierrez@amd.com .desc("number of vec ops executed (e.g. VSZ/inst)") 153311308Santhony.gutierrez@amd.com ; 153411308Santhony.gutierrez@amd.com 153511308Santhony.gutierrez@amd.com totalCycles 153611308Santhony.gutierrez@amd.com .name(name() + ".num_total_cycles") 153711308Santhony.gutierrez@amd.com .desc("number of cycles the CU ran for") 153811308Santhony.gutierrez@amd.com ; 153911308Santhony.gutierrez@amd.com 154011308Santhony.gutierrez@amd.com ipc 154111308Santhony.gutierrez@amd.com .name(name() + ".ipc") 154211308Santhony.gutierrez@amd.com .desc("Instructions per cycle (this CU only)") 154311308Santhony.gutierrez@amd.com ; 154411308Santhony.gutierrez@amd.com 154511308Santhony.gutierrez@amd.com vpc 154611308Santhony.gutierrez@amd.com .name(name() + ".vpc") 154711308Santhony.gutierrez@amd.com .desc("Vector Operations per cycle (this CU only)") 154811308Santhony.gutierrez@amd.com ; 154911308Santhony.gutierrez@amd.com 155011308Santhony.gutierrez@amd.com numALUInstsExecuted 155111308Santhony.gutierrez@amd.com .name(name() + ".num_alu_insts_executed") 155211308Santhony.gutierrez@amd.com .desc("Number of dynamic non-GM memory insts executed") 155311308Santhony.gutierrez@amd.com ; 155411308Santhony.gutierrez@amd.com 155511308Santhony.gutierrez@amd.com wgBlockedDueLdsAllocation 155611308Santhony.gutierrez@amd.com .name(name() + ".wg_blocked_due_lds_alloc") 155711308Santhony.gutierrez@amd.com .desc("Workgroup blocked due to LDS capacity") 155811308Santhony.gutierrez@amd.com ; 155911308Santhony.gutierrez@amd.com 156011308Santhony.gutierrez@amd.com ipc = numInstrExecuted / totalCycles; 156111308Santhony.gutierrez@amd.com vpc = numVecOpsExecuted / totalCycles; 156211308Santhony.gutierrez@amd.com 156311308Santhony.gutierrez@amd.com numTimesWgBlockedDueVgprAlloc 156411308Santhony.gutierrez@amd.com .name(name() + ".times_wg_blocked_due_vgpr_alloc") 156511308Santhony.gutierrez@amd.com .desc("Number of times WGs are blocked due to VGPR allocation per SIMD") 156611308Santhony.gutierrez@amd.com ; 156711308Santhony.gutierrez@amd.com 156811308Santhony.gutierrez@amd.com dynamicGMemInstrCnt 156911308Santhony.gutierrez@amd.com .name(name() + ".global_mem_instr_cnt") 157011308Santhony.gutierrez@amd.com .desc("dynamic global memory instructions count") 157111308Santhony.gutierrez@amd.com ; 157211308Santhony.gutierrez@amd.com 157311308Santhony.gutierrez@amd.com dynamicLMemInstrCnt 157411308Santhony.gutierrez@amd.com .name(name() + ".local_mem_instr_cnt") 157511308Santhony.gutierrez@amd.com .desc("dynamic local memory intruction count") 157611308Santhony.gutierrez@amd.com ; 157711308Santhony.gutierrez@amd.com 157811308Santhony.gutierrez@amd.com numALUInstsExecuted = numInstrExecuted - dynamicGMemInstrCnt - 157911308Santhony.gutierrez@amd.com dynamicLMemInstrCnt; 158011308Santhony.gutierrez@amd.com 158111308Santhony.gutierrez@amd.com completedWfs 158211308Santhony.gutierrez@amd.com .name(name() + ".num_completed_wfs") 158311308Santhony.gutierrez@amd.com .desc("number of completed wavefronts") 158411308Santhony.gutierrez@amd.com ; 158511308Santhony.gutierrez@amd.com 158611308Santhony.gutierrez@amd.com numCASOps 158711308Santhony.gutierrez@amd.com .name(name() + ".num_CAS_ops") 158811308Santhony.gutierrez@amd.com .desc("number of compare and swap operations") 158911308Santhony.gutierrez@amd.com ; 159011308Santhony.gutierrez@amd.com 159111308Santhony.gutierrez@amd.com numFailedCASOps 159211308Santhony.gutierrez@amd.com .name(name() + ".num_failed_CAS_ops") 159311308Santhony.gutierrez@amd.com .desc("number of compare and swap operations that failed") 159411308Santhony.gutierrez@amd.com ; 159511308Santhony.gutierrez@amd.com 159611308Santhony.gutierrez@amd.com // register stats of pipeline stages 159711308Santhony.gutierrez@amd.com fetchStage.regStats(); 159811308Santhony.gutierrez@amd.com scoreboardCheckStage.regStats(); 159911308Santhony.gutierrez@amd.com scheduleStage.regStats(); 160011308Santhony.gutierrez@amd.com execStage.regStats(); 160111308Santhony.gutierrez@amd.com 160211308Santhony.gutierrez@amd.com // register stats of memory pipeline 160311308Santhony.gutierrez@amd.com globalMemoryPipe.regStats(); 160411308Santhony.gutierrez@amd.com localMemoryPipe.regStats(); 160511308Santhony.gutierrez@amd.com} 160611308Santhony.gutierrez@amd.com 160711308Santhony.gutierrez@amd.comvoid 160811308Santhony.gutierrez@amd.comComputeUnit::updatePageDivergenceDist(Addr addr) 160911308Santhony.gutierrez@amd.com{ 161011308Santhony.gutierrez@amd.com Addr virt_page_addr = roundDown(addr, TheISA::PageBytes); 161111308Santhony.gutierrez@amd.com 161211308Santhony.gutierrez@amd.com if (!pagesTouched.count(virt_page_addr)) 161311308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr] = 1; 161411308Santhony.gutierrez@amd.com else 161511308Santhony.gutierrez@amd.com pagesTouched[virt_page_addr]++; 161611308Santhony.gutierrez@amd.com} 161711308Santhony.gutierrez@amd.com 161811308Santhony.gutierrez@amd.comvoid 161911308Santhony.gutierrez@amd.comComputeUnit::CUExitCallback::process() 162011308Santhony.gutierrez@amd.com{ 162111308Santhony.gutierrez@amd.com if (computeUnit->countPages) { 162211308Santhony.gutierrez@amd.com std::ostream *page_stat_file = 162311364Sandreas.hansson@arm.com simout.create(computeUnit->name().c_str())->stream(); 162411308Santhony.gutierrez@amd.com 162511308Santhony.gutierrez@amd.com *page_stat_file << "page, wavefront accesses, workitem accesses" << 162611308Santhony.gutierrez@amd.com std::endl; 162711308Santhony.gutierrez@amd.com 162811308Santhony.gutierrez@amd.com for (auto iter : computeUnit->pageAccesses) { 162911308Santhony.gutierrez@amd.com *page_stat_file << std::hex << iter.first << ","; 163011308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.first << ","; 163111308Santhony.gutierrez@amd.com *page_stat_file << std::dec << iter.second.second << std::endl; 163211308Santhony.gutierrez@amd.com } 163311308Santhony.gutierrez@amd.com } 163411308Santhony.gutierrez@amd.com } 163511308Santhony.gutierrez@amd.com 163611308Santhony.gutierrez@amd.combool 163711308Santhony.gutierrez@amd.comComputeUnit::isDone() const 163811308Santhony.gutierrez@amd.com{ 163911308Santhony.gutierrez@amd.com for (int i = 0; i < numSIMDs; ++i) { 164011308Santhony.gutierrez@amd.com if (!isSimdDone(i)) { 164111308Santhony.gutierrez@amd.com return false; 164211308Santhony.gutierrez@amd.com } 164311308Santhony.gutierrez@amd.com } 164411308Santhony.gutierrez@amd.com 164511308Santhony.gutierrez@amd.com bool glbMemBusRdy = true; 164611308Santhony.gutierrez@amd.com for (int j = 0; j < numGlbMemUnits; ++j) { 164711308Santhony.gutierrez@amd.com glbMemBusRdy &= vrfToGlobalMemPipeBus[j].rdy(); 164811308Santhony.gutierrez@amd.com } 164911308Santhony.gutierrez@amd.com bool locMemBusRdy = true; 165011308Santhony.gutierrez@amd.com for (int j = 0; j < numLocMemUnits; ++j) { 165111308Santhony.gutierrez@amd.com locMemBusRdy &= vrfToLocalMemPipeBus[j].rdy(); 165211308Santhony.gutierrez@amd.com } 165311308Santhony.gutierrez@amd.com 165411308Santhony.gutierrez@amd.com if (!globalMemoryPipe.isGMLdRespFIFOWrRdy() || 165511308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMStRespFIFOWrRdy() || 165611308Santhony.gutierrez@amd.com !globalMemoryPipe.isGMReqFIFOWrRdy() || !localMemoryPipe.isLMReqFIFOWrRdy() 165711308Santhony.gutierrez@amd.com || !localMemoryPipe.isLMRespFIFOWrRdy() || !locMemToVrfBus.rdy() || 165811308Santhony.gutierrez@amd.com !glbMemToVrfBus.rdy() || !locMemBusRdy || !glbMemBusRdy) { 165911308Santhony.gutierrez@amd.com return false; 166011308Santhony.gutierrez@amd.com } 166111308Santhony.gutierrez@amd.com 166211308Santhony.gutierrez@amd.com return true; 166311308Santhony.gutierrez@amd.com} 166411308Santhony.gutierrez@amd.com 166511308Santhony.gutierrez@amd.comint32_t 166611308Santhony.gutierrez@amd.comComputeUnit::getRefCounter(const uint32_t dispatchId, const uint32_t wgId) const 166711308Santhony.gutierrez@amd.com{ 166811308Santhony.gutierrez@amd.com return lds.getRefCounter(dispatchId, wgId); 166911308Santhony.gutierrez@amd.com} 167011308Santhony.gutierrez@amd.com 167111308Santhony.gutierrez@amd.combool 167211308Santhony.gutierrez@amd.comComputeUnit::isSimdDone(uint32_t simdId) const 167311308Santhony.gutierrez@amd.com{ 167411308Santhony.gutierrez@amd.com assert(simdId < numSIMDs); 167511308Santhony.gutierrez@amd.com 167611308Santhony.gutierrez@amd.com for (int i=0; i < numGlbMemUnits; ++i) { 167711308Santhony.gutierrez@amd.com if (!vrfToGlobalMemPipeBus[i].rdy()) 167811308Santhony.gutierrez@amd.com return false; 167911308Santhony.gutierrez@amd.com } 168011308Santhony.gutierrez@amd.com for (int i=0; i < numLocMemUnits; ++i) { 168111308Santhony.gutierrez@amd.com if (!vrfToLocalMemPipeBus[i].rdy()) 168211308Santhony.gutierrez@amd.com return false; 168311308Santhony.gutierrez@amd.com } 168411308Santhony.gutierrez@amd.com if (!aluPipe[simdId].rdy()) { 168511308Santhony.gutierrez@amd.com return false; 168611308Santhony.gutierrez@amd.com } 168711308Santhony.gutierrez@amd.com 168811308Santhony.gutierrez@amd.com for (int i_wf = 0; i_wf < shader->n_wf; ++i_wf){ 168911308Santhony.gutierrez@amd.com if (wfList[simdId][i_wf]->status != Wavefront::S_STOPPED) { 169011308Santhony.gutierrez@amd.com return false; 169111308Santhony.gutierrez@amd.com } 169211308Santhony.gutierrez@amd.com } 169311308Santhony.gutierrez@amd.com 169411308Santhony.gutierrez@amd.com return true; 169511308Santhony.gutierrez@amd.com} 169611308Santhony.gutierrez@amd.com 169711308Santhony.gutierrez@amd.com/** 169811308Santhony.gutierrez@amd.com * send a general request to the LDS 169911308Santhony.gutierrez@amd.com * make sure to look at the return value here as your request might be 170011308Santhony.gutierrez@amd.com * NACK'd and returning false means that you have to have some backup plan 170111308Santhony.gutierrez@amd.com */ 170211308Santhony.gutierrez@amd.combool 170311308Santhony.gutierrez@amd.comComputeUnit::sendToLds(GPUDynInstPtr gpuDynInst) 170411308Santhony.gutierrez@amd.com{ 170511308Santhony.gutierrez@amd.com // this is just a request to carry the GPUDynInstPtr 170611308Santhony.gutierrez@amd.com // back and forth 170711308Santhony.gutierrez@amd.com Request *newRequest = new Request(); 170811308Santhony.gutierrez@amd.com newRequest->setPaddr(0x0); 170911308Santhony.gutierrez@amd.com 171011308Santhony.gutierrez@amd.com // ReadReq is not evaluted by the LDS but the Packet ctor requires this 171111308Santhony.gutierrez@amd.com PacketPtr newPacket = new Packet(newRequest, MemCmd::ReadReq); 171211308Santhony.gutierrez@amd.com 171311308Santhony.gutierrez@amd.com // This is the SenderState needed upon return 171411308Santhony.gutierrez@amd.com newPacket->senderState = new LDSPort::SenderState(gpuDynInst); 171511308Santhony.gutierrez@amd.com 171611308Santhony.gutierrez@amd.com return ldsPort->sendTimingReq(newPacket); 171711308Santhony.gutierrez@amd.com} 171811308Santhony.gutierrez@amd.com 171911308Santhony.gutierrez@amd.com/** 172011308Santhony.gutierrez@amd.com * get the result of packets sent to the LDS when they return 172111308Santhony.gutierrez@amd.com */ 172211308Santhony.gutierrez@amd.combool 172311308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvTimingResp(PacketPtr packet) 172411308Santhony.gutierrez@amd.com{ 172511308Santhony.gutierrez@amd.com const ComputeUnit::LDSPort::SenderState *senderState = 172611308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState *>(packet->senderState); 172711308Santhony.gutierrez@amd.com 172811308Santhony.gutierrez@amd.com fatal_if(!senderState, "did not get the right sort of sender state"); 172911308Santhony.gutierrez@amd.com 173011308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst = senderState->getMemInst(); 173111308Santhony.gutierrez@amd.com 173211308Santhony.gutierrez@amd.com delete packet->senderState; 173311308Santhony.gutierrez@amd.com delete packet->req; 173411308Santhony.gutierrez@amd.com delete packet; 173511308Santhony.gutierrez@amd.com 173611308Santhony.gutierrez@amd.com computeUnit->localMemoryPipe.getLMRespFIFO().push(gpuDynInst); 173711308Santhony.gutierrez@amd.com return true; 173811308Santhony.gutierrez@amd.com} 173911308Santhony.gutierrez@amd.com 174011308Santhony.gutierrez@amd.com/** 174111308Santhony.gutierrez@amd.com * attempt to send this packet, either the port is already stalled, the request 174211308Santhony.gutierrez@amd.com * is nack'd and must stall or the request goes through 174311308Santhony.gutierrez@amd.com * when a request cannot be sent, add it to the retries queue 174411308Santhony.gutierrez@amd.com */ 174511308Santhony.gutierrez@amd.combool 174611308Santhony.gutierrez@amd.comComputeUnit::LDSPort::sendTimingReq(PacketPtr pkt) 174711308Santhony.gutierrez@amd.com{ 174811308Santhony.gutierrez@amd.com ComputeUnit::LDSPort::SenderState *sender_state = 174911308Santhony.gutierrez@amd.com dynamic_cast<ComputeUnit::LDSPort::SenderState*>(pkt->senderState); 175011308Santhony.gutierrez@amd.com fatal_if(!sender_state, "packet without a valid sender state"); 175111308Santhony.gutierrez@amd.com 175211308Santhony.gutierrez@amd.com GPUDynInstPtr gpuDynInst M5_VAR_USED = sender_state->getMemInst(); 175311308Santhony.gutierrez@amd.com 175411308Santhony.gutierrez@amd.com if (isStalled()) { 175511308Santhony.gutierrez@amd.com fatal_if(retries.empty(), "must have retries waiting to be stalled"); 175611308Santhony.gutierrez@amd.com 175711308Santhony.gutierrez@amd.com retries.push(pkt); 175811308Santhony.gutierrez@amd.com 175911308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: LDS send failed!\n", 176011308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 176111308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId); 176211308Santhony.gutierrez@amd.com return false; 176311308Santhony.gutierrez@amd.com } else if (!MasterPort::sendTimingReq(pkt)) { 176411308Santhony.gutierrez@amd.com // need to stall the LDS port until a recvReqRetry() is received 176511308Santhony.gutierrez@amd.com // this indicates that there is more space 176611308Santhony.gutierrez@amd.com stallPort(); 176711308Santhony.gutierrez@amd.com retries.push(pkt); 176811308Santhony.gutierrez@amd.com 176911308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req failed!\n", 177011308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 177111308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 177211308Santhony.gutierrez@amd.com return false; 177311308Santhony.gutierrez@amd.com } else { 177411308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: WF[%d][%d]: addr %#x lds req sent!\n", 177511308Santhony.gutierrez@amd.com computeUnit->cu_id, gpuDynInst->simdId, 177611308Santhony.gutierrez@amd.com gpuDynInst->wfSlotId, pkt->req->getPaddr()); 177711308Santhony.gutierrez@amd.com return true; 177811308Santhony.gutierrez@amd.com } 177911308Santhony.gutierrez@amd.com} 178011308Santhony.gutierrez@amd.com 178111308Santhony.gutierrez@amd.com/** 178211308Santhony.gutierrez@amd.com * the bus is telling the port that there is now space so retrying stalled 178311308Santhony.gutierrez@amd.com * requests should work now 178411308Santhony.gutierrez@amd.com * this allows the port to have a request be nack'd and then have the receiver 178511308Santhony.gutierrez@amd.com * say when there is space, rather than simply retrying the send every cycle 178611308Santhony.gutierrez@amd.com */ 178711308Santhony.gutierrez@amd.comvoid 178811308Santhony.gutierrez@amd.comComputeUnit::LDSPort::recvReqRetry() 178911308Santhony.gutierrez@amd.com{ 179011308Santhony.gutierrez@amd.com auto queueSize = retries.size(); 179111308Santhony.gutierrez@amd.com 179211308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: LDSPort recvReqRetry - %d pending requests\n", 179311308Santhony.gutierrez@amd.com computeUnit->cu_id, queueSize); 179411308Santhony.gutierrez@amd.com 179511308Santhony.gutierrez@amd.com fatal_if(queueSize < 1, 179611308Santhony.gutierrez@amd.com "why was there a recvReqRetry() with no pending reqs?"); 179711308Santhony.gutierrez@amd.com fatal_if(!isStalled(), 179811308Santhony.gutierrez@amd.com "recvReqRetry() happened when the port was not stalled"); 179911308Santhony.gutierrez@amd.com 180011308Santhony.gutierrez@amd.com unstallPort(); 180111308Santhony.gutierrez@amd.com 180211308Santhony.gutierrez@amd.com while (!retries.empty()) { 180311308Santhony.gutierrez@amd.com PacketPtr packet = retries.front(); 180411308Santhony.gutierrez@amd.com 180511308Santhony.gutierrez@amd.com DPRINTF(GPUPort, "CU%d: retrying LDS send\n", computeUnit->cu_id); 180611308Santhony.gutierrez@amd.com 180711308Santhony.gutierrez@amd.com if (!MasterPort::sendTimingReq(packet)) { 180811308Santhony.gutierrez@amd.com // Stall port 180911308Santhony.gutierrez@amd.com stallPort(); 181011308Santhony.gutierrez@amd.com DPRINTF(GPUPort, ": LDS send failed again\n"); 181111308Santhony.gutierrez@amd.com break; 181211308Santhony.gutierrez@amd.com } else { 181311308Santhony.gutierrez@amd.com DPRINTF(GPUTLB, ": LDS send successful\n"); 181411308Santhony.gutierrez@amd.com retries.pop(); 181511308Santhony.gutierrez@amd.com } 181611308Santhony.gutierrez@amd.com } 181711308Santhony.gutierrez@amd.com} 1818