GPU.py revision 13665
16019Shines@cs.fsu.edu# 27093Sgblack@eecs.umich.edu# Copyright (c) 2015 Advanced Micro Devices, Inc. 37093Sgblack@eecs.umich.edu# All rights reserved. 47093Sgblack@eecs.umich.edu# 57093Sgblack@eecs.umich.edu# For use for simulation and test purposes only 67093Sgblack@eecs.umich.edu# 77093Sgblack@eecs.umich.edu# Redistribution and use in source and binary forms, with or without 87093Sgblack@eecs.umich.edu# modification, are permitted provided that the following conditions are met: 97093Sgblack@eecs.umich.edu# 107093Sgblack@eecs.umich.edu# 1. Redistributions of source code must retain the above copyright notice, 117093Sgblack@eecs.umich.edu# this list of conditions and the following disclaimer. 127093Sgblack@eecs.umich.edu# 137093Sgblack@eecs.umich.edu# 2. Redistributions in binary form must reproduce the above copyright notice, 146019Shines@cs.fsu.edu# this list of conditions and the following disclaimer in the documentation 156019Shines@cs.fsu.edu# and/or other materials provided with the distribution. 166019Shines@cs.fsu.edu# 176019Shines@cs.fsu.edu# 3. Neither the name of the copyright holder nor the names of its contributors 186019Shines@cs.fsu.edu# may be used to endorse or promote products derived from this software 196019Shines@cs.fsu.edu# without specific prior written permission. 206019Shines@cs.fsu.edu# 216019Shines@cs.fsu.edu# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 226019Shines@cs.fsu.edu# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 236019Shines@cs.fsu.edu# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 246019Shines@cs.fsu.edu# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE 256019Shines@cs.fsu.edu# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 266019Shines@cs.fsu.edu# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 276019Shines@cs.fsu.edu# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 286019Shines@cs.fsu.edu# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 296019Shines@cs.fsu.edu# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 306019Shines@cs.fsu.edu# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 316019Shines@cs.fsu.edu# POSSIBILITY OF SUCH DAMAGE. 326019Shines@cs.fsu.edu# 336019Shines@cs.fsu.edu# Author: Steve Reinhardt 346019Shines@cs.fsu.edu# 356019Shines@cs.fsu.edu 366019Shines@cs.fsu.edufrom m5.defines import buildEnv 376019Shines@cs.fsu.edufrom m5.params import * 386019Shines@cs.fsu.edufrom m5.proxy import * 396019Shines@cs.fsu.edufrom m5.SimObject import SimObject 406019Shines@cs.fsu.edu 416735Sgblack@eecs.umich.edufrom m5.objects.ClockedObject import ClockedObject 426735Sgblack@eecs.umich.edufrom m5.objects.Device import DmaDevice 436019Shines@cs.fsu.edufrom m5.objects.MemObject import MemObject 446019Shines@cs.fsu.edufrom m5.objects.Process import EmulatedDriver 456019Shines@cs.fsu.edufrom m5.objects.Bridge import Bridge 468229Snate@binkert.orgfrom m5.objects.LdsState import LdsState 478229Snate@binkert.org 486019Shines@cs.fsu.educlass PrefetchType(Enum): vals = [ 498232Snate@binkert.org 'PF_CU', 508782Sgblack@eecs.umich.edu 'PF_PHASE', 516019Shines@cs.fsu.edu 'PF_WF', 526019Shines@cs.fsu.edu 'PF_STRIDE', 536019Shines@cs.fsu.edu 'PF_END', 546019Shines@cs.fsu.edu ] 557362Sgblack@eecs.umich.edu 566735Sgblack@eecs.umich.educlass VectorRegisterFile(SimObject): 576019Shines@cs.fsu.edu type = 'VectorRegisterFile' 587362Sgblack@eecs.umich.edu cxx_class = 'VectorRegisterFile' 596735Sgblack@eecs.umich.edu cxx_header = 'gpu-compute/vector_register_file.hh' 606019Shines@cs.fsu.edu 617362Sgblack@eecs.umich.edu simd_id = Param.Int(0, 'SIMD ID associated with this VRF') 626735Sgblack@eecs.umich.edu num_regs_per_simd = Param.Int(2048, 'number of vector registers per SIMD') 636019Shines@cs.fsu.edu wfSize = Param.Int(64, 'Wavefront size (in work items)') 647362Sgblack@eecs.umich.edu min_alloc = Param.Int(4, 'min number of VGPRs allocated per WF') 656735Sgblack@eecs.umich.edu 666019Shines@cs.fsu.educlass Wavefront(SimObject): 677362Sgblack@eecs.umich.edu type = 'Wavefront' 686735Sgblack@eecs.umich.edu cxx_class = 'Wavefront' 696019Shines@cs.fsu.edu cxx_header = 'gpu-compute/wavefront.hh' 707362Sgblack@eecs.umich.edu 716735Sgblack@eecs.umich.edu simdId = Param.Int('SIMD id (0-ComputeUnit.num_SIMDs)') 726019Shines@cs.fsu.edu wf_slot_id = Param.Int('wavefront id (0-ComputeUnit.max_wfs)') 737362Sgblack@eecs.umich.edu wfSize = Param.Int(64, 'Wavefront size (in work items)') 746735Sgblack@eecs.umich.edu 756019Shines@cs.fsu.educlass ComputeUnit(MemObject): 767652Sminkyu.jeong@arm.com type = 'ComputeUnit' 777652Sminkyu.jeong@arm.com cxx_class = 'ComputeUnit' 787652Sminkyu.jeong@arm.com cxx_header = 'gpu-compute/compute_unit.hh' 798518Sgeoffrey.blake@arm.com 808518Sgeoffrey.blake@arm.com wavefronts = VectorParam.Wavefront('Number of wavefronts') 816735Sgblack@eecs.umich.edu wfSize = Param.Int(64, 'Wavefront size (in work items)') 827362Sgblack@eecs.umich.edu num_SIMDs = Param.Int(4, 'number of SIMD units per CU') 836735Sgblack@eecs.umich.edu 846735Sgblack@eecs.umich.edu spbypass_pipe_length = Param.Int(4, 'vector ALU Single Precision bypass '\ 856019Shines@cs.fsu.edu 'latency') 866735Sgblack@eecs.umich.edu 877400SAli.Saidi@ARM.com dpbypass_pipe_length = Param.Int(8, 'vector ALU Double Precision bypass '\ 886735Sgblack@eecs.umich.edu 'latency') 896735Sgblack@eecs.umich.edu 906735Sgblack@eecs.umich.edu issue_period = Param.Int(4, 'number of cycles per issue period') 917400SAli.Saidi@ARM.com num_global_mem_pipes = Param.Int(1,'number of global memory pipes per CU') 926735Sgblack@eecs.umich.edu num_shared_mem_pipes = Param.Int(1,'number of shared memory pipes per CU') 936735Sgblack@eecs.umich.edu n_wf = Param.Int(1, 'Number of wavefront slots per SIMD') 946735Sgblack@eecs.umich.edu mem_req_latency = Param.Int(9, "Latency for request from the cu to ruby. "\ 956019Shines@cs.fsu.edu "Represents the pipeline to reach the TCP and "\ 966019Shines@cs.fsu.edu "specified in GPU clock cycles") 976019Shines@cs.fsu.edu mem_resp_latency = Param.Int(9, "Latency for responses from ruby to the "\ 986735Sgblack@eecs.umich.edu "cu. Represents the pipeline between the TCP "\ 997678Sgblack@eecs.umich.edu "and cu as well as TCP data array access. "\ 1006019Shines@cs.fsu.edu "Specified in GPU clock cycles") 1016735Sgblack@eecs.umich.edu system = Param.System(Parent.any, "system object") 1026735Sgblack@eecs.umich.edu cu_id = Param.Int('CU id') 1038782Sgblack@eecs.umich.edu vrf_to_coalescer_bus_width = Param.Int(32, "VRF->Coalescer data bus width "\ 1048782Sgblack@eecs.umich.edu "in bytes") 1056735Sgblack@eecs.umich.edu coalescer_to_vrf_bus_width = Param.Int(32, "Coalescer->VRF data bus width "\ 1066019Shines@cs.fsu.edu "in bytes") 1076735Sgblack@eecs.umich.edu 1086735Sgblack@eecs.umich.edu memory_port = VectorMasterPort("Port to the memory system") 1098303SAli.Saidi@ARM.com translation_port = VectorMasterPort('Port to the TLB hierarchy') 1108303SAli.Saidi@ARM.com sqc_port = MasterPort("Port to the SQC (I-cache") 1118303SAli.Saidi@ARM.com sqc_tlb_port = MasterPort("Port to the TLB for the SQC (I-cache)") 1128303SAli.Saidi@ARM.com perLaneTLB = Param.Bool(False, "enable per-lane TLB") 1138303SAli.Saidi@ARM.com prefetch_depth = Param.Int(0, "Number of prefetches triggered at a time"\ 1148303SAli.Saidi@ARM.com "(0 turns off prefetching)") 1157720Sgblack@eecs.umich.edu prefetch_stride = Param.Int(1, "Fixed Prefetch Stride (1 means next-page)") 1168205SAli.Saidi@ARM.com prefetch_prev_type = Param.PrefetchType('PF_PHASE', "Prefetch the stride "\ 1178205SAli.Saidi@ARM.com "from last mem req in lane of "\ 1188205SAli.Saidi@ARM.com "CU|Phase|Wavefront") 1196735Sgblack@eecs.umich.edu execPolicy = Param.String("OLDEST-FIRST", "WF execution selection policy"); 1206735Sgblack@eecs.umich.edu xactCasMode = Param.Bool(False, "Behavior of xact_cas_load magic instr."); 1216735Sgblack@eecs.umich.edu debugSegFault = Param.Bool(False, "enable debugging GPU seg faults") 1226735Sgblack@eecs.umich.edu functionalTLB = Param.Bool(False, "Assume TLB causes no delay") 1236735Sgblack@eecs.umich.edu 1247093Sgblack@eecs.umich.edu localMemBarrier = Param.Bool(False, "Assume Barriers do not wait on "\ 1256735Sgblack@eecs.umich.edu "kernel end") 1266735Sgblack@eecs.umich.edu 1276735Sgblack@eecs.umich.edu countPages = Param.Bool(False, "Generate per-CU file of all pages touched "\ 1287302Sgblack@eecs.umich.edu "and how many times") 1296735Sgblack@eecs.umich.edu global_mem_queue_size = Param.Int(256, "Number of entries in the global " 1308518Sgeoffrey.blake@arm.com "memory pipeline's queues") 1318518Sgeoffrey.blake@arm.com local_mem_queue_size = Param.Int(256, "Number of entries in the local " 1327720Sgblack@eecs.umich.edu "memory pipeline's queues") 1336735Sgblack@eecs.umich.edu ldsBus = Bridge() # the bridge between the CU and its LDS 1346735Sgblack@eecs.umich.edu ldsPort = MasterPort("The port that goes to the LDS") 1356735Sgblack@eecs.umich.edu localDataStore = Param.LdsState("the LDS for this CU") 1366735Sgblack@eecs.umich.edu 1376735Sgblack@eecs.umich.edu vector_register_file = VectorParam.VectorRegisterFile("Vector register "\ 1386735Sgblack@eecs.umich.edu "file") 1396735Sgblack@eecs.umich.edu out_of_order_data_delivery = Param.Bool(False, "enable OoO data delivery" 1406735Sgblack@eecs.umich.edu " in the GM pipeline") 1416735Sgblack@eecs.umich.edu 1426735Sgblack@eecs.umich.educlass Shader(ClockedObject): 1436735Sgblack@eecs.umich.edu type = 'Shader' 1446735Sgblack@eecs.umich.edu cxx_class = 'Shader' 1456735Sgblack@eecs.umich.edu cxx_header = 'gpu-compute/shader.hh' 1466735Sgblack@eecs.umich.edu 1476735Sgblack@eecs.umich.edu CUs = VectorParam.ComputeUnit('Number of compute units') 1486735Sgblack@eecs.umich.edu n_wf = Param.Int(1, 'Number of wavefront slots per SIMD') 1496735Sgblack@eecs.umich.edu impl_kern_boundary_sync = Param.Bool(True, """Insert acq/rel packets into 1506735Sgblack@eecs.umich.edu ruby at kernel boundaries""") 1516735Sgblack@eecs.umich.edu separate_acquire_release = Param.Bool(False, 1526735Sgblack@eecs.umich.edu """Do ld_acquire/st_release generate separate requests for the 1537093Sgblack@eecs.umich.edu acquire and release?""") 1547093Sgblack@eecs.umich.edu globalmem = Param.MemorySize('64kB', 'Memory size') 1557720Sgblack@eecs.umich.edu timing = Param.Bool(False, 'timing memory accesses') 1567585SAli.Saidi@arm.com 1577720Sgblack@eecs.umich.edu cpu_pointer = Param.BaseCPU(NULL, "pointer to base CPU") 1587720Sgblack@eecs.umich.edu translation = Param.Bool(False, "address translation"); 1597720Sgblack@eecs.umich.edu 1607720Sgblack@eecs.umich.educlass ClDriver(EmulatedDriver): 1617720Sgblack@eecs.umich.edu type = 'ClDriver' 1627720Sgblack@eecs.umich.edu cxx_header = 'gpu-compute/cl_driver.hh' 1637720Sgblack@eecs.umich.edu codefile = VectorParam.String('code file name(s)') 1646019Shines@cs.fsu.edu 1657189Sgblack@eecs.umich.educlass GpuDispatcher(DmaDevice): 1667400SAli.Saidi@ARM.com type = 'GpuDispatcher' 1677678Sgblack@eecs.umich.edu cxx_header = 'gpu-compute/dispatcher.hh' 1687400SAli.Saidi@ARM.com # put at 8GB line for now 1698782Sgblack@eecs.umich.edu pio_addr = Param.Addr(0x200000000, "Device Address") 1708782Sgblack@eecs.umich.edu pio_latency = Param.Latency('1ns', "Programmed IO latency") 1718782Sgblack@eecs.umich.edu shader_pointer = Param.Shader('pointer to shader') 1728782Sgblack@eecs.umich.edu translation_port = MasterPort('Port to the dispatcher TLB') 1738205SAli.Saidi@ARM.com cpu = Param.BaseCPU("CPU to wake up on kernel completion") 1747400SAli.Saidi@ARM.com 1757400SAli.Saidi@ARM.com cl_driver = Param.ClDriver('pointer to driver') 1767189Sgblack@eecs.umich.edu 1777678Sgblack@eecs.umich.educlass MemType(Enum): vals = [ 1787189Sgblack@eecs.umich.edu 'M_U8', 1798782Sgblack@eecs.umich.edu 'M_U16', 1808782Sgblack@eecs.umich.edu 'M_U32', 1817189Sgblack@eecs.umich.edu 'M_U64', 1828782Sgblack@eecs.umich.edu 'M_S8', 1838782Sgblack@eecs.umich.edu 'M_S16', 1848782Sgblack@eecs.umich.edu 'M_S32', 1858782Sgblack@eecs.umich.edu 'M_S64', 1868782Sgblack@eecs.umich.edu 'M_F16', 1878782Sgblack@eecs.umich.edu 'M_F32', 1888782Sgblack@eecs.umich.edu 'M_F64', 1898782Sgblack@eecs.umich.edu ] 1908782Sgblack@eecs.umich.edu 1918782Sgblack@eecs.umich.educlass StorageClassType(Enum): vals = [ 1928782Sgblack@eecs.umich.edu 'SC_SPILL', 1938782Sgblack@eecs.umich.edu 'SC_GLOBAL', 1947189Sgblack@eecs.umich.edu 'SC_SHARED', 1957189Sgblack@eecs.umich.edu 'SC_PRIVATE', 1967189Sgblack@eecs.umich.edu 'SC_READONLY', 1977197Sgblack@eecs.umich.edu 'SC_KERNARG', 1987678Sgblack@eecs.umich.edu 'SC_NONE', 1997197Sgblack@eecs.umich.edu ] 2008782Sgblack@eecs.umich.edu 2018782Sgblack@eecs.umich.educlass RegisterType(Enum): vals = [ 2028782Sgblack@eecs.umich.edu 'RT_VECTOR', 2038782Sgblack@eecs.umich.edu 'RT_SCALAR', 2048782Sgblack@eecs.umich.edu 'RT_CONDITION', 2058782Sgblack@eecs.umich.edu 'RT_HARDWARE', 2068782Sgblack@eecs.umich.edu 'RT_NONE', 2078782Sgblack@eecs.umich.edu ] 2087197Sgblack@eecs.umich.edu