pc.cc revision 5829
12810SN/A/* 22810SN/A * Copyright (c) 2008 The Regents of The University of Michigan 32810SN/A * All rights reserved. 42810SN/A * 52810SN/A * Redistribution and use in source and binary forms, with or without 62810SN/A * modification, are permitted provided that the following conditions are 72810SN/A * met: redistributions of source code must retain the above copyright 82810SN/A * notice, this list of conditions and the following disclaimer; 92810SN/A * redistributions in binary form must reproduce the above copyright 102810SN/A * notice, this list of conditions and the following disclaimer in the 112810SN/A * documentation and/or other materials provided with the distribution; 122810SN/A * neither the name of the copyright holders nor the names of its 132810SN/A * contributors may be used to endorse or promote products derived from 142810SN/A * this software without specific prior written permission. 152810SN/A * 162810SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 172810SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 182810SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 192810SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 202810SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 212810SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 222810SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 232810SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 242810SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 252810SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 262810SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 272810SN/A * 282810SN/A * Authors: Gabe Black 292810SN/A */ 302810SN/A 312810SN/A/** @file 322810SN/A * Implementation of PC platform. 332810SN/A */ 342810SN/A 354626SN/A#include <deque> 364626SN/A#include <string> 372810SN/A#include <vector> 382810SN/A 394626SN/A#include "arch/x86/intmessage.hh" 404626SN/A#include "arch/x86/x86_traits.hh" 415338Sstever@gmail.com#include "cpu/intr_control.hh" 422810SN/A#include "dev/terminal.hh" 432810SN/A#include "dev/x86/i82094aa.hh" 443374SN/A#include "dev/x86/i8254.hh" 452810SN/A#include "dev/x86/pc.hh" 464626SN/A#include "dev/x86/south_bridge.hh" 474626SN/A#include "sim/system.hh" 482810SN/A 495314SN/Ausing namespace std; 505314SN/Ausing namespace TheISA; 515314SN/A 522810SN/APc::Pc(const Params *p) 534626SN/A : Platform(p), system(p->system) 544626SN/A{ 552810SN/A southBridge = NULL; 564626SN/A // set the back pointer from the system to myself 574666SN/A system->platform = this; 584626SN/A} 592810SN/A 602810SN/Avoid 612810SN/APc::init() 622810SN/A{ 634626SN/A assert(southBridge); 644626SN/A 654626SN/A /* 662810SN/A * Initialize the timer. 674626SN/A */ 682810SN/A I8254 & timer = *southBridge->pit; 692810SN/A //Timer 0, mode 2, no bcd, 16 bit count 704626SN/A timer.writeControl(0x34); 714626SN/A //Timer 0, latch command 722810SN/A timer.writeControl(0x00); 732810SN/A //Write a 16 bit count of 0 742810SN/A timer.writeCounter(0, 0); 754666SN/A timer.writeCounter(0, 0); 764666SN/A 774666SN/A /* 782810SN/A * Initialize the I/O APIC. 794626SN/A */ 802810SN/A I82094AA & ioApic = *southBridge->ioApic; 814626SN/A I82094AA::RedirTableEntry entry = 0; 824626SN/A entry.deliveryMode = DeliveryMode::ExtInt; 834628SN/A entry.vector = 0x20; 844628SN/A ioApic.writeReg(0x10, entry.bottomDW); 854628SN/A ioApic.writeReg(0x11, entry.topDW); 862810SN/A entry.deliveryMode = DeliveryMode::Fixed; 872810SN/A entry.vector = 0x24; 884626SN/A ioApic.writeReg(0x18, entry.bottomDW); 894626SN/A ioApic.writeReg(0x19, entry.topDW); 904626SN/A entry.mask = 1; 914626SN/A entry.vector = 0x21; 922810SN/A ioApic.writeReg(0x12, entry.bottomDW); 935314SN/A ioApic.writeReg(0x13, entry.topDW); 945314SN/A entry.vector = 0x20; 952810SN/A ioApic.writeReg(0x14, entry.bottomDW); 962810SN/A ioApic.writeReg(0x15, entry.topDW); 972810SN/A entry.vector = 0x28; 982810SN/A ioApic.writeReg(0x20, entry.bottomDW); 992810SN/A ioApic.writeReg(0x21, entry.topDW); 1004626SN/A entry.vector = 0x2C; 1012810SN/A ioApic.writeReg(0x28, entry.bottomDW); 1022810SN/A ioApic.writeReg(0x29, entry.topDW); 1032810SN/A} 1044626SN/A 1052810SN/ATick 1062810SN/APc::intrFrequency() 1074626SN/A{ 1082810SN/A panic("Need implementation\n"); 1094626SN/A M5_DUMMY_RETURN 1102810SN/A} 1112810SN/A 1122810SN/Avoid 1132991SN/APc::postConsoleInt() 1142810SN/A{ 1152810SN/A warn_once("Don't know what interrupt to post for console.\n"); 1163374SN/A //panic("Need implementation\n"); 1172982SN/A} 1182810SN/A 1192810SN/Avoid 1204626SN/APc::clearConsoleInt() 1212810SN/A{ 1224920SN/A warn_once("Don't know what interrupt to clear for console.\n"); 1234920SN/A //panic("Need implementation\n"); 1242810SN/A} 1253374SN/A 1262810SN/Avoid 1272982SN/APc::postPciInt(int line) 1282810SN/A{ 1292810SN/A panic("Need implementation\n"); 1302810SN/A} 1314626SN/A 1322810SN/Avoid 1334666SN/APc::clearPciInt(int line) 1344666SN/A{ 1352810SN/A panic("Need implementation\n"); 1362810SN/A} 1372810SN/A 1382810SN/AAddr 1392810SN/APc::pciToDma(Addr pciAddr) const 1402810SN/A{ 1414626SN/A panic("Need implementation\n"); 1422810SN/A M5_DUMMY_RETURN 1432810SN/A} 1444626SN/A 1454626SN/A 1462810SN/AAddr 1472810SN/APc::calcConfigAddr(int bus, int dev, int func) 1482810SN/A{ 1494626SN/A assert(func < 8); 1502810SN/A assert(dev < 32); 1512810SN/A assert(bus == 0); 1524626SN/A return (PhysAddrPrefixPciConfig | (func << 8) | (dev << 11)); 1534626SN/A} 1544626SN/A 1552810SN/APc * 1562810SN/APcParams::create() 1572810SN/A{ 1582810SN/A return new Pc(this); 1592810SN/A} 1604666SN/A