pc.cc revision 11793
16129Snate@binkert.org/* 26129Snate@binkert.org * Copyright (c) 2008 The Regents of The University of Michigan 36129Snate@binkert.org * All rights reserved. 46129Snate@binkert.org * 56129Snate@binkert.org * Redistribution and use in source and binary forms, with or without 66129Snate@binkert.org * modification, are permitted provided that the following conditions are 76129Snate@binkert.org * met: redistributions of source code must retain the above copyright 86129Snate@binkert.org * notice, this list of conditions and the following disclaimer; 96129Snate@binkert.org * redistributions in binary form must reproduce the above copyright 106129Snate@binkert.org * notice, this list of conditions and the following disclaimer in the 116129Snate@binkert.org * documentation and/or other materials provided with the distribution; 126129Snate@binkert.org * neither the name of the copyright holders nor the names of its 136129Snate@binkert.org * contributors may be used to endorse or promote products derived from 146129Snate@binkert.org * this software without specific prior written permission. 156129Snate@binkert.org * 166129Snate@binkert.org * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 176129Snate@binkert.org * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 186129Snate@binkert.org * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 196129Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 206129Snate@binkert.org * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 216129Snate@binkert.org * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 226129Snate@binkert.org * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 236129Snate@binkert.org * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 246129Snate@binkert.org * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 256129Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 266129Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 276129Snate@binkert.org * 286129Snate@binkert.org * Authors: Gabe Black 296129Snate@binkert.org */ 306129Snate@binkert.org 316169Snate@binkert.org/** @file 326169Snate@binkert.org * Implementation of PC platform. 336169Snate@binkert.org */ 348229Snate@binkert.org 356130Snate@binkert.org#include "dev/x86/pc.hh" 366129Snate@binkert.org 376129Snate@binkert.org#include <deque> 386129Snate@binkert.org#include <string> 396130Snate@binkert.org#include <vector> 406130Snate@binkert.org 416130Snate@binkert.org#include "arch/x86/intmessage.hh" 426130Snate@binkert.org#include "arch/x86/x86_traits.hh" 436130Snate@binkert.org#include "config/the_isa.hh" 446130Snate@binkert.org#include "cpu/intr_control.hh" 456130Snate@binkert.org#include "dev/terminal.hh" 466130Snate@binkert.org#include "dev/x86/i82094aa.hh" 477462Snate@binkert.org#include "dev/x86/i8254.hh" 486130Snate@binkert.org#include "dev/x86/i8259.hh" 496130Snate@binkert.org#include "dev/x86/south_bridge.hh" 506130Snate@binkert.org#include "sim/system.hh" 516130Snate@binkert.org 526130Snate@binkert.orgusing namespace std; 536130Snate@binkert.orgusing namespace TheISA; 546130Snate@binkert.org 556130Snate@binkert.orgPc::Pc(const Params *p) 566130Snate@binkert.org : Platform(p), system(p->system) 576130Snate@binkert.org{ 586130Snate@binkert.org southBridge = NULL; 596130Snate@binkert.org} 609743Snilay@cs.wisc.edu 619743Snilay@cs.wisc.eduvoid 626130Snate@binkert.orgPc::init() 636130Snate@binkert.org{ 647462Snate@binkert.org assert(southBridge); 656130Snate@binkert.org 667505Snate@binkert.org /* 678296Snate@binkert.org * Initialize the timer. 686129Snate@binkert.org */ 696129Snate@binkert.org I8254 & timer = *southBridge->pit; 706129Snate@binkert.org //Timer 0, mode 2, no bcd, 16 bit count 716129Snate@binkert.org timer.writeControl(0x34); 726129Snate@binkert.org //Timer 0, latch command 736129Snate@binkert.org timer.writeControl(0x00); 748243Sbradley.danofsky@amd.com //Write a 16 bit count of 0 758243Sbradley.danofsky@amd.com timer.writeCounter(0, 0); 766129Snate@binkert.org timer.writeCounter(0, 0); 776129Snate@binkert.org 786129Snate@binkert.org /* 796130Snate@binkert.org * Initialize the I/O APIC. 806129Snate@binkert.org */ 816129Snate@binkert.org I82094AA & ioApic = *southBridge->ioApic; 826129Snate@binkert.org I82094AA::RedirTableEntry entry = 0; 836129Snate@binkert.org entry.deliveryMode = DeliveryMode::ExtInt; 846129Snate@binkert.org entry.vector = 0x20; 856129Snate@binkert.org ioApic.writeReg(0x10, entry.bottomDW); 866129Snate@binkert.org ioApic.writeReg(0x11, entry.topDW); 876129Snate@binkert.org entry.deliveryMode = DeliveryMode::Fixed; 886129Snate@binkert.org entry.vector = 0x24; 896129Snate@binkert.org ioApic.writeReg(0x18, entry.bottomDW); 906129Snate@binkert.org ioApic.writeReg(0x19, entry.topDW); 916129Snate@binkert.org entry.mask = 1; 926129Snate@binkert.org entry.vector = 0x21; 936129Snate@binkert.org ioApic.writeReg(0x12, entry.bottomDW); 946129Snate@binkert.org ioApic.writeReg(0x13, entry.topDW); 956129Snate@binkert.org entry.vector = 0x20; 966129Snate@binkert.org ioApic.writeReg(0x14, entry.bottomDW); 976129Snate@binkert.org ioApic.writeReg(0x15, entry.topDW); 986129Snate@binkert.org entry.vector = 0x28; 996129Snate@binkert.org ioApic.writeReg(0x20, entry.bottomDW); 1008243Sbradley.danofsky@amd.com ioApic.writeReg(0x21, entry.topDW); 1016129Snate@binkert.org entry.vector = 0x2C; 1026129Snate@binkert.org ioApic.writeReg(0x28, entry.bottomDW); 1036129Snate@binkert.org ioApic.writeReg(0x29, entry.topDW); 1046129Snate@binkert.org entry.vector = 0x2E; 1056129Snate@binkert.org ioApic.writeReg(0x2C, entry.bottomDW); 1066129Snate@binkert.org ioApic.writeReg(0x2D, entry.topDW); 1076129Snate@binkert.org entry.vector = 0x30; 1086129Snate@binkert.org ioApic.writeReg(0x30, entry.bottomDW); 1096129Snate@binkert.org ioApic.writeReg(0x31, entry.topDW); 1106129Snate@binkert.org 1116129Snate@binkert.org /* 1126129Snate@binkert.org * Mask the PICs. I'm presuming the BIOS/bootloader would have cleared 1136129Snate@binkert.org * these out and masked them before passing control to the OS. 1146129Snate@binkert.org */ 1156129Snate@binkert.org southBridge->pic1->maskAll(); 1166129Snate@binkert.org southBridge->pic2->maskAll(); 1176129Snate@binkert.org} 1186129Snate@binkert.org 1196129Snate@binkert.orgvoid 1206129Snate@binkert.orgPc::postConsoleInt() 1216129Snate@binkert.org{ 1226129Snate@binkert.org southBridge->ioApic->signalInterrupt(4); 1236129Snate@binkert.org southBridge->pic1->signalInterrupt(4); 1246129Snate@binkert.org} 1256129Snate@binkert.org 1266129Snate@binkert.orgvoid 1276129Snate@binkert.orgPc::clearConsoleInt() 1286129Snate@binkert.org{ 1296129Snate@binkert.org warn_once("Don't know what interrupt to clear for console.\n"); 1306129Snate@binkert.org //panic("Need implementation\n"); 1316129Snate@binkert.org} 1326129Snate@binkert.org 1336129Snate@binkert.orgvoid 1348296Snate@binkert.orgPc::postPciInt(int line) 1356129Snate@binkert.org{ 1366129Snate@binkert.org southBridge->ioApic->signalInterrupt(line); 1376129Snate@binkert.org} 1386129Snate@binkert.org 1396129Snate@binkert.orgvoid 1406129Snate@binkert.orgPc::clearPciInt(int line) 1416129Snate@binkert.org{ 1426129Snate@binkert.org warn_once("Tried to clear PCI interrupt %d\n", line); 1436129Snate@binkert.org} 1446129Snate@binkert.org 1456129Snate@binkert.orgPc * 1466129Snate@binkert.orgPcParams::create() 1476129Snate@binkert.org{ 1486129Snate@binkert.org return new Pc(this); 1496129Snate@binkert.org} 1506129Snate@binkert.org