intdev.hh revision 8839:eeb293859255 
1/*
2 * Copyright (c) 2008 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#ifndef __DEV_X86_INTDEV_HH__
32#define __DEV_X86_INTDEV_HH__
33
34#include <cassert>
35#include <list>
36#include <string>
37
38#include "arch/x86/intmessage.hh"
39#include "arch/x86/x86_traits.hh"
40#include "mem/mem_object.hh"
41#include "mem/mport.hh"
42#include "params/X86IntLine.hh"
43#include "params/X86IntSinkPin.hh"
44#include "params/X86IntSourcePin.hh"
45#include "sim/sim_object.hh"
46
47namespace X86ISA {
48
49typedef std::list<int> ApicList;
50
51class IntDev
52{
53  protected:
54    class IntPort : public MessagePort
55    {
56        IntDev * device;
57        Tick latency;
58        Addr intAddr;
59      public:
60        IntPort(const std::string &_name, MemObject * _parent,
61                IntDev *dev, Tick _latency) :
62            MessagePort(_name, _parent), device(dev), latency(_latency)
63        {
64        }
65
66        AddrRangeList getAddrRanges()
67        {
68            return device->getIntAddrRange();
69        }
70
71        Tick recvMessage(PacketPtr pkt)
72        {
73            return device->recvMessage(pkt);
74        }
75
76        Tick recvResponse(PacketPtr pkt)
77        {
78            return device->recvResponse(pkt);
79        }
80
81        // This is x86 focused, so if this class becomes generic, this would
82        // need to be moved into a subclass.
83        void sendMessage(ApicList apics,
84                TriggerIntMessage message, bool timing);
85    };
86
87    IntPort * intPort;
88
89  public:
90    IntDev(MemObject * parent, Tick latency = 0)
91    {
92        if (parent != NULL) {
93            intPort = new IntPort(parent->name() + ".int_master",
94                    parent, this, latency);
95        } else {
96            intPort = NULL;
97        }
98    }
99
100    virtual ~IntDev()
101    {}
102
103    virtual void init();
104
105    virtual void
106    signalInterrupt(int line)
107    {
108        panic("signalInterrupt not implemented.\n");
109    }
110
111    virtual void
112    raiseInterruptPin(int number)
113    {
114        panic("raiseInterruptPin not implemented.\n");
115    }
116
117    virtual void
118    lowerInterruptPin(int number)
119    {
120        panic("lowerInterruptPin not implemented.\n");
121    }
122
123    virtual Tick
124    recvMessage(PacketPtr pkt)
125    {
126        panic("recvMessage not implemented.\n");
127        return 0;
128    }
129
130    virtual Tick
131    recvResponse(PacketPtr pkt)
132    {
133        return 0;
134    }
135
136    virtual AddrRangeList
137    getIntAddrRange()
138    {
139        panic("intAddrRange not implemented.\n");
140    }
141};
142
143class IntSinkPin : public SimObject
144{
145  public:
146    IntDev * device;
147    int number;
148
149    typedef X86IntSinkPinParams Params;
150
151    const Params *
152    params() const
153    {
154        return dynamic_cast<const Params *>(_params);
155    }
156
157    IntSinkPin(Params *p) : SimObject(p),
158            device(dynamic_cast<IntDev *>(p->device)), number(p->number)
159    {
160        assert(device);
161    }
162};
163
164class IntSourcePin : public SimObject
165{
166  protected:
167    std::vector<IntSinkPin *> sinks;
168
169  public:
170    typedef X86IntSourcePinParams Params;
171
172    const Params *
173    params() const
174    {
175        return dynamic_cast<const Params *>(_params);
176    }
177
178    void
179    addSink(IntSinkPin *sink)
180    {
181        sinks.push_back(sink);
182    }
183
184    void
185    raise()
186    {
187        for (int i = 0; i < sinks.size(); i++) {
188            const IntSinkPin &pin = *sinks[i];
189            pin.device->raiseInterruptPin(pin.number);
190        }
191    }
192
193    void
194    lower()
195    {
196        for (int i = 0; i < sinks.size(); i++) {
197            const IntSinkPin &pin = *sinks[i];
198            pin.device->lowerInterruptPin(pin.number);
199        }
200    }
201
202    IntSourcePin(Params *p) : SimObject(p)
203    {}
204};
205
206class IntLine : public SimObject
207{
208  protected:
209    IntSourcePin *source;
210    IntSinkPin *sink;
211
212  public:
213    typedef X86IntLineParams Params;
214
215    const Params *
216    params() const
217    {
218        return dynamic_cast<const Params *>(_params);
219    }
220
221    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
222    {
223        source->addSink(sink);
224    }
225};
226
227} // namespace X86ISA
228
229#endif //__DEV_X86_INTDEV_HH__
230