intdev.hh revision 14291:722551795497 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __DEV_X86_INTDEV_HH__
44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mport.hh"
53#include "sim/sim_object.hh"
54
55namespace X86ISA {
56
57typedef std::list<int> ApicList;
58
59class IntDevice
60{
61  protected:
62    class IntSlavePort : public MessageSlavePort
63    {
64        IntDevice * device;
65
66      public:
67        IntSlavePort(const std::string& _name, SimObject* _parent,
68                     IntDevice* dev) :
69            MessageSlavePort(_name, _parent), device(dev)
70        {
71        }
72
73        AddrRangeList getAddrRanges() const
74        {
75            return device->getIntAddrRange();
76        }
77
78        Tick recvMessage(PacketPtr pkt)
79        {
80            // @todo someone should pay for this
81            pkt->headerDelay = pkt->payloadDelay = 0;
82            return device->recvMessage(pkt);
83        }
84    };
85
86    class IntMasterPort : public MessageMasterPort
87    {
88        IntDevice* device;
89        Tick latency;
90      public:
91        IntMasterPort(const std::string& _name, SimObject* _parent,
92                      IntDevice* dev, Tick _latency) :
93            MessageMasterPort(_name, _parent), device(dev), latency(_latency)
94        {
95        }
96
97        Tick recvResponse(PacketPtr pkt)
98        {
99            return device->recvResponse(pkt);
100        }
101
102        // This is x86 focused, so if this class becomes generic, this would
103        // need to be moved into a subclass.
104        void sendMessage(ApicList apics,
105                TriggerIntMessage message, bool timing);
106    };
107
108    IntMasterPort intMasterPort;
109
110  public:
111    IntDevice(SimObject * parent, Tick latency = 0) :
112        intMasterPort(parent->name() + ".int_master", parent, this, latency)
113    {
114    }
115
116    virtual ~IntDevice()
117    {}
118
119    virtual void init();
120
121    virtual Tick
122    recvMessage(PacketPtr pkt)
123    {
124        panic("recvMessage not implemented.\n");
125        return 0;
126    }
127
128    virtual Tick
129    recvResponse(PacketPtr pkt)
130    {
131        panic("recvResponse not implemented.\n");
132        return 0;
133    }
134
135    virtual AddrRangeList
136    getIntAddrRange() const
137    {
138        panic("intAddrRange not implemented.\n");
139    }
140};
141
142} // namespace X86ISA
143
144#endif //__DEV_X86_INTDEV_HH__
145