intdev.hh revision 11144:90eeefe7e341 
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2008 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Gabe Black
41 */
42
43#ifndef __DEV_X86_INTDEV_HH__
44#define __DEV_X86_INTDEV_HH__
45
46#include <cassert>
47#include <list>
48#include <string>
49
50#include "arch/x86/intmessage.hh"
51#include "arch/x86/x86_traits.hh"
52#include "mem/mem_object.hh"
53#include "mem/mport.hh"
54#include "params/X86IntLine.hh"
55#include "params/X86IntSinkPin.hh"
56#include "params/X86IntSourcePin.hh"
57#include "sim/sim_object.hh"
58
59namespace X86ISA {
60
61typedef std::list<int> ApicList;
62
63class IntDevice
64{
65  protected:
66    class IntSlavePort : public MessageSlavePort
67    {
68        IntDevice * device;
69
70      public:
71        IntSlavePort(const std::string& _name, MemObject* _parent,
72                     IntDevice* dev) :
73            MessageSlavePort(_name, _parent), device(dev)
74        {
75        }
76
77        AddrRangeList getAddrRanges() const
78        {
79            return device->getIntAddrRange();
80        }
81
82        Tick recvMessage(PacketPtr pkt)
83        {
84            // @todo someone should pay for this
85            pkt->headerDelay = pkt->payloadDelay = 0;
86            return device->recvMessage(pkt);
87        }
88    };
89
90    class IntMasterPort : public MessageMasterPort
91    {
92        IntDevice* device;
93        Tick latency;
94      public:
95        IntMasterPort(const std::string& _name, MemObject* _parent,
96                      IntDevice* dev, Tick _latency) :
97            MessageMasterPort(_name, _parent), device(dev), latency(_latency)
98        {
99        }
100
101        Tick recvResponse(PacketPtr pkt)
102        {
103            return device->recvResponse(pkt);
104        }
105
106        // This is x86 focused, so if this class becomes generic, this would
107        // need to be moved into a subclass.
108        void sendMessage(ApicList apics,
109                TriggerIntMessage message, bool timing);
110    };
111
112    IntMasterPort intMasterPort;
113
114  public:
115    IntDevice(MemObject * parent, Tick latency = 0) :
116        intMasterPort(parent->name() + ".int_master", parent, this, latency)
117    {
118    }
119
120    virtual ~IntDevice()
121    {}
122
123    virtual void init();
124
125    virtual void
126    signalInterrupt(int line)
127    {
128        panic("signalInterrupt not implemented.\n");
129    }
130
131    virtual void
132    raiseInterruptPin(int number)
133    {
134        panic("raiseInterruptPin not implemented.\n");
135    }
136
137    virtual void
138    lowerInterruptPin(int number)
139    {
140        panic("lowerInterruptPin not implemented.\n");
141    }
142
143    virtual Tick
144    recvMessage(PacketPtr pkt)
145    {
146        panic("recvMessage not implemented.\n");
147        return 0;
148    }
149
150    virtual Tick
151    recvResponse(PacketPtr pkt)
152    {
153        panic("recvResponse not implemented.\n");
154        return 0;
155    }
156
157    virtual AddrRangeList
158    getIntAddrRange() const
159    {
160        panic("intAddrRange not implemented.\n");
161    }
162};
163
164class IntSinkPin : public SimObject
165{
166  public:
167    IntDevice * device;
168    int number;
169
170    typedef X86IntSinkPinParams Params;
171
172    const Params *
173    params() const
174    {
175        return dynamic_cast<const Params *>(_params);
176    }
177
178    IntSinkPin(Params *p) : SimObject(p),
179            device(dynamic_cast<IntDevice *>(p->device)), number(p->number)
180    {
181        assert(device);
182    }
183};
184
185class IntSourcePin : public SimObject
186{
187  protected:
188    std::vector<IntSinkPin *> sinks;
189
190  public:
191    typedef X86IntSourcePinParams Params;
192
193    const Params *
194    params() const
195    {
196        return dynamic_cast<const Params *>(_params);
197    }
198
199    void
200    addSink(IntSinkPin *sink)
201    {
202        sinks.push_back(sink);
203    }
204
205    void
206    raise()
207    {
208        for (int i = 0; i < sinks.size(); i++) {
209            const IntSinkPin &pin = *sinks[i];
210            pin.device->raiseInterruptPin(pin.number);
211        }
212    }
213
214    void
215    lower()
216    {
217        for (int i = 0; i < sinks.size(); i++) {
218            const IntSinkPin &pin = *sinks[i];
219            pin.device->lowerInterruptPin(pin.number);
220        }
221    }
222
223    IntSourcePin(Params *p) : SimObject(p)
224    {}
225};
226
227class IntLine : public SimObject
228{
229  protected:
230    IntSourcePin *source;
231    IntSinkPin *sink;
232
233  public:
234    typedef X86IntLineParams Params;
235
236    const Params *
237    params() const
238    {
239        return dynamic_cast<const Params *>(_params);
240    }
241
242    IntLine(Params *p) : SimObject(p), source(p->source), sink(p->sink)
243    {
244        source->addSink(sink);
245    }
246};
247
248} // namespace X86ISA
249
250#endif //__DEV_X86_INTDEV_HH__
251