i8259.hh revision 5632
15390SN/A/*
25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan
35390SN/A * All rights reserved.
45390SN/A *
55390SN/A * Redistribution and use in source and binary forms, with or without
65390SN/A * modification, are permitted provided that the following conditions are
75390SN/A * met: redistributions of source code must retain the above copyright
85390SN/A * notice, this list of conditions and the following disclaimer;
95390SN/A * redistributions in binary form must reproduce the above copyright
105390SN/A * notice, this list of conditions and the following disclaimer in the
115390SN/A * documentation and/or other materials provided with the distribution;
125390SN/A * neither the name of the copyright holders nor the names of its
135390SN/A * contributors may be used to endorse or promote products derived from
145390SN/A * this software without specific prior written permission.
155390SN/A *
165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
275390SN/A *
285390SN/A * Authors: Gabe Black
295390SN/A */
305390SN/A
315630Sgblack@eecs.umich.edu#ifndef __DEV_X86_I8259_HH__
325630Sgblack@eecs.umich.edu#define __DEV_X86_I8259_HH__
335390SN/A
345630Sgblack@eecs.umich.edu#include "dev/io_device.hh"
355630Sgblack@eecs.umich.edu#include "params/I8259.hh"
365390SN/A
375390SN/Anamespace X86ISA
385390SN/A{
395390SN/A
405630Sgblack@eecs.umich.educlass I8259 : public BasicPioDevice
415390SN/A{
425630Sgblack@eecs.umich.edu  protected:
435630Sgblack@eecs.umich.edu    Tick latency;
445632Sgblack@eecs.umich.edu    I8259 *master;
455630Sgblack@eecs.umich.edu
465631Sgblack@eecs.umich.edu    // Interrupt Request Register
475631Sgblack@eecs.umich.edu    uint8_t IRR;
485631Sgblack@eecs.umich.edu    // In Service Register
495631Sgblack@eecs.umich.edu    uint8_t ISR;
505631Sgblack@eecs.umich.edu    // Interrupt Mask Register
515631Sgblack@eecs.umich.edu    uint8_t IMR;
525631Sgblack@eecs.umich.edu
535632Sgblack@eecs.umich.edu    bool cascadeMode;
545632Sgblack@eecs.umich.edu    // A bit vector of lines with slaves attached, or the slave id, depending
555632Sgblack@eecs.umich.edu    // on if this is a master or slave PIC.
565632Sgblack@eecs.umich.edu    uint8_t cascadeBits;
575632Sgblack@eecs.umich.edu
585631Sgblack@eecs.umich.edu    bool edgeTriggered;
595632Sgblack@eecs.umich.edu    bool readIRR;
605632Sgblack@eecs.umich.edu
615632Sgblack@eecs.umich.edu    // State machine information for reading in initialization control words.
625631Sgblack@eecs.umich.edu    bool expectICW4;
635631Sgblack@eecs.umich.edu    int initControlWord;
645631Sgblack@eecs.umich.edu
655390SN/A  public:
665630Sgblack@eecs.umich.edu    typedef I8259Params Params;
675390SN/A
685630Sgblack@eecs.umich.edu    const Params *
695630Sgblack@eecs.umich.edu    params() const
705630Sgblack@eecs.umich.edu    {
715630Sgblack@eecs.umich.edu        return dynamic_cast<const Params *>(_params);
725630Sgblack@eecs.umich.edu    }
735630Sgblack@eecs.umich.edu
745630Sgblack@eecs.umich.edu    I8259(Params * p) : BasicPioDevice(p)
755630Sgblack@eecs.umich.edu    {
765630Sgblack@eecs.umich.edu        pioSize = 2;
775631Sgblack@eecs.umich.edu        initControlWord = 0;
785631Sgblack@eecs.umich.edu        readIRR = true;
795630Sgblack@eecs.umich.edu        latency = p->pio_latency;
805630Sgblack@eecs.umich.edu        master = p->master;
815630Sgblack@eecs.umich.edu    }
825390SN/A
835390SN/A    Tick read(PacketPtr pkt);
845390SN/A
855390SN/A    Tick write(PacketPtr pkt);
865632Sgblack@eecs.umich.edu
875632Sgblack@eecs.umich.edu    void signalInterrupt(int line);
885390SN/A};
895390SN/A
905390SN/A}; // namespace X86ISA
915390SN/A
925630Sgblack@eecs.umich.edu#endif //__DEV_X86_I8259_HH__
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