i8259.hh revision 14291
110461SAndreas.Sandberg@ARM.com/* 210461SAndreas.Sandberg@ARM.com * Copyright (c) 2004-2005 The Regents of The University of Michigan 310461SAndreas.Sandberg@ARM.com * All rights reserved. 410461SAndreas.Sandberg@ARM.com * 510461SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 610461SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 710461SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 810461SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 910461SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 1010461SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 1110461SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 1210461SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 1310461SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 1410461SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 1510461SAndreas.Sandberg@ARM.com * 1610461SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1710461SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1810461SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1910461SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2010461SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2110461SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2210461SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2310461SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2410461SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2510461SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2610461SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2710461SAndreas.Sandberg@ARM.com * 2810461SAndreas.Sandberg@ARM.com * Authors: Gabe Black 2910461SAndreas.Sandberg@ARM.com */ 3010461SAndreas.Sandberg@ARM.com 3110461SAndreas.Sandberg@ARM.com#ifndef __DEV_X86_I8259_HH__ 3210461SAndreas.Sandberg@ARM.com#define __DEV_X86_I8259_HH__ 3310461SAndreas.Sandberg@ARM.com 3410461SAndreas.Sandberg@ARM.com#include "dev/intpin.hh" 3510461SAndreas.Sandberg@ARM.com#include "dev/io_device.hh" 3610461SAndreas.Sandberg@ARM.com#include "enums/X86I8259CascadeMode.hh" 3710461SAndreas.Sandberg@ARM.com#include "params/I8259.hh" 3810461SAndreas.Sandberg@ARM.com 3910461SAndreas.Sandberg@ARM.comnamespace X86ISA 4010461SAndreas.Sandberg@ARM.com{ 4110461SAndreas.Sandberg@ARM.com 4210461SAndreas.Sandberg@ARM.comclass I8259 : public BasicPioDevice 4310461SAndreas.Sandberg@ARM.com{ 4410461SAndreas.Sandberg@ARM.com protected: 4510461SAndreas.Sandberg@ARM.com static const int NumLines = 8; 4610461SAndreas.Sandberg@ARM.com bool pinStates[NumLines]; 4710461SAndreas.Sandberg@ARM.com 4810461SAndreas.Sandberg@ARM.com void init() override; 4910461SAndreas.Sandberg@ARM.com 5010461SAndreas.Sandberg@ARM.com Tick latency; 5110461SAndreas.Sandberg@ARM.com std::vector<IntSourcePin<I8259> *> output; 5210461SAndreas.Sandberg@ARM.com std::vector<IntSinkPin<I8259> *> inputs; 5310461SAndreas.Sandberg@ARM.com Enums::X86I8259CascadeMode mode; 5410461SAndreas.Sandberg@ARM.com I8259 * slave; 5510461SAndreas.Sandberg@ARM.com 5610461SAndreas.Sandberg@ARM.com // Interrupt Request Register 5710461SAndreas.Sandberg@ARM.com uint8_t IRR; 5810461SAndreas.Sandberg@ARM.com // In Service Register 5910461SAndreas.Sandberg@ARM.com uint8_t ISR; 6010461SAndreas.Sandberg@ARM.com // Interrupt Mask Register 6110461SAndreas.Sandberg@ARM.com uint8_t IMR; 6210461SAndreas.Sandberg@ARM.com 6310461SAndreas.Sandberg@ARM.com // The higher order bits of the vector to return 6410461SAndreas.Sandberg@ARM.com uint8_t vectorOffset; 6510461SAndreas.Sandberg@ARM.com 6610461SAndreas.Sandberg@ARM.com bool cascadeMode; 6710461SAndreas.Sandberg@ARM.com // A bit vector of lines with slaves attached, or the slave id, depending 6810461SAndreas.Sandberg@ARM.com // on if this is a master or slave PIC. 6910461SAndreas.Sandberg@ARM.com uint8_t cascadeBits; 7010461SAndreas.Sandberg@ARM.com 7110461SAndreas.Sandberg@ARM.com bool edgeTriggered; 7210461SAndreas.Sandberg@ARM.com bool readIRR; 7310461SAndreas.Sandberg@ARM.com 7410461SAndreas.Sandberg@ARM.com // State machine information for reading in initialization control words. 7510461SAndreas.Sandberg@ARM.com bool expectICW4; 7610461SAndreas.Sandberg@ARM.com int initControlWord; 7710461SAndreas.Sandberg@ARM.com 7810461SAndreas.Sandberg@ARM.com // Whether or not the PIC is in auto EOI mode. 7910461SAndreas.Sandberg@ARM.com bool autoEOI; 8010461SAndreas.Sandberg@ARM.com 8110461SAndreas.Sandberg@ARM.com void requestInterrupt(int line); 8210461SAndreas.Sandberg@ARM.com void handleEOI(int line); 8310461SAndreas.Sandberg@ARM.com 8410461SAndreas.Sandberg@ARM.com public: 8510461SAndreas.Sandberg@ARM.com typedef I8259Params Params; 8610461SAndreas.Sandberg@ARM.com 8710461SAndreas.Sandberg@ARM.com const Params * 8810461SAndreas.Sandberg@ARM.com params() const 8910461SAndreas.Sandberg@ARM.com { 9010461SAndreas.Sandberg@ARM.com return dynamic_cast<const Params *>(_params); 9110461SAndreas.Sandberg@ARM.com } 9210461SAndreas.Sandberg@ARM.com 9310461SAndreas.Sandberg@ARM.com I8259(Params * p); 9410461SAndreas.Sandberg@ARM.com 9510461SAndreas.Sandberg@ARM.com Port & 9610461SAndreas.Sandberg@ARM.com getPort(const std::string &if_name, PortID idx=InvalidPortID) override 9710461SAndreas.Sandberg@ARM.com { 9810461SAndreas.Sandberg@ARM.com if (if_name == "inputs") 9910461SAndreas.Sandberg@ARM.com return *inputs.at(idx); 100 else if (if_name == "output") 101 return *output.at(idx); 102 else 103 return BasicPioDevice::getPort(if_name, idx); 104 } 105 106 Tick read(PacketPtr pkt) override; 107 Tick write(PacketPtr pkt) override; 108 109 void 110 maskAll() 111 { 112 IMR = 0xFF; 113 } 114 115 void 116 unmaskAll() 117 { 118 IMR = 0x00; 119 } 120 121 void signalInterrupt(int line); 122 void raiseInterruptPin(int number); 123 void lowerInterruptPin(int number); 124 int getVector(); 125 126 void serialize(CheckpointOut &cp) const override; 127 void unserialize(CheckpointIn &cp) override; 128}; 129 130} // namespace X86ISA 131 132#endif //__DEV_X86_I8259_HH__ 133