i8259.cc revision 9808:13ffc0066b76
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "base/bitfield.hh" 32#include "debug/I8259.hh" 33#include "dev/x86/i82094aa.hh" 34#include "dev/x86/i8259.hh" 35#include "mem/packet.hh" 36#include "mem/packet_access.hh" 37 38X86ISA::I8259::I8259(Params * p) 39 : BasicPioDevice(p, 2), IntDevice(this), 40 latency(p->pio_latency), output(p->output), 41 mode(p->mode), slave(p->slave), 42 IRR(0), ISR(0), IMR(0), 43 readIRR(true), initControlWord(0), autoEOI(false) 44{ 45 for (int i = 0; i < NumLines; i++) 46 pinStates[i] = false; 47} 48 49Tick 50X86ISA::I8259::read(PacketPtr pkt) 51{ 52 assert(pkt->getSize() == 1); 53 switch(pkt->getAddr() - pioAddr) 54 { 55 case 0x0: 56 if (readIRR) { 57 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 58 pkt->set(IRR); 59 } else { 60 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 61 pkt->set(ISR); 62 } 63 break; 64 case 0x1: 65 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 66 pkt->set(IMR); 67 break; 68 } 69 pkt->makeAtomicResponse(); 70 return latency; 71} 72 73Tick 74X86ISA::I8259::write(PacketPtr pkt) 75{ 76 assert(pkt->getSize() == 1); 77 uint8_t val = pkt->get<uint8_t>(); 78 switch (pkt->getAddr() - pioAddr) { 79 case 0x0: 80 if (bits(val, 4)) { 81 DPRINTF(I8259, "Received initialization command word 1.\n"); 82 IMR = 0; 83 edgeTriggered = bits(val, 3); 84 DPRINTF(I8259, "%s triggered mode.\n", 85 edgeTriggered ? "Edge" : "Level"); 86 cascadeMode = !bits(val, 1); 87 DPRINTF(I8259, "%s mode.\n", 88 cascadeMode ? "Cascade" : "Single"); 89 expectICW4 = bits(val, 0); 90 if (!expectICW4) { 91 autoEOI = false; 92 } 93 initControlWord = 1; 94 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 95 } else if (bits(val, 4, 3) == 0) { 96 DPRINTF(I8259, "Received operation command word 2.\n"); 97 switch (bits(val, 7, 5)) { 98 case 0x0: 99 DPRINTF(I8259, 100 "Subcommand: Rotate in auto-EOI mode (clear).\n"); 101 break; 102 case 0x1: 103 { 104 int line = findMsbSet(ISR); 105 DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 106 line); 107 handleEOI(line); 108 } 109 break; 110 case 0x2: 111 DPRINTF(I8259, "Subcommand: No operation.\n"); 112 break; 113 case 0x3: 114 { 115 int line = bits(val, 2, 0); 116 DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 117 line); 118 handleEOI(line); 119 } 120 break; 121 case 0x4: 122 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 123 break; 124 case 0x5: 125 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 126 break; 127 case 0x6: 128 DPRINTF(I8259, "Subcommand: Set priority command.\n"); 129 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 130 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 131 break; 132 case 0x7: 133 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 134 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 135 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 136 break; 137 } 138 } else if (bits(val, 4, 3) == 1) { 139 DPRINTF(I8259, "Received operation command word 3.\n"); 140 if (bits(val, 7)) { 141 DPRINTF(I8259, "%s special mask mode.\n", 142 bits(val, 6) ? "Set" : "Clear"); 143 } 144 if (bits(val, 1)) { 145 readIRR = bits(val, 0); 146 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 147 } 148 } 149 break; 150 case 0x1: 151 switch (initControlWord) { 152 case 0x0: 153 DPRINTF(I8259, "Received operation command word 1.\n"); 154 DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 155 IMR = val; 156 break; 157 case 0x1: 158 DPRINTF(I8259, "Received initialization command word 2.\n"); 159 vectorOffset = val & ~mask(3); 160 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 161 vectorOffset, vectorOffset | mask(3)); 162 if (cascadeMode) { 163 initControlWord++; 164 } else { 165 cascadeBits = 0; 166 initControlWord = 0; 167 } 168 break; 169 case 0x2: 170 DPRINTF(I8259, "Received initialization command word 3.\n"); 171 if (mode == Enums::I8259Master) { 172 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 173 bits(val, 0) ? " 0" : "", 174 bits(val, 1) ? " 1" : "", 175 bits(val, 2) ? " 2" : "", 176 bits(val, 3) ? " 3" : "", 177 bits(val, 4) ? " 4" : "", 178 bits(val, 5) ? " 5" : "", 179 bits(val, 6) ? " 6" : "", 180 bits(val, 7) ? " 7" : ""); 181 cascadeBits = val; 182 } else { 183 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 184 cascadeBits = val & mask(3); 185 } 186 if (expectICW4) 187 initControlWord++; 188 else 189 initControlWord = 0; 190 break; 191 case 0x3: 192 DPRINTF(I8259, "Received initialization command word 4.\n"); 193 if (bits(val, 4)) { 194 DPRINTF(I8259, "Special fully nested mode.\n"); 195 } else { 196 DPRINTF(I8259, "Not special fully nested mode.\n"); 197 } 198 if (bits(val, 3) == 0) { 199 DPRINTF(I8259, "Nonbuffered.\n"); 200 } else if (bits(val, 2) == 0) { 201 DPRINTF(I8259, "Buffered.\n"); 202 } else { 203 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 204 } 205 autoEOI = bits(val, 1); 206 DPRINTF(I8259, "%s End Of Interrupt.\n", 207 autoEOI ? "Automatic" : "Normal"); 208 209 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 210 initControlWord = 0; 211 break; 212 } 213 break; 214 } 215 pkt->makeAtomicResponse(); 216 return latency; 217} 218 219void 220X86ISA::I8259::handleEOI(int line) 221{ 222 ISR &= ~(1 << line); 223 // There may be an interrupt that was waiting which can 224 // now be sent. 225 if (IRR) 226 requestInterrupt(findMsbSet(IRR)); 227} 228 229void 230X86ISA::I8259::requestInterrupt(int line) 231{ 232 if (bits(ISR, 7, line) == 0) { 233 if (output) { 234 DPRINTF(I8259, "Propogating interrupt.\n"); 235 output->raise(); 236 //XXX This is a hack. 237 output->lower(); 238 } else { 239 warn("Received interrupt but didn't have " 240 "anyone to tell about it.\n"); 241 } 242 } 243} 244 245void 246X86ISA::I8259::signalInterrupt(int line) 247{ 248 DPRINTF(I8259, "Interrupt requested for line %d.\n", line); 249 if (line >= NumLines) 250 fatal("Line number %d doesn't exist. The max is %d.\n", 251 line, NumLines - 1); 252 if (bits(IMR, line)) { 253 DPRINTF(I8259, "Interrupt %d was masked.\n", line); 254 } else { 255 IRR |= 1 << line; 256 requestInterrupt(line); 257 } 258} 259 260void 261X86ISA::I8259::raiseInterruptPin(int number) 262{ 263 DPRINTF(I8259, "Interrupt signal raised for pin %d.\n", number); 264 if (number >= NumLines) 265 fatal("Line number %d doesn't exist. The max is %d.\n", 266 number, NumLines - 1); 267 if (!pinStates[number]) 268 signalInterrupt(number); 269 pinStates[number] = true; 270} 271 272void 273X86ISA::I8259::lowerInterruptPin(int number) 274{ 275 DPRINTF(I8259, "Interrupt signal lowered for pin %d.\n", number); 276 if (number >= NumLines) 277 fatal("Line number %d doesn't exist. The max is %d.\n", 278 number, NumLines - 1); 279 pinStates[number] = false; 280} 281 282int 283X86ISA::I8259::getVector() 284{ 285 /* 286 * This code only handles one slave. Since that's how the PC platform 287 * always uses the 8259 PIC, there shouldn't be any need for more. If 288 * there -is- a need for more for some reason, "slave" can become a 289 * vector of slaves. 290 */ 291 int line = findMsbSet(IRR); 292 IRR &= ~(1 << line); 293 DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 294 if (autoEOI) { 295 handleEOI(line); 296 } else { 297 ISR |= 1 << line; 298 } 299 if (slave && bits(cascadeBits, line)) { 300 DPRINTF(I8259, "Interrupt was from slave who will " 301 "provide the vector.\n"); 302 return slave->getVector(); 303 } 304 return line | vectorOffset; 305} 306 307void 308X86ISA::I8259::serialize(std::ostream &os) 309{ 310 SERIALIZE_ARRAY(pinStates, NumLines); 311 SERIALIZE_ENUM(mode); 312 SERIALIZE_SCALAR(IRR); 313 SERIALIZE_SCALAR(ISR); 314 SERIALIZE_SCALAR(IMR); 315 SERIALIZE_SCALAR(vectorOffset); 316 SERIALIZE_SCALAR(cascadeMode); 317 SERIALIZE_SCALAR(cascadeBits); 318 SERIALIZE_SCALAR(edgeTriggered); 319 SERIALIZE_SCALAR(readIRR); 320 SERIALIZE_SCALAR(expectICW4); 321 SERIALIZE_SCALAR(initControlWord); 322 SERIALIZE_SCALAR(autoEOI); 323} 324 325void 326X86ISA::I8259::unserialize(Checkpoint *cp, const std::string §ion) 327{ 328 UNSERIALIZE_ARRAY(pinStates, NumLines); 329 UNSERIALIZE_ENUM(mode); 330 UNSERIALIZE_SCALAR(IRR); 331 UNSERIALIZE_SCALAR(ISR); 332 UNSERIALIZE_SCALAR(IMR); 333 UNSERIALIZE_SCALAR(vectorOffset); 334 UNSERIALIZE_SCALAR(cascadeMode); 335 UNSERIALIZE_SCALAR(cascadeBits); 336 UNSERIALIZE_SCALAR(edgeTriggered); 337 UNSERIALIZE_SCALAR(readIRR); 338 UNSERIALIZE_SCALAR(expectICW4); 339 UNSERIALIZE_SCALAR(initControlWord); 340 UNSERIALIZE_SCALAR(autoEOI); 341} 342 343X86ISA::I8259 * 344I8259Params::create() 345{ 346 return new X86ISA::I8259(this); 347} 348