i8259.cc revision 5698:584248437e4f
1/* 2 * Copyright (c) 2004-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "base/bitfield.hh" 32#include "dev/x86/i82094aa.hh" 33#include "dev/x86/i8259.hh" 34#include "mem/packet.hh" 35#include "mem/packet_access.hh" 36 37X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this), 38 latency(p->pio_latency), output(p->output), 39 mode(p->mode), slave(NULL), 40 IRR(0), ISR(0), IMR(0), 41 readIRR(true), initControlWord(0), autoEOI(false) 42{ 43 if (output) { 44 I8259 * master; 45 master = dynamic_cast<I8259 *>(output->getDevice()); 46 if (master) 47 master->setSlave(this); 48 I82094AA * ioApic; 49 ioApic = dynamic_cast<I82094AA *>(output->getDevice()); 50 if (ioApic) 51 ioApic->setExtIntPic(this); 52 } 53 pioSize = 2; 54} 55 56Tick 57X86ISA::I8259::read(PacketPtr pkt) 58{ 59 assert(pkt->getSize() == 1); 60 switch(pkt->getAddr() - pioAddr) 61 { 62 case 0x0: 63 if (readIRR) { 64 DPRINTF(I8259, "Reading IRR as %#x.\n", IRR); 65 pkt->set(IRR); 66 } else { 67 DPRINTF(I8259, "Reading ISR as %#x.\n", ISR); 68 pkt->set(ISR); 69 } 70 break; 71 case 0x1: 72 DPRINTF(I8259, "Reading IMR as %#x.\n", IMR); 73 pkt->set(IMR); 74 break; 75 } 76 return latency; 77} 78 79Tick 80X86ISA::I8259::write(PacketPtr pkt) 81{ 82 assert(pkt->getSize() == 1); 83 uint8_t val = pkt->get<uint8_t>(); 84 switch (pkt->getAddr() - pioAddr) { 85 case 0x0: 86 if (bits(val, 4)) { 87 DPRINTF(I8259, "Received initialization command word 1.\n"); 88 IMR = 0; 89 edgeTriggered = bits(val, 3); 90 DPRINTF(I8259, "%s triggered mode.\n", 91 edgeTriggered ? "Edge" : "Level"); 92 cascadeMode = !bits(val, 1); 93 DPRINTF(I8259, "%s mode.\n", 94 cascadeMode ? "Cascade" : "Single"); 95 expectICW4 = bits(val, 0); 96 if (!expectICW4) { 97 autoEOI = false; 98 } 99 initControlWord = 1; 100 DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2); 101 } else if (bits(val, 4, 3) == 0) { 102 DPRINTF(I8259, "Received operation command word 2.\n"); 103 switch (bits(val, 7, 5)) { 104 case 0x0: 105 DPRINTF(I8259, 106 "Subcommand: Rotate in auto-EOI mode (clear).\n"); 107 break; 108 case 0x1: 109 { 110 int line = findMsbSet(ISR); 111 DPRINTF(I8259, "Subcommand: Nonspecific EOI on line %d.\n", 112 line); 113 handleEOI(line); 114 } 115 break; 116 case 0x2: 117 DPRINTF(I8259, "Subcommand: No operation.\n"); 118 break; 119 case 0x3: 120 { 121 int line = bits(val, 2, 0); 122 DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n", 123 line); 124 handleEOI(line); 125 } 126 break; 127 case 0x4: 128 DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n"); 129 break; 130 case 0x5: 131 DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n"); 132 break; 133 case 0x6: 134 DPRINTF(I8259, "Subcommand: Set priority command.\n"); 135 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 136 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 137 break; 138 case 0x7: 139 DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n"); 140 DPRINTF(I8259, "Lowest: IRQ%d Highest IRQ%d.\n", 141 bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8); 142 break; 143 } 144 } else if (bits(val, 4, 3) == 1) { 145 DPRINTF(I8259, "Received operation command word 3.\n"); 146 if (bits(val, 7)) { 147 DPRINTF(I8259, "%s special mask mode.\n", 148 bits(val, 6) ? "Set" : "Clear"); 149 } 150 if (bits(val, 1)) { 151 readIRR = bits(val, 0); 152 DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR"); 153 } 154 } 155 break; 156 case 0x1: 157 switch (initControlWord) { 158 case 0x0: 159 DPRINTF(I8259, "Received operation command word 1.\n"); 160 DPRINTF(I8259, "Wrote IMR value %#x.\n", val); 161 IMR = val; 162 break; 163 case 0x1: 164 DPRINTF(I8259, "Received initialization command word 2.\n"); 165 vectorOffset = val & ~mask(3); 166 DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n", 167 vectorOffset, vectorOffset | mask(3)); 168 if (cascadeMode) { 169 initControlWord++; 170 } else { 171 cascadeBits = 0; 172 initControlWord = 0; 173 } 174 break; 175 case 0x2: 176 DPRINTF(I8259, "Received initialization command word 3.\n"); 177 if (mode == Enums::I8259Master) { 178 DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n", 179 bits(val, 0) ? " 0" : "", 180 bits(val, 1) ? " 1" : "", 181 bits(val, 2) ? " 2" : "", 182 bits(val, 3) ? " 3" : "", 183 bits(val, 4) ? " 4" : "", 184 bits(val, 5) ? " 5" : "", 185 bits(val, 6) ? " 6" : "", 186 bits(val, 7) ? " 7" : ""); 187 cascadeBits = val; 188 } else { 189 DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3)); 190 cascadeBits = val & mask(3); 191 } 192 if (expectICW4) 193 initControlWord++; 194 else 195 initControlWord = 0; 196 break; 197 case 0x3: 198 DPRINTF(I8259, "Received initialization command word 4.\n"); 199 if (bits(val, 4)) { 200 DPRINTF(I8259, "Special fully nested mode.\n"); 201 } else { 202 DPRINTF(I8259, "Not special fully nested mode.\n"); 203 } 204 if (bits(val, 3) == 0) { 205 DPRINTF(I8259, "Nonbuffered.\n"); 206 } else if (bits(val, 2) == 0) { 207 DPRINTF(I8259, "Buffered.\n"); 208 } else { 209 DPRINTF(I8259, "Unrecognized buffer mode.\n"); 210 } 211 autoEOI = bits(val, 1); 212 DPRINTF(I8259, "%s End Of Interrupt.\n", 213 autoEOI ? "Automatic" : "Normal"); 214 215 DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85"); 216 initControlWord = 0; 217 break; 218 } 219 break; 220 } 221 return latency; 222} 223 224void 225X86ISA::I8259::handleEOI(int line) 226{ 227 ISR &= ~(1 << line); 228 // There may be an interrupt that was waiting which can 229 // now be sent. 230 if (IRR) 231 requestInterrupt(findMsbSet(IRR)); 232} 233 234void 235X86ISA::I8259::requestInterrupt(int line) 236{ 237 if (bits(ISR, 7, line) == 0) { 238 if (output) { 239 DPRINTF(I8259, "Propogating interrupt.\n"); 240 output->signalInterrupt(); 241 } else { 242 warn("Received interrupt but didn't have " 243 "anyone to tell about it.\n"); 244 } 245 } 246} 247 248void 249X86ISA::I8259::signalInterrupt(int line) 250{ 251 DPRINTF(I8259, "Interrupt raised on line %d.\n", line); 252 if (line >= NumLines) 253 fatal("Line number %d doesn't exist. The max is %d.\n", 254 line, NumLines - 1); 255 if (bits(IMR, line)) { 256 DPRINTF(I8259, "Interrupt %d was masked.\n", line); 257 } else { 258 IRR |= 1 << line; 259 requestInterrupt(line); 260 } 261} 262 263int 264X86ISA::I8259::getVector() 265{ 266 /* 267 * This code only handles one slave. Since that's how the PC platform 268 * always uses the 8259 PIC, there shouldn't be any need for more. If 269 * there -is- a need for more for some reason, "slave" can become a 270 * vector of slaves. 271 */ 272 int line = findMsbSet(IRR); 273 IRR &= ~(1 << line); 274 DPRINTF(I8259, "Interrupt %d was accepted.\n", line); 275 if (autoEOI) { 276 handleEOI(line); 277 } else { 278 ISR |= 1 << line; 279 } 280 if (slave && bits(cascadeBits, line)) { 281 DPRINTF(I8259, "Interrupt was from slave who will " 282 "provide the vector.\n"); 283 return slave->getVector(); 284 } 285 return line | vectorOffset; 286} 287 288X86ISA::I8259 * 289I8259Params::create() 290{ 291 return new X86ISA::I8259(this); 292} 293