i8259.cc revision 5686:f33045b4dbee 
1/*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31#include "base/bitfield.hh"
32#include "dev/x86/i82094aa.hh"
33#include "dev/x86/i8259.hh"
34
35X86ISA::I8259::I8259(Params * p) : BasicPioDevice(p), IntDev(this),
36                    latency(p->pio_latency), output(p->output),
37                    mode(p->mode), slave(NULL),
38                    IRR(0), ISR(0), IMR(0),
39                    readIRR(true), initControlWord(0)
40{
41    if (output) {
42        I8259 * master;
43        master = dynamic_cast<I8259 *>(output->getDevice());
44        if (master)
45            master->setSlave(this);
46        I82094AA * ioApic;
47        ioApic = dynamic_cast<I82094AA *>(output->getDevice());
48        if (ioApic)
49            ioApic->setExtIntPic(this);
50    }
51    pioSize = 2;
52}
53
54Tick
55X86ISA::I8259::read(PacketPtr pkt)
56{
57    assert(pkt->getSize() == 1);
58    switch(pkt->getAddr() - pioAddr)
59    {
60      case 0x0:
61        if (readIRR) {
62            DPRINTF(I8259, "Reading IRR as %#x.\n", IRR);
63            pkt->set(IRR);
64        } else {
65            DPRINTF(I8259, "Reading ISR as %#x.\n", ISR);
66            pkt->set(ISR);
67        }
68        break;
69      case 0x1:
70        DPRINTF(I8259, "Reading IMR as %#x.\n", IMR);
71        pkt->set(IMR);
72        break;
73    }
74    return latency;
75}
76
77Tick
78X86ISA::I8259::write(PacketPtr pkt)
79{
80    assert(pkt->getSize() == 1);
81    uint8_t val = pkt->get<uint8_t>();
82    switch (pkt->getAddr() - pioAddr) {
83      case 0x0:
84        if (bits(val, 4)) {
85            DPRINTF(I8259, "Received initialization command word 1.\n");
86            IMR = 0;
87            edgeTriggered = bits(val, 3);
88            DPRINTF(I8259, "%s triggered mode.\n",
89                    edgeTriggered ? "Edge" : "Level");
90            cascadeMode = !bits(val, 1);
91            DPRINTF(I8259, "%s mode.\n",
92                    cascadeMode ? "Cascade" : "Single");
93            expectICW4 = bits(val, 0);
94            initControlWord = 1;
95            DPRINTF(I8259, "Expecting %d more bytes.\n", expectICW4 ? 3 : 2);
96        } else if (bits(val, 4, 3) == 0) {
97            DPRINTF(I8259, "Received operation command word 2.\n");
98            switch (bits(val, 7, 5)) {
99              case 0x0:
100                DPRINTF(I8259,
101                        "Subcommand: Rotate in auto-EOI mode (clear).\n");
102                break;
103              case 0x1:
104                DPRINTF(I8259, "Subcommand: Nonspecific EOI.\n");
105                break;
106              case 0x2:
107                DPRINTF(I8259, "Subcommand: No operation.\n");
108                break;
109              case 0x3:
110                {
111                    int line = bits(val, 2, 0);
112                    DPRINTF(I8259, "Subcommand: Specific EIO on line %d.\n",
113                            line);
114                    handleEOI(line);
115                }
116                break;
117              case 0x4:
118                DPRINTF(I8259, "Subcommand: Rotate in auto-EOI mode (set).\n");
119                break;
120              case 0x5:
121                DPRINTF(I8259, "Subcommand: Rotate on nonspecific EOI.\n");
122                break;
123              case 0x6:
124                DPRINTF(I8259, "Subcommand: Set priority command.\n");
125                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
126                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
127                break;
128              case 0x7:
129                DPRINTF(I8259, "Subcommand: Rotate on specific EOI.\n");
130                DPRINTF(I8259, "Lowest: IRQ%d   Highest IRQ%d.\n",
131                        bits(val, 2, 0), (bits(val, 2, 0) + 1) % 8);
132                break;
133            }
134        } else if (bits(val, 4, 3) == 1) {
135            DPRINTF(I8259, "Received operation command word 3.\n");
136            if (bits(val, 7)) {
137                DPRINTF(I8259, "%s special mask mode.\n",
138                        bits(val, 6) ? "Set" : "Clear");
139            }
140            if (bits(val, 1)) {
141                readIRR = bits(val, 0);
142                DPRINTF(I8259, "Read %s.\n", readIRR ? "IRR" : "ISR");
143            }
144        }
145        break;
146      case 0x1:
147        switch (initControlWord) {
148          case 0x0:
149            DPRINTF(I8259, "Received operation command word 1.\n");
150            DPRINTF(I8259, "Wrote IMR value %#x.\n", val);
151            IMR = val;
152            break;
153          case 0x1:
154            DPRINTF(I8259, "Received initialization command word 2.\n");
155            vectorOffset = val & ~mask(3);
156            DPRINTF(I8259, "Responsible for vectors %#x-%#x.\n",
157                    vectorOffset, vectorOffset | mask(3));
158            if (cascadeMode) {
159                initControlWord++;
160            } else {
161                cascadeBits = 0;
162                initControlWord = 0;
163            }
164            break;
165          case 0x2:
166            DPRINTF(I8259, "Received initialization command word 3.\n");
167            if (mode == Enums::I8259Master) {
168                DPRINTF(I8259, "Slaves attached to IRQs:%s%s%s%s%s%s%s%s\n",
169                        bits(val, 0) ? " 0" : "",
170                        bits(val, 1) ? " 1" : "",
171                        bits(val, 2) ? " 2" : "",
172                        bits(val, 3) ? " 3" : "",
173                        bits(val, 4) ? " 4" : "",
174                        bits(val, 5) ? " 5" : "",
175                        bits(val, 6) ? " 6" : "",
176                        bits(val, 7) ? " 7" : "");
177                cascadeBits = val;
178            } else {
179                DPRINTF(I8259, "Slave ID is %d.\n", val & mask(3));
180                cascadeBits = val & mask(3);
181            }
182            if (expectICW4)
183                initControlWord++;
184            else
185                initControlWord = 0;
186            break;
187          case 0x3:
188            DPRINTF(I8259, "Received initialization command word 4.\n");
189            if (bits(val, 4)) {
190                DPRINTF(I8259, "Special fully nested mode.\n");
191            } else {
192                DPRINTF(I8259, "Not special fully nested mode.\n");
193            }
194            if (bits(val, 3) == 0) {
195                DPRINTF(I8259, "Nonbuffered.\n");
196            } else if (bits(val, 2) == 0) {
197                DPRINTF(I8259, "Buffered.\n");
198            } else {
199                DPRINTF(I8259, "Unrecognized buffer mode.\n");
200            }
201            DPRINTF(I8259, "%s End Of Interrupt.\n",
202                    bits(val, 1) ? "Automatic" : "Normal");
203            DPRINTF(I8259, "%s mode.\n", bits(val, 0) ? "80x86" : "MCX-80/85");
204            initControlWord = 0;
205            break;
206        }
207        break;
208    }
209    return latency;
210}
211
212void
213X86ISA::I8259::handleEOI(int line)
214{
215    ISR &= ~(1 << line);
216    // There may be an interrupt that was waiting which can
217    // now be sent.
218    if (IRR)
219        requestInterrupt(findMsbSet(IRR));
220}
221
222void
223X86ISA::I8259::requestInterrupt(int line)
224{
225    if (bits(ISR, 7, line) == 0) {
226        if (output) {
227            DPRINTF(I8259, "Propogating interrupt.\n");
228            output->signalInterrupt();
229        } else {
230            warn("Received interrupt but didn't have "
231                    "anyone to tell about it.\n");
232        }
233    }
234}
235
236void
237X86ISA::I8259::signalInterrupt(int line)
238{
239    DPRINTF(I8259, "Interrupt raised on line %d.\n", line);
240    if (line >= NumLines)
241        fatal("Line number %d doesn't exist. The max is %d.\n",
242                line, NumLines - 1);
243    if (bits(IMR, line)) {
244        DPRINTF(I8259, "Interrupt %d was masked.\n", line);
245    } else {
246        IRR |= 1 << line;
247        requestInterrupt(line);
248    }
249}
250
251int
252X86ISA::I8259::getVector()
253{
254    /*
255     * This code only handles one slave. Since that's how the PC platform
256     * always uses the 8259 PIC, there shouldn't be any need for more. If
257     * there -is- a need for more for some reason, "slave" can become a
258     * vector of slaves.
259     */
260    int line = findMsbSet(IRR);
261    IRR &= ~(1 << line);
262    DPRINTF(I8259, "Interrupt %d was accepted.\n", line);
263    ISR |= 1 << line;
264    if (slave && bits(cascadeBits, line)) {
265        DPRINTF(I8259, "Interrupt was from slave who will "
266                "provide the vector.\n");
267        return slave->getVector();
268    }
269    return line | vectorOffset;
270}
271
272X86ISA::I8259 *
273I8259Params::create()
274{
275    return new X86ISA::I8259(this);
276}
277