i82094aa.cc revision 7913:70b56a9ac1b2
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/interrupts.hh" 32#include "arch/x86/intmessage.hh" 33#include "dev/x86/i82094aa.hh" 34#include "dev/x86/i8259.hh" 35#include "mem/packet.hh" 36#include "mem/packet_access.hh" 37#include "sim/system.hh" 38 39X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 40 IntDev(this, p->int_latency), 41 latency(p->pio_latency), pioAddr(p->pio_addr), 42 extIntPic(p->external_int_pic), lowestPriorityOffset(0) 43{ 44 // This assumes there's only one I/O APIC in the system and since the apic 45 // id is stored in a 8-bit field with 0xff meaning broadcast, the id must 46 // be less than 0xff 47 48 assert(p->apic_id < 0xff); 49 initialApicId = id = p->apic_id; 50 arbId = id; 51 regSel = 0; 52 RedirTableEntry entry = 0; 53 entry.mask = 1; 54 for (int i = 0; i < TableSize; i++) { 55 redirTable[i] = entry; 56 pinStates[i] = false; 57 } 58} 59 60void 61X86ISA::I82094AA::init() 62{ 63 // The io apic must register its address ranges on both its pio port 64 // via the piodevice init() function and its int port that it inherited 65 // from IntDev. Note IntDev is not a SimObject itself. 66 67 PioDevice::init(); 68 IntDev::init(); 69} 70 71Tick 72X86ISA::I82094AA::read(PacketPtr pkt) 73{ 74 assert(pkt->getSize() == 4); 75 Addr offset = pkt->getAddr() - pioAddr; 76 switch(offset) { 77 case 0: 78 pkt->set<uint32_t>(regSel); 79 break; 80 case 16: 81 pkt->set<uint32_t>(readReg(regSel)); 82 break; 83 default: 84 panic("Illegal read from I/O APIC.\n"); 85 } 86 pkt->makeAtomicResponse(); 87 return latency; 88} 89 90Tick 91X86ISA::I82094AA::write(PacketPtr pkt) 92{ 93 assert(pkt->getSize() == 4); 94 Addr offset = pkt->getAddr() - pioAddr; 95 switch(offset) { 96 case 0: 97 regSel = pkt->get<uint32_t>(); 98 break; 99 case 16: 100 writeReg(regSel, pkt->get<uint32_t>()); 101 break; 102 default: 103 panic("Illegal write to I/O APIC.\n"); 104 } 105 pkt->makeAtomicResponse(); 106 return latency; 107} 108 109void 110X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 111{ 112 if (offset == 0x0) { 113 id = bits(value, 31, 24); 114 } else if (offset == 0x1) { 115 // The IOAPICVER register is read only. 116 } else if (offset == 0x2) { 117 arbId = bits(value, 31, 24); 118 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 119 int index = (offset - 0x10) / 2; 120 if (offset % 2) { 121 redirTable[index].topDW = value; 122 redirTable[index].topReserved = 0; 123 } else { 124 redirTable[index].bottomDW = value; 125 redirTable[index].bottomReserved = 0; 126 } 127 } else { 128 warn("Access to undefined I/O APIC register %#x.\n", offset); 129 } 130 DPRINTF(I82094AA, 131 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 132} 133 134uint32_t 135X86ISA::I82094AA::readReg(uint8_t offset) 136{ 137 uint32_t result = 0; 138 if (offset == 0x0) { 139 result = id << 24; 140 } else if (offset == 0x1) { 141 result = ((TableSize - 1) << 16) | APICVersion; 142 } else if (offset == 0x2) { 143 result = arbId << 24; 144 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 145 int index = (offset - 0x10) / 2; 146 if (offset % 2) { 147 result = redirTable[index].topDW; 148 } else { 149 result = redirTable[index].bottomDW; 150 } 151 } else { 152 warn("Access to undefined I/O APIC register %#x.\n", offset); 153 } 154 DPRINTF(I82094AA, 155 "Read %#x from I/O APIC register %#x.\n", result, offset); 156 return result; 157} 158 159void 160X86ISA::I82094AA::signalInterrupt(int line) 161{ 162 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 163 assert(line < TableSize); 164 RedirTableEntry entry = redirTable[line]; 165 if (entry.mask) { 166 DPRINTF(I82094AA, "Entry was masked.\n"); 167 return; 168 } else { 169 TriggerIntMessage message = 0; 170 message.destination = entry.dest; 171 if (entry.deliveryMode == DeliveryMode::ExtInt) { 172 assert(extIntPic); 173 message.vector = extIntPic->getVector(); 174 } else { 175 message.vector = entry.vector; 176 } 177 message.deliveryMode = entry.deliveryMode; 178 message.destMode = entry.destMode; 179 message.level = entry.polarity; 180 message.trigger = entry.trigger; 181 ApicList apics; 182 int numContexts = sys->numContexts(); 183 if (message.destMode == 0) { 184 if (message.deliveryMode == DeliveryMode::LowestPriority) { 185 panic("Lowest priority delivery mode from the " 186 "IO APIC aren't supported in physical " 187 "destination mode.\n"); 188 } 189 if (message.destination == 0xFF) { 190 for (int i = 0; i < numContexts; i++) { 191 apics.push_back(i); 192 } 193 } else { 194 apics.push_back(message.destination); 195 } 196 } else { 197 for (int i = 0; i < numContexts; i++) { 198 std::map<int, Interrupts *>::iterator localApicIt = 199 localApics.find(i); 200 assert(localApicIt != localApics.end()); 201 Interrupts *localApic = localApicIt->second; 202 if ((localApic->readReg(APIC_LOGICAL_DESTINATION) >> 24) & 203 message.destination) { 204 apics.push_back(localApicIt->first); 205 } 206 } 207 if (message.deliveryMode == DeliveryMode::LowestPriority && 208 apics.size()) { 209 // The manual seems to suggest that the chipset just does 210 // something reasonable for these instead of actually using 211 // state from the local APIC. We'll just rotate an offset 212 // through the set of APICs selected above. 213 uint64_t modOffset = lowestPriorityOffset % apics.size(); 214 lowestPriorityOffset++; 215 ApicList::iterator apicIt = apics.begin(); 216 while (modOffset--) { 217 apicIt++; 218 assert(apicIt != apics.end()); 219 } 220 int selected = *apicIt; 221 apics.clear(); 222 apics.push_back(selected); 223 } 224 } 225 intPort->sendMessage(apics, message, 226 sys->getMemoryMode() == Enums::timing); 227 } 228} 229 230void 231X86ISA::I82094AA::raiseInterruptPin(int number) 232{ 233 assert(number < TableSize); 234 if (!pinStates[number]) 235 signalInterrupt(number); 236 pinStates[number] = true; 237} 238 239void 240X86ISA::I82094AA::lowerInterruptPin(int number) 241{ 242 assert(number < TableSize); 243 pinStates[number] = false; 244} 245 246void 247X86ISA::I82094AA::registerLocalApic(int initialId, Interrupts *localApic) 248{ 249 assert(localApic); 250 localApics[initialId] = localApic; 251} 252 253void 254X86ISA::I82094AA::serialize(std::ostream &os) 255{ 256 uint64_t* redirTableArray = (uint64_t*)redirTable; 257 SERIALIZE_SCALAR(regSel); 258 SERIALIZE_SCALAR(initialApicId); 259 SERIALIZE_SCALAR(id); 260 SERIALIZE_SCALAR(arbId); 261 SERIALIZE_SCALAR(lowestPriorityOffset); 262 SERIALIZE_ARRAY(redirTableArray, TableSize); 263 SERIALIZE_ARRAY(pinStates, TableSize); 264} 265 266void 267X86ISA::I82094AA::unserialize(Checkpoint *cp, const std::string §ion) 268{ 269 uint64_t redirTableArray[TableSize]; 270 UNSERIALIZE_SCALAR(regSel); 271 UNSERIALIZE_SCALAR(initialApicId); 272 UNSERIALIZE_SCALAR(id); 273 UNSERIALIZE_SCALAR(arbId); 274 UNSERIALIZE_SCALAR(lowestPriorityOffset); 275 UNSERIALIZE_ARRAY(redirTableArray, TableSize); 276 UNSERIALIZE_ARRAY(pinStates, TableSize); 277 for (int i = 0; i < TableSize; i++) { 278 redirTable[i] = (RedirTableEntry)redirTableArray[i]; 279 } 280} 281 282X86ISA::I82094AA * 283I82094AAParams::create() 284{ 285 return new X86ISA::I82094AA(this); 286} 287