i82094aa.cc revision 5654:340254de2031
1/* 2 * Copyright (c) 2008 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * Authors: Gabe Black 29 */ 30 31#include "arch/x86/intmessage.hh" 32#include "dev/x86/i82094aa.hh" 33#include "mem/packet.hh" 34#include "mem/packet_access.hh" 35#include "sim/system.hh" 36 37X86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 38 latency(p->pio_latency), pioAddr(p->pio_addr) 39{ 40 // This assumes there's only one I/O APIC in the system 41 id = sys->getNumCPUs(); 42 assert(id <= 0xf); 43 arbId = id; 44 regSel = 0; 45 RedirTableEntry entry = 0; 46 entry.mask = 1; 47 for (int i = 0; i < TableSize; i++) { 48 redirTable[i] = entry; 49 } 50} 51 52Tick 53X86ISA::I82094AA::read(PacketPtr pkt) 54{ 55 assert(pkt->getSize() == 4); 56 Addr offset = pkt->getAddr() - pioAddr; 57 switch(offset) { 58 case 0: 59 pkt->set<uint32_t>(regSel); 60 break; 61 case 16: 62 pkt->set<uint32_t>(readReg(regSel)); 63 break; 64 default: 65 panic("Illegal read from I/O APIC.\n"); 66 } 67 return latency; 68} 69 70Tick 71X86ISA::I82094AA::write(PacketPtr pkt) 72{ 73 assert(pkt->getSize() == 4); 74 Addr offset = pkt->getAddr() - pioAddr; 75 switch(offset) { 76 case 0: 77 regSel = pkt->get<uint32_t>(); 78 break; 79 case 16: 80 writeReg(regSel, pkt->get<uint32_t>()); 81 break; 82 default: 83 panic("Illegal write to I/O APIC.\n"); 84 } 85 return latency; 86} 87 88void 89X86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 90{ 91 if (offset == 0x0) { 92 id = bits(value, 27, 24); 93 } else if (offset == 0x1) { 94 // The IOAPICVER register is read only. 95 } else if (offset == 0x2) { 96 arbId = bits(value, 27, 24); 97 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 98 int index = (offset - 0x10) / 2; 99 if (offset % 2) { 100 redirTable[index].topDW = value; 101 redirTable[index].topReserved = 0; 102 } else { 103 redirTable[index].bottomDW = value; 104 redirTable[index].bottomReserved = 0; 105 } 106 } else { 107 warn("Access to undefined I/O APIC register %#x.\n", offset); 108 } 109 DPRINTF(I82094AA, 110 "Wrote %#x to I/O APIC register %#x .\n", value, offset); 111} 112 113uint32_t 114X86ISA::I82094AA::readReg(uint8_t offset) 115{ 116 uint32_t result = 0; 117 if (offset == 0x0) { 118 result = id << 24; 119 } else if (offset == 0x1) { 120 result = ((TableSize - 1) << 16) | APICVersion; 121 } else if (offset == 0x2) { 122 result = arbId << 24; 123 } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 124 int index = (offset - 0x10) / 2; 125 if (offset % 2) { 126 result = redirTable[index].topDW; 127 } else { 128 result = redirTable[index].bottomDW; 129 } 130 } else { 131 warn("Access to undefined I/O APIC register %#x.\n", offset); 132 } 133 DPRINTF(I82094AA, 134 "Read %#x from I/O APIC register %#x.\n", result, offset); 135 return result; 136} 137 138void 139X86ISA::I82094AA::signalInterrupt(int line) 140{ 141 DPRINTF(I82094AA, "Received interrupt %d.\n", line); 142 assert(line < TableSize); 143 RedirTableEntry entry = redirTable[line]; 144 if (entry.mask) { 145 DPRINTF(I82094AA, "Entry was masked.\n"); 146 return; 147 } else { 148 if (DTRACE(I82094AA)) { 149 if (DeliveryMode::isReserved(entry.deliveryMode)) { 150 fatal("Tried to use reserved delivery mode " 151 "for IO APIC entry %d.\n", line); 152 } else { 153 DPRINTF(I82094AA, "Delivery mode is: %s.\n", 154 DeliveryMode::names[entry.deliveryMode]); 155 } 156 DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector); 157 } 158 159 TriggerIntMessage message; 160 message.destination = entry.dest; 161 message.vector = entry.vector; 162 message.deliveryMode = entry.deliveryMode; 163 message.destMode = entry.destMode; 164 message.level = entry.polarity; 165 message.trigger = entry.trigger; 166 167 if (entry.destMode == 0) { 168 DPRINTF(I82094AA, 169 "Sending interrupt to APIC ID %d.\n", entry.dest); 170 PacketPtr pkt = buildIntRequest(entry.dest, message); 171 if (sys->getMemoryMode() == Enums::timing) 172 intPort->sendMessageTiming(pkt, latency); 173 else if (sys->getMemoryMode() == Enums::atomic) 174 intPort->sendMessageAtomic(pkt); 175 else 176 panic("Unrecognized memory mode.\n"); 177 } else { 178 DPRINTF(I82094AA, "Sending interrupts to APIC IDs:" 179 "%s%s%s%s%s%s%s%s\n", 180 bits((int)entry.dest, 0) ? " 0": "", 181 bits((int)entry.dest, 1) ? " 1": "", 182 bits((int)entry.dest, 2) ? " 2": "", 183 bits((int)entry.dest, 3) ? " 3": "", 184 bits((int)entry.dest, 4) ? " 4": "", 185 bits((int)entry.dest, 5) ? " 5": "", 186 bits((int)entry.dest, 6) ? " 6": "", 187 bits((int)entry.dest, 7) ? " 7": "" 188 ); 189 uint8_t dests = entry.dest; 190 uint8_t id = 0; 191 while(dests) { 192 if (dests & 0x1) { 193 PacketPtr pkt = buildIntRequest(id, message); 194 if (sys->getMemoryMode() == Enums::timing) 195 intPort->sendMessageTiming(pkt, latency); 196 else if (sys->getMemoryMode() == Enums::atomic) 197 intPort->sendMessageAtomic(pkt); 198 else 199 panic("Unrecognized memory mode.\n"); 200 } 201 dests >>= 1; 202 id++; 203 } 204 } 205 } 206} 207 208X86ISA::I82094AA * 209I82094AAParams::create() 210{ 211 return new X86ISA::I82094AA(this); 212} 213