i82094aa.cc revision 6136
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 315651Sgblack@eecs.umich.edu#include "arch/x86/intmessage.hh" 325643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 335657Sgblack@eecs.umich.edu#include "dev/x86/i8259.hh" 345643Sgblack@eecs.umich.edu#include "mem/packet.hh" 355643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 365643Sgblack@eecs.umich.edu#include "sim/system.hh" 375643Sgblack@eecs.umich.edu 385651Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), IntDev(this), 395827Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr), 405827Sgblack@eecs.umich.edu extIntPic(p->external_int_pic) 415643Sgblack@eecs.umich.edu{ 425643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 436136Sgblack@eecs.umich.edu initialApicId = id = p->apic_id; 445643Sgblack@eecs.umich.edu assert(id <= 0xf); 455643Sgblack@eecs.umich.edu arbId = id; 465643Sgblack@eecs.umich.edu regSel = 0; 475653Sgblack@eecs.umich.edu RedirTableEntry entry = 0; 485653Sgblack@eecs.umich.edu entry.mask = 1; 495653Sgblack@eecs.umich.edu for (int i = 0; i < TableSize; i++) { 505653Sgblack@eecs.umich.edu redirTable[i] = entry; 515827Sgblack@eecs.umich.edu pinStates[i] = false; 525653Sgblack@eecs.umich.edu } 535643Sgblack@eecs.umich.edu} 545643Sgblack@eecs.umich.edu 555643Sgblack@eecs.umich.eduTick 565643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 575643Sgblack@eecs.umich.edu{ 585643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 595643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 605643Sgblack@eecs.umich.edu switch(offset) { 615643Sgblack@eecs.umich.edu case 0: 625643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 635643Sgblack@eecs.umich.edu break; 645643Sgblack@eecs.umich.edu case 16: 655643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 665643Sgblack@eecs.umich.edu break; 675643Sgblack@eecs.umich.edu default: 685643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 695643Sgblack@eecs.umich.edu } 705898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 715643Sgblack@eecs.umich.edu return latency; 725643Sgblack@eecs.umich.edu} 735643Sgblack@eecs.umich.edu 745643Sgblack@eecs.umich.eduTick 755643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 765643Sgblack@eecs.umich.edu{ 775643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 785643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 795643Sgblack@eecs.umich.edu switch(offset) { 805643Sgblack@eecs.umich.edu case 0: 815643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 825643Sgblack@eecs.umich.edu break; 835643Sgblack@eecs.umich.edu case 16: 845643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 855643Sgblack@eecs.umich.edu break; 865643Sgblack@eecs.umich.edu default: 875643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 885643Sgblack@eecs.umich.edu } 895898Sgblack@eecs.umich.edu pkt->makeAtomicResponse(); 905643Sgblack@eecs.umich.edu return latency; 915643Sgblack@eecs.umich.edu} 925643Sgblack@eecs.umich.edu 935643Sgblack@eecs.umich.eduvoid 945643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 955643Sgblack@eecs.umich.edu{ 965643Sgblack@eecs.umich.edu if (offset == 0x0) { 975643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 985643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 995643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 1005643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1015643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 1025643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1035643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1045643Sgblack@eecs.umich.edu if (offset % 2) { 1055643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 1065643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 1075643Sgblack@eecs.umich.edu } else { 1085643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 1095643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1105643Sgblack@eecs.umich.edu } 1115643Sgblack@eecs.umich.edu } else { 1125643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1135643Sgblack@eecs.umich.edu } 1145643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1155643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1165643Sgblack@eecs.umich.edu} 1175643Sgblack@eecs.umich.edu 1185643Sgblack@eecs.umich.eduuint32_t 1195643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1205643Sgblack@eecs.umich.edu{ 1215643Sgblack@eecs.umich.edu uint32_t result = 0; 1225643Sgblack@eecs.umich.edu if (offset == 0x0) { 1235643Sgblack@eecs.umich.edu result = id << 24; 1245643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1255643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1265643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1275643Sgblack@eecs.umich.edu result = arbId << 24; 1285643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1295643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1305643Sgblack@eecs.umich.edu if (offset % 2) { 1315643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1325643Sgblack@eecs.umich.edu } else { 1335643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1345643Sgblack@eecs.umich.edu } 1355643Sgblack@eecs.umich.edu } else { 1365643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1375643Sgblack@eecs.umich.edu } 1385643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1395643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1405643Sgblack@eecs.umich.edu return result; 1415643Sgblack@eecs.umich.edu} 1425643Sgblack@eecs.umich.edu 1435643Sgblack@eecs.umich.eduvoid 1445643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1455643Sgblack@eecs.umich.edu{ 1465643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1475643Sgblack@eecs.umich.edu assert(line < TableSize); 1485643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1495643Sgblack@eecs.umich.edu if (entry.mask) { 1505643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1515643Sgblack@eecs.umich.edu return; 1525643Sgblack@eecs.umich.edu } else { 1535651Sgblack@eecs.umich.edu TriggerIntMessage message; 1545651Sgblack@eecs.umich.edu message.destination = entry.dest; 1555657Sgblack@eecs.umich.edu if (entry.deliveryMode == DeliveryMode::ExtInt) { 1565657Sgblack@eecs.umich.edu assert(extIntPic); 1575657Sgblack@eecs.umich.edu message.vector = extIntPic->getVector(); 1585657Sgblack@eecs.umich.edu } else { 1595657Sgblack@eecs.umich.edu message.vector = entry.vector; 1605657Sgblack@eecs.umich.edu } 1615651Sgblack@eecs.umich.edu message.deliveryMode = entry.deliveryMode; 1625651Sgblack@eecs.umich.edu message.destMode = entry.destMode; 1635654Sgblack@eecs.umich.edu message.level = entry.polarity; 1645654Sgblack@eecs.umich.edu message.trigger = entry.trigger; 1656045Sgblack@eecs.umich.edu intPort->sendMessage(message, sys->getMemoryMode() == Enums::timing); 1665643Sgblack@eecs.umich.edu } 1675643Sgblack@eecs.umich.edu} 1685643Sgblack@eecs.umich.edu 1695827Sgblack@eecs.umich.eduvoid 1705827Sgblack@eecs.umich.eduX86ISA::I82094AA::raiseInterruptPin(int number) 1715827Sgblack@eecs.umich.edu{ 1725827Sgblack@eecs.umich.edu assert(number < TableSize); 1735827Sgblack@eecs.umich.edu if (!pinStates[number]) 1745827Sgblack@eecs.umich.edu signalInterrupt(number); 1755827Sgblack@eecs.umich.edu pinStates[number] = true; 1765827Sgblack@eecs.umich.edu} 1775827Sgblack@eecs.umich.edu 1785827Sgblack@eecs.umich.eduvoid 1795827Sgblack@eecs.umich.eduX86ISA::I82094AA::lowerInterruptPin(int number) 1805827Sgblack@eecs.umich.edu{ 1815827Sgblack@eecs.umich.edu assert(number < TableSize); 1825827Sgblack@eecs.umich.edu pinStates[number] = false; 1835827Sgblack@eecs.umich.edu} 1845827Sgblack@eecs.umich.edu 1855643Sgblack@eecs.umich.eduX86ISA::I82094AA * 1865643Sgblack@eecs.umich.eduI82094AAParams::create() 1875643Sgblack@eecs.umich.edu{ 1885643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 1895643Sgblack@eecs.umich.edu} 190