i82094aa.cc revision 5643
15643Sgblack@eecs.umich.edu/* 25643Sgblack@eecs.umich.edu * Copyright (c) 2008 The Regents of The University of Michigan 35643Sgblack@eecs.umich.edu * All rights reserved. 45643Sgblack@eecs.umich.edu * 55643Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 65643Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 75643Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 85643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 95643Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 105643Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 115643Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 125643Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 135643Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 145643Sgblack@eecs.umich.edu * this software without specific prior written permission. 155643Sgblack@eecs.umich.edu * 165643Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175643Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185643Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195643Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205643Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215643Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225643Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235643Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245643Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255643Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265643Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275643Sgblack@eecs.umich.edu * 285643Sgblack@eecs.umich.edu * Authors: Gabe Black 295643Sgblack@eecs.umich.edu */ 305643Sgblack@eecs.umich.edu 315643Sgblack@eecs.umich.edu#include "dev/x86/i82094aa.hh" 325643Sgblack@eecs.umich.edu#include "mem/packet.hh" 335643Sgblack@eecs.umich.edu#include "mem/packet_access.hh" 345643Sgblack@eecs.umich.edu#include "sim/system.hh" 355643Sgblack@eecs.umich.edu 365643Sgblack@eecs.umich.eduX86ISA::I82094AA::I82094AA(Params *p) : PioDevice(p), 375643Sgblack@eecs.umich.edu latency(p->pio_latency), pioAddr(p->pio_addr) 385643Sgblack@eecs.umich.edu{ 395643Sgblack@eecs.umich.edu // This assumes there's only one I/O APIC in the system 405643Sgblack@eecs.umich.edu id = sys->getNumCPUs(); 415643Sgblack@eecs.umich.edu assert(id <= 0xf); 425643Sgblack@eecs.umich.edu arbId = id; 435643Sgblack@eecs.umich.edu regSel = 0; 445643Sgblack@eecs.umich.edu memset(redirTable, 0, sizeof(RedirTableEntry) * TableSize); 455643Sgblack@eecs.umich.edu} 465643Sgblack@eecs.umich.edu 475643Sgblack@eecs.umich.eduTick 485643Sgblack@eecs.umich.eduX86ISA::I82094AA::read(PacketPtr pkt) 495643Sgblack@eecs.umich.edu{ 505643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 515643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 525643Sgblack@eecs.umich.edu switch(offset) { 535643Sgblack@eecs.umich.edu case 0: 545643Sgblack@eecs.umich.edu pkt->set<uint32_t>(regSel); 555643Sgblack@eecs.umich.edu break; 565643Sgblack@eecs.umich.edu case 16: 575643Sgblack@eecs.umich.edu pkt->set<uint32_t>(readReg(regSel)); 585643Sgblack@eecs.umich.edu break; 595643Sgblack@eecs.umich.edu default: 605643Sgblack@eecs.umich.edu panic("Illegal read from I/O APIC.\n"); 615643Sgblack@eecs.umich.edu } 625643Sgblack@eecs.umich.edu return latency; 635643Sgblack@eecs.umich.edu} 645643Sgblack@eecs.umich.edu 655643Sgblack@eecs.umich.eduTick 665643Sgblack@eecs.umich.eduX86ISA::I82094AA::write(PacketPtr pkt) 675643Sgblack@eecs.umich.edu{ 685643Sgblack@eecs.umich.edu assert(pkt->getSize() == 4); 695643Sgblack@eecs.umich.edu Addr offset = pkt->getAddr() - pioAddr; 705643Sgblack@eecs.umich.edu switch(offset) { 715643Sgblack@eecs.umich.edu case 0: 725643Sgblack@eecs.umich.edu regSel = pkt->get<uint32_t>(); 735643Sgblack@eecs.umich.edu break; 745643Sgblack@eecs.umich.edu case 16: 755643Sgblack@eecs.umich.edu writeReg(regSel, pkt->get<uint32_t>()); 765643Sgblack@eecs.umich.edu break; 775643Sgblack@eecs.umich.edu default: 785643Sgblack@eecs.umich.edu panic("Illegal write to I/O APIC.\n"); 795643Sgblack@eecs.umich.edu } 805643Sgblack@eecs.umich.edu return latency; 815643Sgblack@eecs.umich.edu} 825643Sgblack@eecs.umich.edu 835643Sgblack@eecs.umich.eduvoid 845643Sgblack@eecs.umich.eduX86ISA::I82094AA::writeReg(uint8_t offset, uint32_t value) 855643Sgblack@eecs.umich.edu{ 865643Sgblack@eecs.umich.edu if (offset == 0x0) { 875643Sgblack@eecs.umich.edu id = bits(value, 27, 24); 885643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 895643Sgblack@eecs.umich.edu // The IOAPICVER register is read only. 905643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 915643Sgblack@eecs.umich.edu arbId = bits(value, 27, 24); 925643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 935643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 945643Sgblack@eecs.umich.edu if (offset % 2) { 955643Sgblack@eecs.umich.edu redirTable[index].topDW = value; 965643Sgblack@eecs.umich.edu redirTable[index].topReserved = 0; 975643Sgblack@eecs.umich.edu } else { 985643Sgblack@eecs.umich.edu redirTable[index].bottomDW = value; 995643Sgblack@eecs.umich.edu redirTable[index].bottomReserved = 0; 1005643Sgblack@eecs.umich.edu } 1015643Sgblack@eecs.umich.edu } else { 1025643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1035643Sgblack@eecs.umich.edu } 1045643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1055643Sgblack@eecs.umich.edu "Wrote %#x to I/O APIC register %#x .\n", value, offset); 1065643Sgblack@eecs.umich.edu} 1075643Sgblack@eecs.umich.edu 1085643Sgblack@eecs.umich.eduuint32_t 1095643Sgblack@eecs.umich.eduX86ISA::I82094AA::readReg(uint8_t offset) 1105643Sgblack@eecs.umich.edu{ 1115643Sgblack@eecs.umich.edu uint32_t result = 0; 1125643Sgblack@eecs.umich.edu if (offset == 0x0) { 1135643Sgblack@eecs.umich.edu result = id << 24; 1145643Sgblack@eecs.umich.edu } else if (offset == 0x1) { 1155643Sgblack@eecs.umich.edu result = ((TableSize - 1) << 16) | APICVersion; 1165643Sgblack@eecs.umich.edu } else if (offset == 0x2) { 1175643Sgblack@eecs.umich.edu result = arbId << 24; 1185643Sgblack@eecs.umich.edu } else if (offset >= 0x10 && offset <= (0x10 + TableSize * 2)) { 1195643Sgblack@eecs.umich.edu int index = (offset - 0x10) / 2; 1205643Sgblack@eecs.umich.edu if (offset % 2) { 1215643Sgblack@eecs.umich.edu result = redirTable[index].topDW; 1225643Sgblack@eecs.umich.edu } else { 1235643Sgblack@eecs.umich.edu result = redirTable[index].bottomDW; 1245643Sgblack@eecs.umich.edu } 1255643Sgblack@eecs.umich.edu } else { 1265643Sgblack@eecs.umich.edu warn("Access to undefined I/O APIC register %#x.\n", offset); 1275643Sgblack@eecs.umich.edu } 1285643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1295643Sgblack@eecs.umich.edu "Read %#x from I/O APIC register %#x.\n", result, offset); 1305643Sgblack@eecs.umich.edu return result; 1315643Sgblack@eecs.umich.edu} 1325643Sgblack@eecs.umich.edu 1335643Sgblack@eecs.umich.eduvoid 1345643Sgblack@eecs.umich.eduX86ISA::I82094AA::signalInterrupt(int line) 1355643Sgblack@eecs.umich.edu{ 1365643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Received interrupt %d.\n", line); 1375643Sgblack@eecs.umich.edu assert(line < TableSize); 1385643Sgblack@eecs.umich.edu RedirTableEntry entry = redirTable[line]; 1395643Sgblack@eecs.umich.edu if (entry.mask) { 1405643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Entry was masked.\n"); 1415643Sgblack@eecs.umich.edu return; 1425643Sgblack@eecs.umich.edu } else { 1435643Sgblack@eecs.umich.edu if (entry.destMode == 0) { 1445643Sgblack@eecs.umich.edu DPRINTF(I82094AA, 1455643Sgblack@eecs.umich.edu "Would send interrupt to APIC ID %d.\n", entry.dest); 1465643Sgblack@eecs.umich.edu } else { 1475643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Would send interrupts to APIC IDs:" 1485643Sgblack@eecs.umich.edu "%s%s%s%s%s%s%s%s\n", 1495643Sgblack@eecs.umich.edu bits((int)entry.dest, 0) ? " 0": "", 1505643Sgblack@eecs.umich.edu bits((int)entry.dest, 1) ? " 1": "", 1515643Sgblack@eecs.umich.edu bits((int)entry.dest, 2) ? " 2": "", 1525643Sgblack@eecs.umich.edu bits((int)entry.dest, 3) ? " 3": "", 1535643Sgblack@eecs.umich.edu bits((int)entry.dest, 4) ? " 4": "", 1545643Sgblack@eecs.umich.edu bits((int)entry.dest, 5) ? " 5": "", 1555643Sgblack@eecs.umich.edu bits((int)entry.dest, 6) ? " 6": "", 1565643Sgblack@eecs.umich.edu bits((int)entry.dest, 7) ? " 7": "" 1575643Sgblack@eecs.umich.edu ); 1585643Sgblack@eecs.umich.edu } 1595643Sgblack@eecs.umich.edu switch(entry.deliveryMode) { 1605643Sgblack@eecs.umich.edu case 0: 1615643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: Fixed.\n"); 1625643Sgblack@eecs.umich.edu break; 1635643Sgblack@eecs.umich.edu case 1: 1645643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: Lowest Priority.\n"); 1655643Sgblack@eecs.umich.edu break; 1665643Sgblack@eecs.umich.edu case 2: 1675643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: SMI.\n"); 1685643Sgblack@eecs.umich.edu break; 1695643Sgblack@eecs.umich.edu case 3: 1705643Sgblack@eecs.umich.edu fatal("Tried to use reserved delivery mode " 1715643Sgblack@eecs.umich.edu "for IO APIC entry %d.\n", line); 1725643Sgblack@eecs.umich.edu break; 1735643Sgblack@eecs.umich.edu case 4: 1745643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: NMI.\n"); 1755643Sgblack@eecs.umich.edu break; 1765643Sgblack@eecs.umich.edu case 5: 1775643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: INIT.\n"); 1785643Sgblack@eecs.umich.edu break; 1795643Sgblack@eecs.umich.edu case 6: 1805643Sgblack@eecs.umich.edu fatal("Tried to use reserved delivery mode " 1815643Sgblack@eecs.umich.edu "for IO APIC entry %d.\n", line); 1825643Sgblack@eecs.umich.edu break; 1835643Sgblack@eecs.umich.edu case 7: 1845643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Delivery mode is: ExtINT.\n"); 1855643Sgblack@eecs.umich.edu break; 1865643Sgblack@eecs.umich.edu } 1875643Sgblack@eecs.umich.edu DPRINTF(I82094AA, "Vector is %#x.\n", entry.vector); 1885643Sgblack@eecs.umich.edu } 1895643Sgblack@eecs.umich.edu} 1905643Sgblack@eecs.umich.edu 1915643Sgblack@eecs.umich.eduX86ISA::I82094AA * 1925643Sgblack@eecs.umich.eduI82094AAParams::create() 1935643Sgblack@eecs.umich.edu{ 1945643Sgblack@eecs.umich.edu return new X86ISA::I82094AA(this); 1955643Sgblack@eecs.umich.edu} 196