cmos.cc revision 5827
15390SN/A/* 25390SN/A * Copyright (c) 2004-2005 The Regents of The University of Michigan 35390SN/A * All rights reserved. 45390SN/A * 55390SN/A * Redistribution and use in source and binary forms, with or without 65390SN/A * modification, are permitted provided that the following conditions are 75390SN/A * met: redistributions of source code must retain the above copyright 85390SN/A * notice, this list of conditions and the following disclaimer; 95390SN/A * redistributions in binary form must reproduce the above copyright 105390SN/A * notice, this list of conditions and the following disclaimer in the 115390SN/A * documentation and/or other materials provided with the distribution; 125390SN/A * neither the name of the copyright holders nor the names of its 135390SN/A * contributors may be used to endorse or promote products derived from 145390SN/A * this software without specific prior written permission. 155390SN/A * 165390SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 175390SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 185390SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 195390SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 205390SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 215390SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 225390SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 235390SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 245390SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 255390SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 265390SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 275390SN/A * 285390SN/A * Authors: Gabe Black 295390SN/A */ 305390SN/A 315629Sgblack@eecs.umich.edu#include "dev/x86/cmos.hh" 325634Sgblack@eecs.umich.edu#include "dev/x86/intdev.hh" 335390SN/A#include "mem/packet_access.hh" 345390SN/A 355632Sgblack@eecs.umich.eduvoid 365632Sgblack@eecs.umich.eduX86ISA::Cmos::X86RTC::handleEvent() 375632Sgblack@eecs.umich.edu{ 385634Sgblack@eecs.umich.edu assert(intPin); 395827Sgblack@eecs.umich.edu intPin->raise(); 405827Sgblack@eecs.umich.edu //XXX This is a hack. 415827Sgblack@eecs.umich.edu intPin->lower(); 425632Sgblack@eecs.umich.edu} 435632Sgblack@eecs.umich.edu 445390SN/ATick 455390SN/AX86ISA::Cmos::read(PacketPtr pkt) 465390SN/A{ 475390SN/A assert(pkt->getSize() == 1); 485629Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 495390SN/A { 505390SN/A case 0x0: 515390SN/A pkt->set(address); 525390SN/A break; 535390SN/A case 0x1: 545390SN/A pkt->set(readRegister(address)); 555390SN/A break; 565390SN/A default: 575390SN/A panic("Read from undefined CMOS port.\n"); 585390SN/A } 595390SN/A return latency; 605390SN/A} 615390SN/A 625390SN/ATick 635390SN/AX86ISA::Cmos::write(PacketPtr pkt) 645390SN/A{ 655390SN/A assert(pkt->getSize() == 1); 665629Sgblack@eecs.umich.edu switch(pkt->getAddr() - pioAddr) 675390SN/A { 685390SN/A case 0x0: 695390SN/A address = pkt->get<uint8_t>(); 705390SN/A break; 715390SN/A case 0x1: 725390SN/A writeRegister(address, pkt->get<uint8_t>()); 735390SN/A break; 745390SN/A default: 755390SN/A panic("Write to undefined CMOS port.\n"); 765390SN/A } 775390SN/A return latency; 785390SN/A} 795390SN/A 805390SN/Auint8_t 815390SN/AX86ISA::Cmos::readRegister(uint8_t reg) 825390SN/A{ 835390SN/A assert(reg < numRegs); 845629Sgblack@eecs.umich.edu uint8_t val; 855393SN/A if (reg <= 0xD) { 865629Sgblack@eecs.umich.edu val = rtc.readData(reg); 875629Sgblack@eecs.umich.edu DPRINTF(CMOS, 885629Sgblack@eecs.umich.edu "Reading CMOS RTC reg %x as %x.\n", reg, val); 895393SN/A } else { 905629Sgblack@eecs.umich.edu val = regs[reg]; 915629Sgblack@eecs.umich.edu DPRINTF(CMOS, 925629Sgblack@eecs.umich.edu "Reading non-volitile CMOS address %x as %x.\n", reg, val); 935390SN/A } 945629Sgblack@eecs.umich.edu return val; 955390SN/A} 965390SN/A 975390SN/Avoid 985390SN/AX86ISA::Cmos::writeRegister(uint8_t reg, uint8_t val) 995390SN/A{ 1005390SN/A assert(reg < numRegs); 1015393SN/A if (reg <= 0xD) { 1025629Sgblack@eecs.umich.edu DPRINTF(CMOS, "Writing CMOS RTC reg %x with %x.\n", 1035629Sgblack@eecs.umich.edu reg, val); 1045393SN/A rtc.writeData(reg, val); 1055393SN/A } else { 1065629Sgblack@eecs.umich.edu DPRINTF(CMOS, "Writing non-volitile CMOS address %x with %x.\n", 1075629Sgblack@eecs.umich.edu reg, val); 1085629Sgblack@eecs.umich.edu regs[reg] = val; 1095390SN/A } 1105390SN/A} 1115629Sgblack@eecs.umich.edu 1125629Sgblack@eecs.umich.eduX86ISA::Cmos * 1135629Sgblack@eecs.umich.eduCmosParams::create() 1145629Sgblack@eecs.umich.edu{ 1155629Sgblack@eecs.umich.edu return new X86ISA::Cmos(this); 1165629Sgblack@eecs.umich.edu} 117