Pc.py revision 5638:dc073dc6358b 
1# Copyright (c) 2008 The Regents of The University of Michigan
2# All rights reserved.
3#
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5# modification, are permitted provided that the following conditions are
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8# redistributions in binary form must reproduce the above copyright
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14#
15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26#
27# Authors: Gabe Black
28
29from m5.params import *
30from m5.proxy import *
31
32from Device import IsaFake
33from Pci import PciConfigAll
34from Platform import Platform
35from SouthBridge import SouthBridge
36from Terminal import Terminal
37from Uart import Uart8250
38
39def x86IOAddress(port):
40    IO_address_space_base = 0x8000000000000000
41    return IO_address_space_base + port;
42
43class Pc(Platform):
44    type = 'Pc'
45    system = Param.System(Parent.any, "system")
46
47    pciconfig = PciConfigAll()
48
49    south_bridge = SouthBridge()
50
51    # "Non-existant" port used for timing purposes by the linux kernel
52    i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1)
53
54    # Ports behind the pci config and data regsiters. These don't do anything,
55    # but the linux kernel fiddles with them anway.
56    behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8)
57
58    # Serial port and terminal
59    terminal = Terminal()
60    com_1 = Uart8250()
61    com_1.pio_addr = x86IOAddress(0x3f8)
62    com_1.terminal = terminal
63
64    def attachIO(self, bus):
65        self.south_bridge.attachIO(bus)
66        self.i_dont_exist.pio = bus.port
67        self.behind_pci.pio = bus.port
68        self.com_1.pio = bus.port
69        self.pciconfig.pio = bus.default
70        bus.responder_set = True
71        bus.responder = self.pciconfig
72