Pc.py revision 7523
15389SN/A# Copyright (c) 2008 The Regents of The University of Michigan 25389SN/A# All rights reserved. 35389SN/A# 45389SN/A# Redistribution and use in source and binary forms, with or without 55389SN/A# modification, are permitted provided that the following conditions are 65389SN/A# met: redistributions of source code must retain the above copyright 75389SN/A# notice, this list of conditions and the following disclaimer; 85389SN/A# redistributions in binary form must reproduce the above copyright 95389SN/A# notice, this list of conditions and the following disclaimer in the 105389SN/A# documentation and/or other materials provided with the distribution; 115389SN/A# neither the name of the copyright holders nor the names of its 125389SN/A# contributors may be used to endorse or promote products derived from 135389SN/A# this software without specific prior written permission. 145389SN/A# 155389SN/A# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 165389SN/A# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 175389SN/A# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 185389SN/A# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 195389SN/A# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 205389SN/A# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 215389SN/A# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 225389SN/A# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 235389SN/A# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 245389SN/A# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 255389SN/A# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 265389SN/A# 275389SN/A# Authors: Gabe Black 285389SN/A 295389SN/Afrom m5.params import * 305389SN/Afrom m5.proxy import * 315478SN/A 325478SN/Afrom Device import IsaFake 335478SN/Afrom Pci import PciConfigAll 345478SN/Afrom Platform import Platform 355478SN/Afrom SouthBridge import SouthBridge 365478SN/Afrom Terminal import Terminal 375389SN/Afrom Uart import Uart8250 385389SN/A 395389SN/Adef x86IOAddress(port): 405389SN/A IO_address_space_base = 0x8000000000000000 415389SN/A return IO_address_space_base + port; 425389SN/A 435638Sgblack@eecs.umich.educlass Pc(Platform): 445638Sgblack@eecs.umich.edu type = 'Pc' 455389SN/A system = Param.System(Parent.any, "system") 465389SN/A 475389SN/A pciconfig = PciConfigAll() 485389SN/A 495390SN/A south_bridge = SouthBridge() 505390SN/A 515390SN/A # "Non-existant" port used for timing purposes by the linux kernel 525390SN/A i_dont_exist = IsaFake(pio_addr=x86IOAddress(0x80), pio_size=1) 535390SN/A 545447SN/A # Ports behind the pci config and data regsiters. These don't do anything, 555447SN/A # but the linux kernel fiddles with them anway. 565447SN/A behind_pci = IsaFake(pio_addr=x86IOAddress(0xcf8), pio_size=8) 575447SN/A 585478SN/A # Serial port and terminal 595478SN/A terminal = Terminal() 605389SN/A com_1 = Uart8250() 615389SN/A com_1.pio_addr = x86IOAddress(0x3f8) 625478SN/A com_1.terminal = terminal 635389SN/A 645816Sgblack@eecs.umich.edu # Devices to catch access to non-existant serial ports. 655816Sgblack@eecs.umich.edu fake_com_2 = IsaFake(pio_addr=x86IOAddress(0x2f8), pio_size=8) 665816Sgblack@eecs.umich.edu fake_com_3 = IsaFake(pio_addr=x86IOAddress(0x3e8), pio_size=8) 675816Sgblack@eecs.umich.edu fake_com_4 = IsaFake(pio_addr=x86IOAddress(0x2e8), pio_size=8) 685816Sgblack@eecs.umich.edu 695817Sgblack@eecs.umich.edu # A device to catch accesses to the non-existant floppy controller. 705833Sgblack@eecs.umich.edu fake_floppy = IsaFake(pio_addr=x86IOAddress(0x3f2), pio_size=2) 715817Sgblack@eecs.umich.edu 725389SN/A def attachIO(self, bus): 735636SN/A self.south_bridge.attachIO(bus) 745390SN/A self.i_dont_exist.pio = bus.port 755447SN/A self.behind_pci.pio = bus.port 765389SN/A self.com_1.pio = bus.port 775816Sgblack@eecs.umich.edu self.fake_com_2.pio = bus.port 785816Sgblack@eecs.umich.edu self.fake_com_3.pio = bus.port 795816Sgblack@eecs.umich.edu self.fake_com_4.pio = bus.port 805817Sgblack@eecs.umich.edu self.fake_floppy.pio = bus.port 815389SN/A self.pciconfig.pio = bus.default 827523Ssteve.reinhardt@amd.com bus.use_default_range = True 83