11722SN/A/* $OpenBSD: wdcreg.h,v 1.13 2004/09/24 07:05:44 grange Exp $ */ 21722SN/A/* $NetBSD: wdcreg.h,v 1.22 1999/03/07 14:02:54 bouyer Exp $ */ 31722SN/A 41722SN/A/*- 58332SN/A * Copyright (c) 1991 The Regents of the University of California 68332SN/A * All rights reserved 71722SN/A * 81722SN/A * This code is derived from software contributed to Berkeley by 91722SN/A * William Jolitz. 101722SN/A * 111722SN/A * Redistribution and use in source and binary forms, with or without 121722SN/A * modification, are permitted provided that the following conditions 131722SN/A * are met: 141722SN/A * 1. Redistributions of source code must retain the above copyright 151722SN/A * notice, this list of conditions and the following disclaimer. 161722SN/A * 2. Redistributions in binary form must reproduce the above copyright 171722SN/A * notice, this list of conditions and the following disclaimer in the 181722SN/A * documentation and/or other materials provided with the distribution. 191722SN/A * 3. Neither the name of the University nor the names of its contributors 201722SN/A * may be used to endorse or promote products derived from this software 211722SN/A * without specific prior written permission. 221722SN/A * 231722SN/A * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 241722SN/A * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 251722SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 261722SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 271722SN/A * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 281722SN/A * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 291722SN/A * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 301722SN/A * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 311722SN/A * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 321722SN/A * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 331722SN/A * SUCH DAMAGE. 341722SN/A * 351722SN/A * @(#)wdreg.h 7.1 (Berkeley) 5/9/91 361722SN/A */ 371722SN/A 381722SN/A#ifndef _DEV_IC_WDCREG_H_ 391722SN/A#define _DEV_IC_WDCREG_H_ 401722SN/A 411722SN/A/* 421722SN/A * Controller register (wdr_ctlr) 431722SN/A */ 441722SN/A#define WDCTL_4BIT 0x08 /* use four head bits (wd1003) */ 451722SN/A#define WDCTL_RST 0x04 /* reset the controller */ 461722SN/A#define WDCTL_IDS 0x02 /* disable controller interrupts */ 471722SN/A 481722SN/A/* 491722SN/A * Status bits. 501722SN/A */ 511722SN/A#define WDCS_BSY 0x80 /* busy */ 521722SN/A#define WDCS_DRDY 0x40 /* drive ready */ 531722SN/A#define WDCS_DWF 0x20 /* drive write fault */ 541722SN/A#define WDCS_DSC 0x10 /* drive seek complete */ 551722SN/A#define WDCS_DRQ 0x08 /* data request */ 561722SN/A#define WDCS_CORR 0x04 /* corrected data */ 571722SN/A#define WDCS_IDX 0x02 /* index */ 581722SN/A#define WDCS_ERR 0x01 /* error */ 591722SN/A#define WDCS_BITS "\020\010BSY\007DRDY\006DWF\005DSC\004DRQ\003CORR\002IDX\001ERR" 601722SN/A 611722SN/A/* 621722SN/A * Error bits. 631722SN/A */ 641722SN/A#define WDCE_BBK 0x80 /* bad block detected */ 651722SN/A#define WDCE_CRC 0x80 /* CRC error (Ultra-DMA only) */ 661722SN/A#define WDCE_UNC 0x40 /* uncorrectable data error */ 671722SN/A#define WDCE_MC 0x20 /* media changed */ 681722SN/A#define WDCE_IDNF 0x10 /* id not found */ 691722SN/A#define WDCE_MCR 0x08 /* media change requested */ 701722SN/A#define WDCE_ABRT 0x04 /* aborted command */ 711722SN/A#define WDCE_TK0NF 0x02 /* track 0 not found */ 721722SN/A#define WDCE_AMNF 0x01 /* address mark not found */ 731722SN/A 741722SN/A/* 751722SN/A * Commands for Disk Controller. 761722SN/A */ 771722SN/A#define WDCC_NOP 0x00 /* NOP - Always fail with "aborted command" */ 781722SN/A#define WDCC_RECAL 0x10 /* disk restore code -- resets cntlr */ 791722SN/A 801722SN/A#define WDCC_READ 0x20 /* disk read code */ 811722SN/A#define WDCC_WRITE 0x30 /* disk write code */ 821722SN/A#define WDCC__LONG 0x02 /* modifier -- access ecc bytes */ 831722SN/A#define WDCC__NORETRY 0x01 /* modifier -- no retrys */ 841722SN/A 851722SN/A#define WDCC_FORMAT 0x50 /* disk format code */ 861722SN/A#define WDCC_DIAGNOSE 0x90 /* controller diagnostic */ 871722SN/A#define WDCC_IDP 0x91 /* initialize drive parameters */ 881722SN/A 891722SN/A#define WDCC_READMULTI 0xc4 /* read multiple */ 901722SN/A#define WDCC_WRITEMULTI 0xc5 /* write multiple */ 911722SN/A#define WDCC_SETMULTI 0xc6 /* set multiple mode */ 921722SN/A 931722SN/A#define WDCC_READDMA 0xc8 /* read with DMA */ 941722SN/A#define WDCC_WRITEDMA 0xca /* write with DMA */ 951722SN/A 961722SN/A#define WDCC_ACKMC 0xdb /* acknowledge media change */ 971722SN/A#define WDCC_LOCK 0xde /* lock drawer */ 981722SN/A#define WDCC_UNLOCK 0xdf /* unlock drawer */ 991722SN/A 1001722SN/A#define WDCC_FLUSHCACHE 0xe7 /* Flush cache */ 1011722SN/A#define WDCC_IDENTIFY 0xec /* read parameters from controller */ 1021722SN/A#define SET_FEATURES 0xef /* set features */ 1031722SN/A 1041722SN/A#define WDCC_IDLE 0xe3 /* set idle timer & enter idle mode */ 1051722SN/A#define WDCC_IDLE_IMMED 0xe1 /* enter idle mode */ 1061722SN/A#define WDCC_SLEEP 0xe6 /* enter sleep mode */ 1071722SN/A#define WDCC_STANDBY 0xe2 /* set standby timer & enter standby mode */ 1081722SN/A#define WDCC_STANDBY_IMMED 0xe0 /* enter standby mode */ 1091722SN/A#define WDCC_CHECK_PWR 0xe5 /* check power mode */ 1101722SN/A 1111722SN/A#define WDCC_READ_EXT 0x24 /* read 48-bit addressing */ 1121722SN/A#define WDCC_WRITE_EXT 0x34 /* write 48-bit addressing */ 1131722SN/A 1141722SN/A#define WDCC_READMULTI_EXT 0x29 /* read multiple 48-bit addressing */ 1151722SN/A#define WDCC_WRITEMULTI_EXT 0x39 /* write multiple 48-bit addressing */ 1161722SN/A 1171722SN/A#define WDCC_READDMA_EXT 0x25 /* read 48-bit addressing with DMA */ 1181722SN/A#define WDCC_WRITEDMA_EXT 0x35 /* write 48-bit addressing with DMA */ 1191722SN/A 1201722SN/A#define WDCC_FLUSHCACHE_EXT 0xea /* 48-bit addressing flush cache */ 1211722SN/A 1221722SN/A/* Subcommands for SET_FEATURES (features register ) */ 1231722SN/A#define WDSF_8BIT_PIO_EN 0x01 /* Enable 8bit PIO (CFA featureset) */ 1241722SN/A#define WDSF_EN_WR_CACHE 0x02 1251722SN/A#define WDSF_SET_MODE 0x03 1261722SN/A#define WDSF_REASSIGN_EN 0x04 /* Obsolete in ATA-6 */ 1271722SN/A#define WDSF_APM_EN 0x05 /* Enable Adv. Power Management */ 1281722SN/A#define WDSF_PUIS_EN 0x06 /* Enable Power-Up In Standby */ 1291722SN/A#define WDSF_PUIS_SPINUP 0x07 /* Power-Up In Standby spin-up */ 1301722SN/A#define WDSF_CFA_MODE1_EN 0x0A /* Enable CFA power mode 1 */ 1311722SN/A#define WDSF_RMSN_DS 0x31 /* Disable Removable Media Status */ 1321722SN/A#define WDSF_RETRY_DS 0x33 /* Obsolete in ATA-6 */ 1331722SN/A#define WDSF_AAM_EN 0x42 /* Enable Autom. Acoustic Management */ 1341722SN/A#define WDSF_SET_CACHE_SGMT 0x54 /* Obsolete in ATA-6 */ 1351722SN/A#define WDSF_READAHEAD_DS 0x55 /* Disable read look-ahead */ 1361722SN/A#define WDSF_RLSE_EN 0x5D /* Enable release interrupt */ 1371722SN/A#define WDSF_SRV_EN 0x5E /* Enable SERVICE interrupt */ 1381722SN/A#define WDSF_POD_DS 0x66 1391722SN/A#define WDSF_ECC_DS 0x77 1401722SN/A#define WDSF_8BIT_PIO_DS 0x81 /* Disable 8bit PIO (CFA featureset) */ 1411722SN/A#define WDSF_WRITE_CACHE_DS 0x82 1421722SN/A#define WDSF_REASSIGN_DS 0x84 1431722SN/A#define WDSF_APM_DS 0x85 /* Disable Adv. Power Management */ 1441722SN/A#define WDSF_PUIS_DS 0x86 /* Disable Power-Up In Standby */ 1451722SN/A#define WDSF_ECC_EN 0x88 1461722SN/A#define WDSF_CFA_MODE1_DS 0x8A /* Disable CFA power mode 1 */ 1471722SN/A#define WDSF_RMSN_EN 0x95 /* Enable Removable Media Status */ 1481722SN/A#define WDSF_RETRY_EN 0x99 /* Obsolete in ATA-6 */ 1491722SN/A#define WDSF_SET_CURRENT 0x9A /* Obsolete in ATA-6 */ 1501722SN/A#define WDSF_READAHEAD_EN 0xAA 1511722SN/A#define WDSF_PREFETCH_SET 0xAB /* Obsolete in ATA-6 */ 1521722SN/A#define WDSF_AAM_DS 0xC2 /* Disable Autom. Acoustic Management */ 1531722SN/A#define WDSF_POD_EN 0xCC 1541722SN/A#define WDSF_RLSE_DS 0xDD /* Disable release interrupt */ 1551722SN/A#define WDSF_SRV_DS 0xDE /* Disable SERVICE interrupt */ 1561722SN/A#define WDSF_READ_NATIVE_MAX 0xF8 1571722SN/A#define WDSF_SEEK 0x70 1581722SN/A#define WDSF_VERIFY 0x40 1591722SN/A 1601722SN/A/* parameters uploaded to device/heads register */ 1611722SN/A#define WDSD_IBM 0xa0 /* forced to 512 byte sector, ecc */ 1621722SN/A#define WDSD_CHS 0x00 /* cylinder/head/sector addressing */ 1631722SN/A#define WDSD_LBA 0x40 /* logical block addressing */ 1641722SN/A 1651722SN/A/* Commands for ATAPI devices */ 1661722SN/A#define ATAPI_CHECK_POWER_MODE 0xe5 1671722SN/A#define ATAPI_EXEC_DRIVE_DIAGS 0x90 1681722SN/A#define ATAPI_IDLE_IMMEDIATE 0xe1 1691722SN/A#define ATAPI_NOP 0x00 1701722SN/A#define ATAPI_PKT_CMD 0xa0 1711722SN/A#define ATAPI_IDENTIFY_DEVICE 0xa1 1721722SN/A#define ATAPI_SOFT_RESET 0x08 1731722SN/A#define ATAPI_DEVICE_RESET 0x08 /* ATA/ATAPI-5 name for soft reset */ 1741722SN/A#define ATAPI_SLEEP 0xe6 1751722SN/A#define ATAPI_STANDBY_IMMEDIATE 0xe0 1761722SN/A#define ATAPI_SMART 0xB0 /* SMART operations */ 1771722SN/A#define ATAPI_SETMAX 0xF9 /* Set Max Address */ 1781722SN/A#define ATAPI_WRITEEXT 0x34 /* Write sectors Ext */ 1791722SN/A#define ATAPI_SETMAXEXT 0x37 /* Set Max Address Ext */ 1801722SN/A#define ATAPI_WRITEMULTIEXT 0x39 /* Write Multi Ext */ 1811722SN/A 1821722SN/A/* Bytes used by ATAPI_PACKET_COMMAND ( feature register) */ 1831722SN/A#define ATAPI_PKT_CMD_FTRE_DMA 0x01 1841722SN/A#define ATAPI_PKT_CMD_FTRE_OVL 0x02 1851722SN/A 1861722SN/A/* ireason */ 1871722SN/A#define WDCI_CMD 0x01 /* command(1) or data(0) */ 1881722SN/A#define WDCI_IN 0x02 /* transfer to(1) or from(0) the host */ 1891722SN/A#define WDCI_RELEASE 0x04 /* bus released until completion */ 1901722SN/A 1911722SN/A#define PHASE_CMDOUT (WDCS_DRQ | WDCI_CMD) 1921722SN/A#define PHASE_DATAIN (WDCS_DRQ | WDCI_IN) 1931722SN/A#define PHASE_DATAOUT WDCS_DRQ 1941722SN/A#define PHASE_COMPLETED (WDCI_IN | WDCI_CMD) 1951722SN/A#define PHASE_ABORTED 0 1961722SN/A 1971722SN/A#endif /* !_DEV_IC_WDCREG_H_ */ 198