ide_disk.hh revision 864 
1/*
2 * Copyright (c) 2003 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29/** @file
30 * Device model for an IDE disk
31 */
32
33#ifndef __IDE_DISK_HH__
34#define __IDE_DISK_HH__
35
36#include "dev/ide.hh"
37#include "dev/disk_image.hh"
38#include "dev/io_device.hh"
39#include "sim/eventq.hh"
40
41#define DMA_BACKOFF_PERIOD 200
42
43#define MAX_DMA_SIZE (131072) // 256 * SectorSize (512)
44#define MAX_MULTSECT (128)
45
46#define PRD_BASE_MASK  0xfffffffe
47#define PRD_COUNT_MASK 0xfffe
48#define PRD_EOT_MASK   0x8000
49
50typedef struct PrdEntry {
51    uint32_t baseAddr;
52    uint16_t byteCount;
53    uint16_t endOfTable;
54} PrdEntry_t;
55
56class PrdTableEntry {
57  public:
58    PrdEntry_t entry;
59
60    uint32_t getBaseAddr()
61    {
62        return (entry.baseAddr & PRD_BASE_MASK);
63    }
64
65    uint16_t getByteCount()
66    {
67        return ((entry.byteCount == 0) ? MAX_DMA_SIZE :
68                (entry.byteCount & PRD_COUNT_MASK));
69    }
70
71    uint16_t getEOT()
72    {
73        return (entry.endOfTable & PRD_EOT_MASK);
74    }
75};
76
77#define DATA_OFFSET     (0)
78#define ERROR_OFFSET    (1)
79#define FEATURES_OFFSET (1)
80#define NSECTOR_OFFSET  (2)
81#define SECTOR_OFFSET   (3)
82#define LCYL_OFFSET     (4)
83#define HCYL_OFFSET     (5)
84#define SELECT_OFFSET   (6)
85#define STATUS_OFFSET   (7)
86#define COMMAND_OFFSET  (7)
87
88#define CONTROL_OFFSET  (2)
89#define ALTSTAT_OFFSET  (2)
90
91#define SELECT_DEV_BIT  0x10
92#define CONTROL_RST_BIT 0x04
93#define CONTROL_IEN_BIT 0x02
94#define STATUS_BSY_BIT  0x80
95#define STATUS_DRDY_BIT 0x40
96#define STATUS_DRQ_BIT  0x08
97#define DRIVE_LBA_BIT   0x40
98
99#define DEV0 (0)
100#define DEV1 (1)
101
102typedef struct CommandReg {
103    uint8_t data0;
104    union {
105        uint8_t data1;
106        uint8_t error;
107        uint8_t features;
108    };
109    uint8_t sec_count;
110    uint8_t sec_num;
111    uint8_t cyl_low;
112    uint8_t cyl_high;
113    union {
114        uint8_t drive;
115        uint8_t head;
116    };
117    union {
118        uint8_t status;
119        uint8_t command;
120    };
121} CommandReg_t;
122
123typedef enum Events {
124    None = 0,
125    Transfer,
126    ReadWait,
127    WriteWait,
128    PrdRead,
129    DmaRead,
130    DmaWrite
131} Events_t;
132
133typedef enum DevAction {
134    ACT_NONE = 0,
135    ACT_CMD_WRITE,
136    ACT_CMD_COMPLETE,
137    ACT_CMD_ERROR,
138    ACT_STAT_READ,
139    ACT_DATA_READY,
140    ACT_DATA_READ_BYTE,
141    ACT_DATA_READ_SHORT,
142    ACT_DATA_WRITE_BYTE,
143    ACT_DATA_WRITE_SHORT,
144    ACT_DMA_READY,
145    ACT_DMA_DONE
146} DevAction_t;
147
148typedef enum DevState {
149    // Device idle
150    Device_Idle_S = 0,
151    Device_Idle_SI,
152    Device_Idle_NS,
153
154    // Non-data commands
155    Command_Execution,
156
157    // PIO data-in (data to host)
158    Prepare_Data_In,
159    Data_Ready_INTRQ_In,
160    Transfer_Data_In,
161
162    // PIO data-out (data from host)
163    Prepare_Data_Out,
164    Data_Ready_INTRQ_Out,
165    Transfer_Data_Out,
166
167    // DMA protocol
168    Prepare_Data_Dma,
169    Transfer_Data_Dma
170} DevState_t;
171
172typedef enum DmaState {
173    Dma_Idle = 0,
174    Dma_Start,
175    Dma_Transfer
176} DmaState_t;
177
178class PhysicalMemory;
179class IdeController;
180
181/**
182 * IDE Disk device model
183 */
184class IdeDisk : public SimObject
185{
186  protected:
187    /** The IDE controller for this disk. */
188    IdeController *ctrl;
189    /** The DMA interface to use for transfers */
190    DMAInterface<Bus> *dmaInterface;
191    /** The image that contains the data of this disk. */
192    DiskImage *image;
193    /** Pointer to physical memory for DMA transfers */
194    PhysicalMemory *physmem;
195
196  protected:
197    /** The disk delay in microseconds. */
198    int diskDelay;
199
200  private:
201    /** Drive identification structure for this disk */
202    struct hd_driveid driveID;
203    /** Data buffer for transfers */
204    uint8_t *dataBuffer;
205    /** Number of bytes left in command data transfer */
206    uint32_t cmdBytesLeft;
207    /** Number of bytes left in DRQ block */
208    uint32_t drqBytesLeft;
209    /** Current sector in access */
210    uint32_t curSector;
211    /** Command block registers */
212    CommandReg_t cmdReg;
213    /** Shadow of the current command code */
214    uint8_t curCommand;
215    /** Interrupt enable bit */
216    bool nIENBit;
217    /** Device state */
218    DevState_t devState;
219    /** Dma state */
220    DmaState_t dmaState;
221    /** Dma transaction is a read */
222    bool dmaRead;
223    /** PRD table base address */
224    uint32_t curPrdAddr;
225    /** PRD entry */
226    PrdTableEntry curPrd;
227    /** Number of bytes transfered by DMA interface for current transfer */
228    uint32_t dmaInterfaceBytes;
229    /** Device ID (master=0/slave=1) */
230    int devID;
231    /** Interrupt pending */
232    bool intrPending;
233
234  public:
235    /**
236     * Create and initialize this Disk.
237     * @param name The name of this disk.
238     * @param img The disk image of this disk.
239     * @param phys Pointer to physical memory
240     * @param id The disk ID (master=0/slave=1)
241     * @param disk_delay The disk delay in milliseconds
242     */
243    IdeDisk(const std::string &name, DiskImage *img, PhysicalMemory *phys,
244            int id, int disk_delay);
245
246    /**
247     * Delete the data buffer.
248     */
249    ~IdeDisk();
250
251    /**
252     * Set the controller for this device
253     * @param c The IDE controller
254     */
255    void setController(IdeController *c, DMAInterface<Bus> *dmaIntr) {
256        if (ctrl) panic("Cannot change the controller once set!\n");
257        ctrl = c;
258        dmaInterface = dmaIntr;
259    }
260
261    // Device register read/write
262    void read(const Addr &offset, bool byte, bool cmdBlk, uint8_t *data);
263    void write(const Addr &offset, bool byte, bool cmdBlk, const uint8_t *data);
264
265    // Start/abort functions
266    void startDma(const uint32_t &prdTableBase);
267    void abortDma();
268
269  private:
270    void startCommand();
271
272    // Interrupt management
273    void intrPost();
274    void intrClear();
275
276    // DMA stuff
277    void doDmaTransfer();
278    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer>;
279    EventWrapper<IdeDisk, &IdeDisk::doDmaTransfer> dmaTransferEvent;
280
281    void doDmaRead();
282    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaRead>;
283    EventWrapper<IdeDisk, &IdeDisk::doDmaRead> dmaReadWaitEvent;
284
285    void doDmaWrite();
286    friend class EventWrapper<IdeDisk, &IdeDisk::doDmaWrite>;
287    EventWrapper<IdeDisk, &IdeDisk::doDmaWrite> dmaWriteWaitEvent;
288
289    void dmaPrdReadDone();
290    friend class EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone>;
291    EventWrapper<IdeDisk, &IdeDisk::dmaPrdReadDone> dmaPrdReadEvent;
292
293    void dmaReadDone();
294    friend class EventWrapper<IdeDisk, &IdeDisk::dmaReadDone>;
295    EventWrapper<IdeDisk, &IdeDisk::dmaReadDone> dmaReadEvent;
296
297    void dmaWriteDone();
298    friend class EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone>;
299    EventWrapper<IdeDisk, &IdeDisk::dmaWriteDone> dmaWriteEvent;
300
301    // Disk image read/write
302    void readDisk(uint32_t sector, uint8_t *data);
303    void writeDisk(uint32_t sector, uint8_t *data);
304
305    // State machine management
306    void updateState(DevAction_t action);
307
308    // Utility functions
309    bool isBSYSet() { return (cmdReg.status & STATUS_BSY_BIT); }
310    bool isIENSet() { return nIENBit; }
311    bool isDEVSelect() { return ((cmdReg.drive & SELECT_DEV_BIT) == devID); }
312
313    void setComplete()
314    {
315        // clear out the status byte
316        cmdReg.status = 0;
317
318        // set the DRDY bit
319        cmdReg.status |= STATUS_DRDY_BIT;
320    }
321
322    uint32_t getLBABase()
323    {
324        return  (Addr)(((cmdReg.head & 0xf) << 24) | (cmdReg.cyl_high << 16) |
325                       (cmdReg.cyl_low << 8) | (cmdReg.sec_num));
326    }
327
328    inline Addr pciToDma(Addr pciAddr);
329
330    uint32_t bytesInDmaPage(Addr curAddr, uint32_t bytesLeft);
331
332    /**
333     * Serialize this object to the given output stream.
334     * @param os The stream to serialize to.
335     */
336    void serialize(std::ostream &os);
337
338    /**
339     * Reconstruct the state of this object from a checkpoint.
340     * @param cp The checkpoint to use.
341     * @param section The section name describing this object.
342     */
343    void unserialize(Checkpoint *cp, const std::string &section);
344};
345
346
347#endif // __IDE_DISK_HH__
348