ide_ctrl.hh revision 849
1/* 2 * Copyright (c) 2003 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/** @file 30 * Simple PCI IDE controller with bus mastering capability 31 */ 32 33#ifndef __IDE_CTRL_HH__ 34#define __IDE_CTRL_HH__ 35 36#include "dev/pcidev.hh" 37#include "dev/pcireg.h" 38#include "dev/io_device.hh" 39 40#define BMIC0 0x0 // Bus master IDE command register 41#define BMIS0 0x2 // Bus master IDE status register 42#define BMIDTP0 0x4 // Bus master IDE descriptor table pointer register 43#define BMIC1 0x8 // Bus master IDE command register 44#define BMIS1 0xa // Bus master IDE status register 45#define BMIDTP1 0xc // Bus master IDE descriptor table pointer register 46 47// Bus master IDE command register bit fields 48#define RWCON 0x08 // Bus master read/write control 49#define SSBM 0x01 // Start/stop bus master 50 51// Bus master IDE status register bit fields 52#define DMA1CAP 0x40 // Drive 1 DMA capable 53#define DMA0CAP 0x20 // Drive 0 DMA capable 54#define IDEINTS 0x04 // IDE Interrupt Status 55#define IDEDMAE 0x02 // IDE DMA error 56#define BMIDEA 0x01 // Bus master IDE active 57 58// IDE Command byte fields 59#define IDE_SELECT_OFFSET (6) 60#define IDE_SELECT_DEV_BIT 0x10 61 62#define IDE_FEATURE_OFFSET IDE_ERROR_OFFSET 63#define IDE_COMMAND_OFFSET IDE_STATUS_OFFSET 64 65// PCI device specific register byte offsets 66#define PCI_IDE_TIMING 0x40 67#define PCI_SLAVE_TIMING 0x44 68#define PCI_UDMA33_CTRL 0x48 69#define PCI_UDMA33_TIMING 0x4a 70 71#define IDETIM (0) 72#define SIDETIM (4) 73#define UDMACTL (5) 74#define UDMATIM (6) 75 76// PCI Command bit fields 77#define BME 0x04 // Bus master function enable 78#define IOSE 0x01 // I/O space enable 79 80typedef enum RegType { 81 COMMAND_BLOCK = 0, 82 CONTROL_BLOCK, 83 BMI_BLOCK 84} RegType_t; 85 86class IdeDisk; 87class IntrControl; 88class PciConfigAll; 89class Tsunami; 90class PhysicalMemory; 91class BaseInterface; 92class HierParams; 93class Bus; 94 95/** 96 * Device model for an Intel PIIX4 IDE controller 97 */ 98 99class IdeController : public PciDev 100{ 101 private: 102 /** Primary command block registers */ 103 Addr pri_cmd_addr; 104 Addr pri_cmd_size; 105 /** Primary control block registers */ 106 Addr pri_ctrl_addr; 107 Addr pri_ctrl_size; 108 /** Secondary command block registers */ 109 Addr sec_cmd_addr; 110 Addr sec_cmd_size; 111 /** Secondary control block registers */ 112 Addr sec_ctrl_addr; 113 Addr sec_ctrl_size; 114 /** Bus master interface (BMI) registers */ 115 Addr bmi_addr; 116 Addr bmi_size; 117 118 private: 119 /** Registers used for bus master interface */ 120 uint8_t bmi_regs[16]; 121 /** Shadows of the device select bit */ 122 uint8_t dev[2]; 123 /** Registers used in PCI configuration */ 124 uint8_t pci_regs[8]; 125 126 // Internal management variables 127 bool io_enabled; 128 bool bm_enabled; 129 bool cmd_in_progress[4]; 130 131 public: 132 /** Pointer to the chipset */ 133 Tsunami *tsunami; 134 135 private: 136 /** IDE disks connected to controller */ 137 IdeDisk *disks[4]; 138 139 private: 140 /** Parse the access address to pass on to device */ 141 void parseAddr(const Addr &addr, Addr &offset, bool &primary, 142 RegType_t &type) 143 { 144 offset = addr; 145 146 if (addr >= pri_cmd_addr && addr < (pri_cmd_addr + pri_cmd_size)) { 147 offset -= pri_cmd_addr; 148 type = COMMAND_BLOCK; 149 primary = true; 150 } else if (addr >= pri_ctrl_addr && 151 addr < (pri_ctrl_addr + pri_ctrl_size)) { 152 offset -= pri_ctrl_addr; 153 type = CONTROL_BLOCK; 154 primary = true; 155 } else if (addr >= sec_cmd_addr && 156 addr < (sec_cmd_addr + sec_cmd_size)) { 157 offset -= sec_cmd_addr; 158 type = COMMAND_BLOCK; 159 primary = false; 160 } else if (addr >= sec_ctrl_addr && 161 addr < (sec_ctrl_addr + sec_ctrl_size)) { 162 offset -= sec_ctrl_addr; 163 type = CONTROL_BLOCK; 164 primary = false; 165 } else if (addr >= bmi_addr && addr < (bmi_addr + bmi_size)) { 166 offset -= bmi_addr; 167 type = BMI_BLOCK; 168 primary = (offset < BMIC1) ? true : false; 169 } else { 170 panic("IDE controller access to invalid address: %#x\n", addr); 171 } 172 }; 173 174 /** Select the disk based on the channel and device bit */ 175 int getDisk(bool primary) 176 { 177 int disk = 0; 178 uint8_t *devBit = &dev[0]; 179 180 if (!primary) { 181 disk += 2; 182 devBit = &dev[1]; 183 } 184 185 disk += *devBit; 186 187 assert(*devBit == 0 || *devBit == 1); 188 189 return disk; 190 }; 191 192 /** Select the disk based on a pointer */ 193 int getDisk(IdeDisk *diskPtr) 194 { 195 for (int i = 0; i < 4; i++) { 196 if ((long)diskPtr == (long)disks[i]) 197 return i; 198 } 199 return -1; 200 } 201 202 public: 203 /** 204 * Constructs and initializes this controller. 205 * @param name The name of this controller. 206 * @param ic The interrupt controller. 207 * @param mmu The memory controller 208 * @param cf PCI config space 209 * @param cd PCI config data 210 * @param bus_num The PCI bus number 211 * @param dev_num The PCI device number 212 * @param func_num The PCI function number 213 * @param host_bus The host bus to connect to 214 * @param hier The hierarchy parameters 215 */ 216 IdeController(const std::string &name, IntrControl *ic, 217 const std::vector<IdeDisk *> &new_disks, 218 MemoryController *mmu, PciConfigAll *cf, 219 PciConfigData *cd, Tsunami *t, 220 uint32_t bus_num, uint32_t dev_num, uint32_t func_num, 221 Bus *host_bus, HierParams *hier); 222 223 /** 224 * Deletes the connected devices. 225 */ 226 ~IdeController(); 227 228 virtual void WriteConfig(int offset, int size, uint32_t data); 229 virtual void ReadConfig(int offset, int size, uint8_t *data); 230 231 void intrPost(); 232 void intrClear(); 233 234 void setDmaComplete(IdeDisk *disk); 235 236 /** 237 * Read a done field for a given target. 238 * @param req Contains the address of the field to read. 239 * @param data Return the field read. 240 * @return The fault condition of the access. 241 */ 242 virtual Fault read(MemReqPtr &req, uint8_t *data); 243 244 /** 245 * Write to the mmapped I/O control registers. 246 * @param req Contains the address to write to. 247 * @param data The data to write. 248 * @return The fault condition of the access. 249 */ 250 virtual Fault write(MemReqPtr &req, const uint8_t *data); 251 252 /** 253 * Cache access timing specific to device 254 * @param req Memory request 255 */ 256 Tick cacheAccess(MemReqPtr &req); 257 258 /** 259 * Serialize this object to the given output stream. 260 * @param os The stream to serialize to. 261 */ 262 virtual void serialize(std::ostream &os); 263 264 /** 265 * Reconstruct the state of this object from a checkpoint. 266 * @param cp The checkpoint use. 267 * @param section The section name of this object 268 */ 269 virtual void unserialize(Checkpoint *cp, const std::string §ion); 270 271}; 272#endif // __IDE_CTRL_HH_ 273